CN104716190B - The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of p type buried layer cover type half - Google Patents
The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of p type buried layer cover type half Download PDFInfo
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- CN104716190B CN104716190B CN201510112078.7A CN201510112078A CN104716190B CN 104716190 B CN104716190 B CN 104716190B CN 201510112078 A CN201510112078 A CN 201510112078A CN 104716190 B CN104716190 B CN 104716190B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000005669 field effect Effects 0.000 title claims abstract description 13
- 238000009792 diffusion process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000002019 doping agent Substances 0.000 claims description 11
- 229910044991 metal oxide Inorganic materials 0.000 claims description 7
- 150000004706 metal oxides Chemical class 0.000 claims description 7
- 238000000407 epitaxy Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 4
- 230000009291 secondary effect Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 3
- 230000008094 contradictory effect Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of p type buried layer cover type half.The present invention discloses a kind of new SJ LDMOS devices.The present invention makes half super junction on N-type substrate epitaxial layer, and introduces p type buried layer on half super interface.Compared with traditional super junction, the present invention has passed through the collective effect of N areas and p type buried layer, compensate for the charge unbalance between super junction NeiNXing Zhu areas and PXing Zhu areas, overcomes substrate secondary effects, improve breakdown voltage；Also, due to being half super junction, an electric field peak is introduced on surface, breakdown voltage is further improved.Meanwhile, p type buried layer can improve the concentration in N areas, and conducting resistance is compared in reduction.It can be seen that being the balance of high-breakdown-voltage, low on-resistance and super junction layer charge the characteristics of the structure.The new SJ LDMOS devices structure that the present invention is provided also has manufacturing process relatively easy, the characteristics of technology difficulty is relatively low.The present invention is more easy to meet the application requirement of power electronic system.
Description
Technical field
The present invention relates to semiconductor power device technology field, and in particular to is a kind of half super-junction laterally double diffused metal oxygen
Compound semiconductor field.
Background technology
Power device is the semiconductor devices for carrying out Power Processing.In frequency conversion, transformation, unsteady flow, power amplification, power management
Had a wide range of applications in terms of constant power processing.The huge advance of modern society's generating, power transmission and power management techniques is returned
The performance enhancement of work(and the power device of the flowing of control electricity.With the development of integrated circuit technique, it is desirable to will be more
Module is made in same chip, to obtain the product of more preferable performance.Due to the critical role of power device, by power device and low pressure
Integrated circuit is made in same chip, is described as second of electronic revolution.
Superjunction (super junction) structure is the NXing Zhu areas and PXing Zhu areas being alternately arranged, if with super-junction structure come
Replace LDMOS drift region, be formed super junction LDMOS, abbreviation SJ-LDMOS.In theory, super-junction structure by NXing Zhu areas and
Charge balance between PXing Zhu areas can obtain high breakdown voltage, and can be with by the NXing Zhu areas and PXing Zhu areas of heavy doping
Very low conducting resistance is obtained, therefore, superjunction devices can be obtained between two key parameters of breakdown voltage and conducting resistance
One compromise well.
But for SJ-LDMOS, due to substrate-assisted depletion NXing Zhu areas (HuoPXing Zhu areas) so that during device breakdown, P
Xing Zhu areas (HuoNXing Zhu areas) can not be completely depleted, breaks the charge balance between LiaoNXing Zhu areas and PXing Zhu areas, reduces SJ-
The lateral breakdown voltage of LDMOS device.
Half super junction, i.e., super interface accounts for half or the part of drift region, for common super junction, increases by one
Electric field peak, so as to improve breakdown voltage, but equally exists the defect of the substrate secondary effects as common superjunction.
The content of the invention
The present invention proposes a kind of super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of p type buried layer cover type half,
To solve the problem of substrate-assisted depletion effect reduces SJ-LDMOS breakdown voltage, and improve breakdown voltage with than leading
The contradictory relation being powered between hindering, realizes high breakdown voltage and low ratio conducting resistance.
The present invention program is as follows：
The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of p type buried layer cover type half, including：
P type substrate；
The p-type base on N-type epitaxy layer surface in the P type substrate；
Positioned at the N-type source region of p-type base part surface；
Half super interface, including NXing Zhu areas and PXing Zhu areas；The N-type bottom auxiliary layer in the half super interface is located at the P
On type substrate the surface of N-type epitaxy layer and with p-type base abut；
Positioned at the N-type drain region of half super interface part surface；
It is characterized in that：
The surface (final form) of N-type bottom auxiliary layer is broadly divided into three parts with difference in height, according to by low
To high order, the surface of Part I for injection the NXing Zhu areas and PXing Zhu areas, more than Part II and half super interface
The surface of lower part is covered with the p-type buried dopant layer abutted with N-type drain region, and Part III is abutted with p-type base, and by p-type base
Area isolates with p-type buried dopant layer.
Based on above scheme, the present invention also further makees following optimization：
The surface of N-type bottom auxiliary layer is that stepped-style embodies the difference in height；It should be appreciated that mentioned here
Stepped-style should broadly understood, that is, be not required for as smooth ladder.
Above-mentioned half super interface is discharged using the horizontal period distances in NXing Zhu areas and PXing Zhu areas, the width in each NXing Zhu area
Identical, the width in each PXing Zhu area is identical.Further, each NXing Zhu areas are preferably also identical with the width in each PXing Zhu areas.
The cross section of aforementioned p-type buried dopant layer is regular figure (it is of course also possible to being irregular figure), with circular or
Rectangle is preferred.
The longitudinal section of aforementioned p-type buried dopant layer is regular figure (it is of course also possible to being irregular figure), with circular or
Rectangle is preferred.
The concentration of aforementioned p-type buried dopant layer is uniform (it is of course also possible to being heterogeneous).
Beneficial effects of the present invention are as follows：
The present invention compensate between super junction NeiNXing Zhu areas and PXing Zhu areas by N areas and the collective effect of p type buried layer
Charge unbalance, overcomes substrate secondary effects, improves breakdown voltage；Also, due to being half super junction, one is introduced on surface
Individual electric field peak, further improves breakdown voltage.Meanwhile, p type buried layer can improve the concentration of drift region, and conducting resistance is compared in reduction.
Therefore the optimization than general scheme breakdown voltage and than conducting resistance can be lifted further.
This programme device is simple to manufacture, and operability is stronger.
Brief description of the drawings
Fig. 1 is the schematic three dimensional views of super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of the present invention.
Fig. 2 is sectional view of the drift region along AOC directions in Fig. 1.
Embodiment
Referring to Fig. 1 and Fig. 2, below with a kind of super-junction laterally bilateral diffusion metal oxide of p type buried layer cover type N-channel half half
Carry out the specific new construction for introducing the present invention exemplified by conductor FET.Those skilled in the art should be realized that, the implementation
Example not limiting the scope of the invention.It includes：
P type substrate 1；
The p-type base 2 on N-type epitaxy layer surface in the P type substrate 1；
Positioned at the N-type source region 7 of the part surface of p-type base 2；
Half super interface, using the horizontal period distances discharge in NXing Zhu areas 4 and PXing Zhu areas 5, (only simplification illustrates one in figure
In the individual cycle, actually generally there is multiple cycles), the width in each NXing Zhu area is identical, and the width in each PXing Zhu area is identical；Enter one
Step, each NXing Zhu areas are preferably also identical with the width in each PXing Zhu areas；The N-type bottom auxiliary layer 3 in the half super interface
Abutted in the surface of N-type epitaxy layer in the P type substrate 1 and with p-type base 2；
Positioned at the N-type drain region 6 of half super interface part surface；
The surface of N-type bottom auxiliary layer 3 is broadly divided into three parts of stepped-style, according to order from low to high,
Inject the NXing Zhu areas and PXing Zhu areas in Part I, the surface of Part II and half super interface remaining part covered with
The p-type buried dopant layer 8 abutted with N-type drain region, Part III and p-type base are abutted, and by p-type base and p-type buried dopant layer every
From.
The preparation method of the super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of aforementioned p-type buried regions cover type half,
Its step includes：
P-type base is formed on the P-type semiconductor substrate epitaxial material；
N-type source region is formed in the p-type base；
N areas are formed in the adjacent position of the Semiconductor substrate and p-type base；
Half super interface is formed in the N areas, includes the NXing Zhu areas and PXing Zhu areas of horizontal period distances discharge；
P type buried layer is formed on described half super interface；
Heavily doped N-type drain region is formed on described half super interface.
The preparation method of the above-mentioned super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of p-type buried regions cover type half,
Its step includes：
P-type base is formed on the P-type semiconductor substrate epitaxial material；
N-type source region is formed in the p-type base；
N areas are formed in the adjacent position of the Semiconductor substrate and p-type base；
Half super interface is formed in the N areas, includes the NXing Zhu areas and PXing Zhu areas of horizontal period distances discharge；
P type buried layer is formed on described half super interface；
Heavily doped N-type drain region is formed on described half super interface.
Specific doping process, has very ripe technology, will not be described in detail herein in the prior art.
Technical scheme, the present invention compensate for N-type post in super junction by N areas and the collective effect of p type buried layer
Charge unbalance between area and PXing Zhu areas, overcomes substrate secondary effects, improves breakdown voltage；Also, due to being half super
Level knot, introduces an electric field peak on surface, further improves breakdown voltage.Meanwhile, p type buried layer can improve the dense of drift region
Conducting resistance is compared in degree, reduction.Hence improve LDMOS breakdown voltage and than the contradictory relation between conducting resistance, therefore be
Realize that integrated technology provides a kind of new device architecture.
Certainly, LDMOS of the invention can also be " P ", " N " relation pair of P-channel, then structure and above N-channel scheme
Adjust, that is, be changed to " N-type substrate ", " N-type base ", " p-type source region ", " p-type drain region " ... and will not be repeated here.Although claim
It is not construed as limiting, it is apparent that the P-channel scheme of such a structure should be considered as to the equivalent of claim, belongs to claim institute table
The scope of patent protection reached.
Claims (6)
- The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of 1.P type buried regions cover type half, including：P type substrate；The p-type base on N-type epitaxy layer surface in the P type substrate；Positioned at the N-type source region of p-type base part surface；Half super interface, including NXing Zhu areas and PXing Zhu areas；The N-type bottom auxiliary layer in the half super interface is served as a contrast positioned at the p-type On bottom the surface of N-type epitaxy layer and with p-type base abut；Positioned at the N-type drain region of half super interface part surface；It is characterized in that：The surface of N-type bottom auxiliary layer is broadly divided into three parts with difference in height, according to order from low to high, first It is the NXing Zhu areas and PXing Zhu areas injected on partial surface, the surface of Part II and half super interface remaining part is covered The p-type buried dopant layer abutted with N-type drain region is stamped, Part III and p-type base are abutted, and by p-type base and p-type buried dopant layer Isolation.
- 2. the super-junction laterally double-diffused metal oxide semiconductor field-effect of p type buried layer cover type half according to claim 1 Pipe, it is characterised in that：The surface of N-type bottom auxiliary layer is that stepped-style embodies the difference in height.
- 3. the super-junction laterally double-diffused metal oxide semiconductor field-effect of p type buried layer cover type half according to claim 1 Pipe, it is characterised in that：The half super interface is discharged using the horizontal period distances in NXing Zhu areas and PXing Zhu areas, each NXing Zhu area Width it is identical, the width in each PXing Zhu area is identical.
- 4. the super-junction laterally double-diffused metal oxide semiconductor field-effect of p type buried layer cover type half according to claim 1 Pipe, it is characterised in that：The cross section and/or longitudinal section of the p-type buried dopant layer are regular figure.
- 5. the super-junction laterally double-diffused metal oxide semiconductor field-effect of p type buried layer cover type half according to claim 4 Pipe, it is characterised in that：The regular figure is circular or rectangle.
- 6. the super-junction laterally double-diffused metal oxide semiconductor field-effect of p type buried layer cover type half according to claim 1 Pipe, it is characterised in that：The concentration of the p-type buried dopant layer is uniform.
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| CN110021655B (en) * | 2019-04-19 | 2021-01-01 | 西安电子科技大学 | Semi-super-junction lateral double-diffusion metal oxide semiconductor field effect transistor with stepped N-type heavy-doping buried layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101819998A (en) * | 2010-04-29 | 2010-09-01 | 哈尔滨工程大学 | High voltage low power consumption SOI LDMOS transistor having strained silicon structure |
| CN102376762A (en) * | 2010-08-26 | 2012-03-14 | 上海华虹Nec电子有限公司 | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
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| US8525261B2 (en) * | 2010-11-23 | 2013-09-03 | Macronix International Co., Ltd. | Semiconductor device having a split gate and a super-junction structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101819998A (en) * | 2010-04-29 | 2010-09-01 | 哈尔滨工程大学 | High voltage low power consumption SOI LDMOS transistor having strained silicon structure |
| CN102376762A (en) * | 2010-08-26 | 2012-03-14 | 上海华虹Nec电子有限公司 | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
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