CN107579119B - Longitudinal super-junction double-diffusion metal oxide semiconductor field effect transistor with composite dielectric layer and manufacturing method thereof - Google Patents
Longitudinal super-junction double-diffusion metal oxide semiconductor field effect transistor with composite dielectric layer and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a Composite Dielectric Layer (CDL) longitudinal super-junction double-diffused metal oxide semiconductor field effect transistor (SJ-VDMOS) and a manufacturing method thereof. When the device is turned off, the SIPOS column and the High K dielectric layer have uniform electric fields, and the electric fields in the super junction drift region of the device are uniformly distributed through electric field modulation. Meanwhile, the composite dielectric layer and the super junction jointly assist in depleting the super junction drift region, so that the depletion capability of the super junction drift region is greatly improved, the doping concentration of the drift region of the device is increased, and the on-resistance of the device is reduced. When the device is started, the side wall of the drift region is provided with a majority carrier accumulation layer, so that the on-resistance of the device is further reduced.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a Trench (Trench) type longitudinal double-diffusion metal oxide semiconductor field effect transistor.
Background
As power MOSFET devices represent new power semiconductor devices and are rapidly developed, power semiconductor devices are widely used in the fields of computers, lighting, consumer electronics, automotive electronics, industrial drives, and the like. The power semiconductor device is a core device with green, low power consumption, energy conservation and environmental protection. For high voltage MOSFETs, the energy efficient requirement of the power supply is a major factor affecting the future development of the product. However, in the high-voltage application field of the power device, the thickness of the power VDMOS epitaxial layer is continuously increased along with the increase of the breakdown voltage of the device, and the doping concentration of the drift region is gradually reduced, so that the on-resistance of the device is sharply increased along with 2.5 times of the breakdown voltage of the device, and the on-loss of the device is increased. In 1998, chen xingbi academy and the like put forward a new structure theory of a longitudinal voltage-resisting layer and break through the traditional silicon limit theory, namely a voltage-resisting structure which is called super junction in the future. The drift region is mutually compensated by a series of N regions and P regions which are alternately doped with high concentration by utilizing the charge compensation theory, so that the concentration of the drift region of the device is improved by one order of magnitude. The condition satisfied by the super junction charge compensation is formula (1)
It can be known that under a certain width of the N column, the maximum value of the doping concentration of the N column is determined, that is, the doping concentration of the super junction drift region is limited, thereby affecting the conduction loss of the device.
Disclosure of Invention
The invention provides a longitudinal super-junction double-diffusion metal oxide semiconductor field effect transistor with a composite dielectric layer, and aims to optimize the contradiction relationship between the breakdown voltage and the specific on-resistance of the traditional VDMOS device.
The technical scheme of the invention is as follows:
a longitudinal super junction double-diffusion metal oxide semiconductor field effect transistor with a composite dielectric layer comprises:
a substrate of semiconductor material, also serving as a drain region;
a super junction drift region epitaxially formed on the substrate; the widths and doping concentrations of an N column and a P column of the super junction drift region meet the charge balance condition;
a left base region and a right base region which are formed by further extending and doping are formed above the super junction drift region;
doping the upper part of the base region to form a source region and a channel substrate contact respectively;
a source electrode formed on the upper surface of the source region and the channel substrate contact;
a drain electrode formed on the lower surface of the drain region;
the difference from the existing VDMOS is that:
the substrate and the super-junction drift region are made of element semiconductor materials, a groove is formed between the left base region and the right base region in an etching mode, and the groove penetrates through the super-junction drift region to the drain region along the longitudinal direction; the depth-to-width ratio of the trench is determined according to the length of a super junction drift region of the device, and the length of the super junction drift region is determined according to the requirement of breakdown voltage; sequentially forming a gate insulating layer and a semi-insulating polycrystalline silicon layer doped with oxygen on the side wall of the groove, and connecting the two longitudinal ends of the semi-insulating polycrystalline silicon layer with the two ends of a gate drain of the device; the longitudinal surface of the semi-insulating polycrystalline silicon layer corresponding to the base region is a heavily doped region, and a grid electrode is formed in the heavily doped region;
and filling a High K dielectric layer in the groove with the surface becoming a semi-insulating polycrystalline silicon layer, wherein the longitudinal area of the High K dielectric layer is equivalent to the area of the super-junction drift region, and the semi-insulating polycrystalline silicon layer and the High K dielectric layer jointly form a composite dielectric layer.
On the basis of the scheme, the invention is optimized as follows:
the High K material has a relative dielectric constant of 100 to 2000.
The width of the High K dielectric in the transverse direction (namely the width of the groove with the surface becoming the semi-insulating polycrystalline silicon layer) is 0.2-5 μm.
The thickness of the gate insulating layer is set according to the threshold voltage of the device, and is typically 0.02 to 0.1 μm.
When the breakdown voltage is 600V, the thickness of the super junction drift region (namely the length of the super junction drift region) is 25-50 μm.
The doping concentration of the substrate of semiconductor material is typical of the doping concentration of the substrate of elemental semiconductor material and is generally 1 x 1013cm-3～1×1015cm-3。
P-pillar width W in the super junction drift regionPWidth W of column NNThe proportion of (A) is set according to the device characteristics and the process conditions, and the typical value is 1/1-5/1; doping concentration N of N columnDDoping concentration N with P columnAThe ratio of (A) is set according to device characteristics and process conditions, and the typical value range is 2/1-10/1.
When the breakdown voltage requires 600V, the depth-to-width ratio of the trench is 15: 1-20: 1; when the breakdown voltage requires 200V, the depth-to-width ratio of the trench is 3:1-8: 1.
The thickness of the semi-insulating polycrystalline silicon layer is 0.2-1.5 mu m; the oxygen doping proportion of the semi-insulating polysilicon layer is 15-35%, and the corresponding resistivity is 109～1011Ω·cm。
Semi-insulatingThe heavily doped region in the silicon crystal layer has a doping concentration of 1018～1020cm-3。
A method for manufacturing the longitudinal super junction double-diffusion metal oxide semiconductor field effect transistor with the composite dielectric layer element semiconductor comprises the following steps:
1) taking a substrate of element semiconductor material (including silicon material, germanium material and other first generation semiconductor materials),
simultaneously, the silicon nitride serves as a drain region;
2) forming a super junction drift region on the substrate in an epitaxial manner;
3) forming a base region on the upper part of the drift region by ion implantation or diffusion;
4) etching a groove in the base region to enable the groove to penetrate through the drift region downwards to the drain region;
5) forming a gate insulating layer on the trench sidewall;
6) depositing a semi-insulating polysilicon layer outside the gate insulating layer and doping oxygen;
7) filling a High K material in a region which corresponds to the drift region in the trench in the longitudinal direction;
8) doping on the base region to form a source region and a channel substrate contact;
9) heavily doping the region of the surface of the semi-insulating polycrystalline silicon layer in the groove, which longitudinally corresponds to the base region, and depositing polycrystalline silicon to form a grid electrode;
10) forming a source electrode on the contact surface of the source region and the channel substrate;
11) and forming a drain electrode on the surface of the drain region.
The technical scheme of the invention has the following beneficial effects:
and forming a semi-insulating polysilicon (SIPOS) layer on the side wall of the drift region of the VDMOS device by utilizing a deep trench technology, so that two ends of the SIPOS layer are respectively connected with a gate electrode and a drain electrode of the device (the connection to the drain region can be regarded as being connected with the drain electrode). The intermediate space part of the SIPOS layer is filled with a High K material. The composite dielectric layer composed of SIPOS and High K has three effects on SJ-VDMOS, firstly, the composite dielectric layer and the super-junction drift region form a metal-insulator-semiconductor (MIS) capacitor structure, when the device is turned off, because the two ends of the MIS capacitor have potential difference, the capacitor is used up the super-junction drift region in an auxiliary mode, the doping concentration of the N-type drift region can be effectively increased, and the on-resistance of the device can be reduced; secondly, the composite dielectric layer is provided with a uniform electric field, and the electric field on the super junction drift region of the device is uniformly distributed through an electric field modulation effect; when the device is in an on state, the surface of the super-junction drift region of the composite dielectric layer has a potential difference, so that a majority carrier accumulation layer is formed on the super-junction drift region, and the on-resistance of the device is further reduced.
Drawings
Fig. 1 is a schematic structural view (front view) of an embodiment of the present invention, in which the device structure is mirror-symmetrical along the dotted line.
The reference numbers illustrate:
1-a source electrode; 2-a gate insulating layer; 3-semi-insulating polysilicon layer; 4-a gate electrode; 5-High K material; 6-a drain electrode; 7-a drain region; 8-an epitaxial layer N-type drift region; 9-epitaxial layer P type drift region; 10-base region; 11-channel substrate contact; 12-source region.
Detailed Description
As shown in fig. 1, the double-diffused metal oxide semiconductor field effect transistor with a longitudinal super junction of a composite dielectric layer of the invention comprises:
the substrate of elemental semiconducting material, i.e. the drain region 7 of the device, has a doping concentration of 1 x 1013cm-3～1×1015cm-3；
Forming a super junction drift region (an epitaxial layer N-type drift region 8 and an epitaxial layer P-type drift region 9) by carrying out zone epitaxy on the substrate; p column width W in super junction drift regionPWidth W of column NNThe typical value of the ratio of (A) is 1/1-5/1; doping concentration N of N columnDDoping concentration N with P columnAThe typical value of the ratio of (A) is 2/1-10/1.
Further extending and doping on the drift region to form a base region 10;
etching a groove on the base region, wherein the lower part of the groove penetrates through the super junction drift region to reach the substrate drain region; when the breakdown voltage requires 600V, the depth-to-width ratio of the trench is 15: 1-20: 1; when the breakdown voltage requires 200V, the depth-to-width ratio of the trench is 3:1-8: 1;
forming a gate insulating layer 2 with the thickness of 0.02-0.1 mu m on the side wall of the groove;
depositing a semi-insulating polysilicon layer 3 outside the gate insulating layer, wherein the thickness of the semi-insulating polysilicon layer is 0.2-1.5 μm, the oxygen doping ratio is 15% -35%, and the corresponding resistivity is 109～1011Omega cm; the doping concentration of the heavily doped region in the semi-insulating polysilicon layer is 1018～1020cm-3；
Depositing a High K material 5 in the longitudinal drift region in the groove; the relative dielectric constant of the High K material is 100-2000, and the width of the High K medium in the transverse direction is 0.2-5 mu m;
doping the base region to form a source region 12 and a channel substrate contact 11 respectively;
carrying out high-concentration doping above the semi-insulating polycrystalline silicon layer 3 and forming a gate electrode 4;
a source electrode 1 is formed on the source region 11 and the channel substrate contact 12.
And forming a SIPOS field plate on the side wall of the drift region of the element semiconductor SJ-VDMOS device by utilizing a deep trench technology, wherein two ends of the SIPOS field plate are respectively connected with a gate electrode and a drain electrode of the device. The composite dielectric layer composed of SIPOS and High K has three effects, firstly, a metal-insulator-semiconductor (MIS) capacitor structure is formed in a super-junction drift region of the composite dielectric layer, when a device is turned off, because the two ends of the MIS capacitor have potential difference, the capacitor is used for assisting in depleting the super-junction drift region, the doping concentration of an N-type drift region can be effectively increased, and the on-resistance of the device can be reduced; secondly, when the device is turned off, the composite dielectric layer has a uniform electric field, and the electric field on the super junction drift region of the device is uniformly distributed through an electric field modulation effect; when the device is in an on state, the composite dielectric layer and the surface of the super junction drift region of the device have potential difference, so that a majority carrier accumulation layer is formed on the super junction drift region, and the on resistance of the device is further reduced.
Taking an N-channel element semiconductor SJ-VDMOS as an example, the preparation method can be specifically prepared by the following steps:
1) the substrate of the element semiconductor material is used as a drain region;
2) forming N and P columns, namely a super junction drift region, on the substrate drain region in a partition epitaxial mode alternately;
3) further extending and ion injecting or diffusing on the super junction drift region to form a base region;
4) etching a groove on the base region;
5) forming a gate insulating layer on the trench sidewall;
6) depositing a thin SIPOS layer outside the insulating layer;
7) depositing a High K material in the longitudinal drift region in the groove;
8) respectively forming a source region and a channel substrate contact in the base region through ion implantation;
9) carrying out high-concentration doping on the SIPOS layer in the groove, namely in the region outside the base region through ion implantation;
10) depositing polycrystalline silicon in the base region in the groove to form a gate electrode;
11) depositing a passivation layer on the surface of the device, and etching a contact hole;
12) depositing metal and etching to form a source electrode and a gate electrode;
13) and forming a drain electrode on the substrate drain region.
Through Sentaurus simulation, the performance of the novel device provided by the invention is greatly improved compared with that of the traditional device, the on-resistance of the novel device is reduced by 65% under the same breakdown voltage of the two devices, and the limit relation of a VDMOS (vertical double-diffused metal oxide semiconductor) of the traditional super junction of an element semiconductor is broken through.
Of course, the element semiconductor SJ-VDMOS in the present invention may also be a P-type channel, and the structure thereof is equivalent to that of an N-channel SJ-VDMOS, which should be considered as falling within the protection scope of the claims of the present application and will not be described herein again.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions also fall into the protection scope of the present invention.
Claims (10)
1. A longitudinal super junction double-diffusion metal oxide semiconductor field effect transistor with a composite dielectric layer comprises:
a substrate of semiconductor material, also serving as a drain region;
a super junction drift region epitaxially formed on the substrate; the widths and doping concentrations of an N column and a P column of the super junction drift region meet the charge balance condition;
a left base region and a right base region which are formed by further extending and doping are formed above the super junction drift region;
doping the upper part of the base region to form a source region and a channel substrate contact respectively;
a source electrode formed on the upper surface of the source region and the channel substrate contact;
a drain electrode formed on the lower surface of the drain region;
the method is characterized in that:
the substrate and the super-junction drift region are made of element semiconductor materials, a groove is formed between the left base region and the right base region in an etching mode, and the groove penetrates through the super-junction drift region to the drain region along the longitudinal direction; the depth-to-width ratio of the trench is determined according to the length of a super junction drift region of the device, and the length of the super junction drift region is determined according to the requirement of breakdown voltage; sequentially forming a gate insulating layer and a semi-insulating polycrystalline silicon layer doped with oxygen on the side wall of the groove, and connecting the two longitudinal ends of the semi-insulating polycrystalline silicon layer with the two ends of a gate drain of the device; the longitudinal surface of the semi-insulating polycrystalline silicon layer corresponding to the base region is a heavily doped region, and a grid electrode is formed in the heavily doped region;
and filling a High K dielectric layer in the groove with the surface becoming a semi-insulating polycrystalline silicon layer, wherein the longitudinal area of the High K dielectric layer is equivalent to the area of the super-junction drift region, and the semi-insulating polycrystalline silicon layer and the High K dielectric layer jointly form a composite dielectric layer.
2. The vertical super junction double-diffused metal oxide semiconductor field effect transistor with a composite dielectric layer of claim 1, wherein: the High K material has a relative dielectric constant of 100 to 2000.
3. The vertical super junction double-diffused metal oxide semiconductor field effect transistor with a composite dielectric layer of claim 2, wherein: the width of the High K medium in the transverse direction is 0.2-5 mu m.
4. The vertical super junction double-diffused metal oxide semiconductor field effect transistor with a composite dielectric layer of claim 1, wherein: the thickness of the gate insulating layer is set according to the threshold voltage, and is typically 0.02 to 0.1 μm.
5. The vertical super junction double-diffused metal oxide semiconductor field effect transistor with a composite dielectric layer of claim 1, wherein: and when the breakdown voltage requires 600V, epitaxially growing the super junction drift region with the thickness of 25-50 μm on the substrate.
6. The vertical super junction double-diffused metal oxide semiconductor field effect transistor with a composite dielectric layer of claim 1, wherein: typical doping concentrations of substrates of elemental semiconductor material are 1 x 1013cm-3～1×1015cm-3。
7. The vertical super junction double-diffused metal oxide semiconductor field effect transistor with a composite dielectric layer of claim 1, wherein: the width W of a P column in the super junction drift regionPWidth W of column NNThe proportion of (A) is set according to the device characteristics and the process conditions, and the typical value is 1/1-5/1; doping concentration N of N columnDDoping concentration N with P columnAThe proportion range of (A) is set according to the device characteristics and the process conditions, and the typical value is 2/1-10/1.
8. The vertical super junction double-diffused metal oxide semiconductor field effect transistor with a composite dielectric layer of claim 1, wherein: when the breakdown voltage requires 600V, the depth-to-width ratio of the trench is 15: 1-20: 1; when the breakdown voltage requires 200V, the depth-to-width ratio of the trench is 3:1-8: 1.
9. The vertical super junction double-diffused metal oxide semiconductor field effect transistor with a composite dielectric layer of claim 1, wherein: the thickness of the semi-insulating polycrystalline silicon layer is 0.2-1.5 mu m; of semi-insulating polycrystalline silicon layerThe oxygen doping proportion is 15-35%, and the corresponding resistivity is 109～1011Ω·cm。
10. A method for manufacturing the longitudinal super junction double-diffusion metal oxide semiconductor field effect transistor with the composite dielectric layer of claim 1 comprises the following steps:
1) taking a substrate made of an element semiconductor material as a drain region at the same time;
2) forming a super junction drift region on the substrate in an epitaxial manner;
3) forming a base region on the upper part of the drift region by ion implantation or diffusion;
4) etching a groove in the base region to enable the groove to penetrate through the drift region downwards to the drain region;
5) forming a gate insulating layer on the trench sidewall;
6) depositing a semi-insulating polycrystalline silicon layer outside the gate insulating layer;
7) filling a High K material in a region which corresponds to the drift region in the trench in the longitudinal direction;
8) doping on the base region to form a source region and a channel substrate contact;
9) heavily doping the region of the surface of the semi-insulating polycrystalline silicon layer in the groove, which longitudinally corresponds to the base region, and depositing polycrystalline silicon to form a grid electrode;
10) forming a source electrode on the contact surface of the source region and the channel substrate;
11) and forming a drain electrode on the surface of the drain region.
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| CN111244179B (en) * | 2020-01-16 | 2021-02-12 | 电子科技大学 | anti-EMI super-junction VDMOS device |
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| DE102005003127B3 (en) * | 2005-01-21 | 2006-06-14 | Infineon Technologies Ag | Lateral semiconductor component, such as IGBT-transistors and MOSFET and JFET, has drift regions of drift zone extending in lateral direction |
| CN106024858A (en) * | 2016-05-19 | 2016-10-12 | 电子科技大学 | HK SOI LDMOSdevice having three-grating structure |
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| CN102779836B (en) * | 2012-07-13 | 2015-02-11 | 电子科技大学 | Longitudinal power device for low-ratio on-resistance employing groove structure with high dielectric constant |
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| DE102005003127B3 (en) * | 2005-01-21 | 2006-06-14 | Infineon Technologies Ag | Lateral semiconductor component, such as IGBT-transistors and MOSFET and JFET, has drift regions of drift zone extending in lateral direction |
| CN106024858A (en) * | 2016-05-19 | 2016-10-12 | 电子科技大学 | HK SOI LDMOSdevice having three-grating structure |
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