CN105742366B - N-type dynamic threshold transistor, preparation method and the method for improving operating voltage - Google Patents
N-type dynamic threshold transistor, preparation method and the method for improving operating voltage Download PDFInfo
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- CN105742366B CN105742366B CN201610237320.8A CN201610237320A CN105742366B CN 105742366 B CN105742366 B CN 105742366B CN 201610237320 A CN201610237320 A CN 201610237320A CN 105742366 B CN105742366 B CN 105742366B
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
Abstract
The present invention provides a kind of N-type dynamic threshold transistor, preparation method and the method for improving operating voltage, including substrat structure, NMOS device and PN junction device；The area P of PN junction device and the body area of NMOS device connect, and the area N of PN junction device and the grid of NMOS device connect.It carries out source, drain region and body area that N-type heavy doping is respectively formed NMOS device, being formed simultaneously PN junction device in p-type intrinsic region；Side sequentially forms gate oxide, polysilicon layer over the channel region, carries out N-type heavy doping to polysilicon layer and forms grid；The grid of NMOS device are connected with the area N of PN junction device with metal by through-hole.The present invention carrys out lifting body area voltage, reduces threshold voltage, improves driving current, realize the raising of operating voltage, extend N-type dynamic threshold transistor in the application value of low consumption circuit design field by forming a reverse biased pn junction on grid body connecting path.
Description
Technical field
The present invention relates to technical field of semiconductor device, more particularly to a kind of N-type dynamic threshold transistor, preparation method
And the method for improving operating voltage.
Background technique
During development of the entire semicon industry to new generation of semiconductor device, chip manufacturer is faced with severe
Challenge.Concretely, produce high performance chips manufacturer's facing challenges come to speed faster, the lower chip of temperature sets
The demand of meter.Chip manufacturer for mobile application is it is desirable that the smaller semiconductor devices of power consumption.It is chosen to cope with these
War, most of leading device manufacturers all selected the advantage with low-power consumption high speed silicon-on-insulator (SOI,
Silicon On Insulator) technology.
The body area of silicon-on-insulator can be with floating, or draws and be connected on a fixed potential position.When body area voltage increases
When, device threshold voltage reduces, and can effectively increase driving current.SOI dynamic threshold transistor (DTMOS, Dynamic
Threshold Metal Oxide Semiconductor) it is that body area and grid connect, realize the dynamic tune of threshold voltage
It is whole.The type device threshold dynamically changeable, when device is opened, body area voltage is increased, and causes threshold value to reduce, current driving ability
It improves, when device is in an off state, threshold voltage with higher, to reduce leakage current.However body Qu Yuyuan, drain region
The PN junction of formation causes electric current to increase suddenly, causes the increase of power consumption if grid voltage is higher than the PN junction conducting voltage.By
In the presence of the parasitic diode, cause dynamic threshold transistor operating voltage lower, generally in 0.7V hereinafter, therefore cannot be with
Traditional transistor shares supply voltage, also limits the application field of dynamic threshold transistor.
Radio-frequency technique to power consumption and performance rdativery sensitive, although SOI DTMOS transistor can provide lower power consumption and
Higher performance, but its operating voltage is lower, can not directly use when higher for operating voltage.
Therefore, how improving the operating voltage of SOI dynamic threshold transistor, to have become those skilled in the art urgently to be resolved
One of the problem of.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of N-type dynamic threshold transistor,
Preparation method and the method for improving operating voltage, the operating voltage for solving SOI dynamic threshold transistor in the prior art is low,
The problems such as cannot sharing supply voltage with traditional transistor, limit application field.
In order to achieve the above objects and other related objects, the present invention provides a kind of N-type dynamic threshold transistor, the N-type
Dynamic threshold transistor includes at least:
Substrat structure, NMOS device and PN junction device on the substrat structure；
The channel region of the NMOS device is p-type intrinsic region, body area is N-type heavily doped region；The PN junction device is with described
The channel region of NMOS device is as the area P, using the body area of the NMOS device as the area N；The area P of the PN junction device with it is described
The area N of the connection in the body area of NMOS device, the PN junction device is connect with the grid of the NMOS device.
Preferably, the substrat structure includes at least semiconductor base and the oxide layer on the semiconductor base.
Preferably, the NMOS device is n NMOS tube in parallel, and n is the natural number more than or equal to 1.
It is highly preferred that the PN junction device is the n PN junction diode that the NMOS tube in parallel with n connects one to one.
It is highly preferred that the PN junction device is 1 PN junction diode.
Preferably, the NMOS device further includes the gate oxide between the channel region and grid, and is located at ditch
The source region of the two sides Dao Qu and drain region；Wherein, the grid are N-type heavily doped region, and the source region and the drain region are N-type heavy doping
Area.
Preferably, the NMOS device is connected with the PN junction device by through-hole and metal.
In order to achieve the above objects and other related objects, the present invention also provides a kind of preparations of N-type dynamic threshold transistor
The preparation method of method, the N-type dynamic threshold transistor includes at least:
One substrat structure is provided, p-type intrinsic region is prepared on the substrat structure；
N-type heavy doping is carried out in the p-type intrinsic region to be respectively formed the source, drain region and body area of NMOS device, it is described
It is channel region between the source of NMOS device, drain region, the channel region of the NMOS device and body area are formed respectively as the area P and the area N
PN junction device, the area P of the PN junction device and the body Qu Xianglian of the NMOS device；
Gate oxide is formed above the channel region of the NMOS device, forms polysilicon layer on the gate oxide,
N-type heavy doping is carried out to form the grid of the NMOS device to the polysilicon layer；
The grid of the NMOS device are connected with the area N of the PN junction device with metal by through-hole.
In order to achieve the above objects and other related objects, the present invention also provides a kind of raising N-type dynamic threshold transistor works
Make the method for voltage, the method for improving N-type dynamic threshold transistor operating voltage includes at least:
PN junction device is connected between the area Shan Heti of NMOS device, the cathode of the PN junction device connects the NMOS device
The anode of the grid of part, the PN junction device connects the body area of the NMOS device；Wherein, the body area of the NMOS device is N-type
The channel region of heavily doped region, while the area N as the PN junction device, the NMOS device is p-type intrinsic region, while as institute
State the area P of PN junction device；So that the body area voltage of the NMOS device increases, and then reduces threshold voltage, improves driving current,
Realize the raising of operating voltage.
As described above, N-type dynamic threshold transistor of the invention, preparation method and the method for improving operating voltage, have
Below the utility model has the advantages that
N-type dynamic threshold transistor, preparation method and the method for improving operating voltage of the invention passes through in the connection of grid body
A reverse biased pn junction is formed on access, is carried out lifting body area voltage, is reduced threshold voltage, improves driving current, realizes operating voltage
Raising, extend N-type dynamic threshold transistor in the application value of low consumption circuit design field.
Detailed description of the invention
Fig. 1 is shown as the schematic top plan view of N-type dynamic threshold transistor domain of the invention.
Fig. 2 is shown as the AA ' of N-type dynamic threshold transistor domain of the invention to schematic cross-sectional view.
Fig. 3 is shown as more finger-cross structure domains of N-type dynamic threshold transistor of the invention.
Fig. 4 is shown as the schematic illustration of the method for raising N-type dynamic threshold transistor operating voltage of the invention.
Component label instructions
1 N-type dynamic threshold transistor
11 substrat structures
111 semiconductor bases
112 oxide layers
12 NMOS devices
121 channel regions
122 gate oxides
123 grid
124 source regions
125 drain regions
126 body areas
13 PN junction devices
131 areas P
132 areas N
14 through-holes
15 metals
16 shallow trench isolations
S1~S4 step
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to FIG. 1 to FIG. 4.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
As shown in FIG. 1 to FIG. 2, the present invention provides a kind of N-type dynamic threshold transistor 1, the N-type dynamic threshold transistor
1 includes at least:
Substrat structure 11, NMOS device 12 and PN junction device 13 on the substrat structure 11.
As shown in Fig. 2, the substrat structure 11 is located at bottom, as the substrate for preparing semiconductor devices.
Specifically, as shown in Fig. 2, in the present embodiment, the substrat structure 11 includes at least semiconductor base 111 and position
Oxide layer 112 on the semiconductor base 111.The semiconductor base 111 includes but is not limited to the materials such as silicon, silica
Material.The substrat structure 11 can also include the semiconductor layer that other improve device performance, be not limited to this embodiment.
As shown in FIG. 1 to FIG. 2, the NMOS device 12 is located on the substrat structure 11, including channel region 121, grid oxygen
Change floor 122, grid 123, source region 124, drain region 125 and body area 126.
Specifically, as shown in Fig. 2, the channel region 121 is located on the substrat structure 11, the channel region 121 is p-type
Intrinsic region.The gate oxide 122 is located on the channel region 121, and in the present embodiment, the gate oxide 122 is using high
The material of dielectric constant.The grid 123 are located at 122 top of gate oxide, and the grid 123 are the polysilicon of N-type heavy doping,
Wherein right part does not carry out N-type heavy doping to play the role of isolation.As shown in Figure 1, the source region 124 and the drain region
125 are located at the two sides of the channel region 121, are the second N-type heavily doped region.The body area 126 connects with the channel region 121
It connects, the body area 126 is the first N-type heavily doped region.
As shown in FIG. 1 to FIG. 2, the PN junction device 13 is located on the substrat structure 11, including the area P 131 and the area N 132.
Specifically, as shown in Fig. 2, the channel region 121 of the area P 131 and the NMOS device shares, the area N 132 with
The body area 121 of the NMOS device shares, and the area N 132 is connect with the area P 131, forms PN junction.
As shown in FIG. 1 to FIG. 2, the connection in the body area 126 of the area P 131 of the PN junction device 13 and the NMOS device 12,
The area N 132 of the PN junction device 13 is connect with the grid 123 of the NMOS device 12 by through-hole 14 and metal 15.
Embodiment two
As shown in figure 3, in the present embodiment, providing a kind of N-type dynamic threshold transistor of more finger-cross structures, being penetrated to meet
The gain of frequency transistor and power requirement.
Specifically, the N-type dynamic threshold transistor of more finger-cross structures includes the NMOS that n NMOS tube in parallel is formed
Device and PN junction device, n are the natural number more than or equal to 1.In the present embodiment, n value is 4, in actual design, with
Gain and the requirement of power determine the occurrence of n, are not limited to this embodiment.The PN junction device can be 1 and n
The PN junction diode that the area Shan Heti of NMOS is separately connected is also possible to n that the NMOS tube in parallel with n connects one to one
PN junction diode.The structure and connection relationship and embodiment one of the NMOS device and the PN junction diode are consistent, herein not
It repeats one by one.
As shown in Fig. 2, the present invention also provides a kind of preparation method of N-type dynamic threshold transistor, the N-type dynamic threshold
The preparation method of transistor includes at least:
Step S1: providing a substrat structure 11, and p-type intrinsic region is prepared on the substrat structure 11.
Specifically, as shown in Fig. 2, in the present embodiment, the substrat structure 11 is including semiconductor base 111 and is located at institute
State the oxide layer 112 on semiconductor base 111.The substrat structure 11 can also include the semiconductor that other improve device performance
Layer, is not limited to this embodiment.
Step S2: N-type heavy doping is carried out in the p-type intrinsic region to be respectively formed source region 124, the leakage of NMOS device 12
Area 125 and body area 126 are channel region 121 between the source region 124 of the NMOS device, drain region 125, the NMOS device 12
Channel region 121 and body area 126 are respectively as the area P 131 and the formation of the area N 132 PN junction device 13, the area P 131 of the PN junction device 13
It is connected with the body area 126 of the NMOS device 12.
Specifically, as shown in Fig. 2, in the present embodiment, first time N-type heavy doping shape is carried out in the p-type intrinsic region
PN junction device 13 is formed at the body area 126 of the NMOS device 12, while as the area N 132 and p-type intrinsic region, wherein p-type is intrinsic
P area 131 of the area as PN junction device 13.Second of N-type heavy doping is carried out in the p-type intrinsic region forms NMOS device 12
Source region 124 and drain region 125 (not shown in Fig. 2).
Step S3: gate oxide 122 is formed above the channel region 121 of the NMOS device 12, in the gate oxide
Polysilicon layer is formed on 122, and N-type heavy doping is carried out to form the grid 123 of the NMOS device 12 to the polysilicon layer.
Specifically, in the 121 disposed thereon high dielectric constant material of channel region of the NMOS device 12 to form gate oxidation
Layer 122.It is described to be formed to carry out N-type heavy doping to the polysilicon layer for the deposit polycrystalline silicon layer on the gate oxide 122
The grid 123 of NMOS device 12, wherein the polysilicon layer for closing on part with the body area 126 does not carry out N-type heavy doping, by
One time n-type doping is isolated with second of n-type doping.
Step S4: by through-hole 14 and metal 15 by the area N of the grid 123 of the NMOS device 12 and the PN junction device 13
132 are connected.
The body area 126 of the NMOS device 12 by STI (Shallow Trench Isolation, shallow trench isolation) with
Other device isolations.
As shown in figure 4, the present invention also provides a kind of method for improving N-type dynamic threshold transistor operating voltage, it is described to mention
The method of high N-type dynamic threshold transistor operating voltage includes at least:
Between the area Shan Heti of NMOS device 12 connect PN junction device 13, the PN junction device 13 cathode connection described in
The grid of NMOS device 12, the anode of the PN junction device 13 connect the body area of the NMOS device 12；Wherein, the NMOS device
12 body area is N-type heavily doped region, while the area N as the PN junction device 13, the channel region of the NMOS device 12 are p-type
Intrinsic region, while the area P as the PN junction device 13；So that the body area voltage of the NMOS device 12 increases, and then reduce
Threshold voltage improves driving current, realizes the raising of operating voltage.
Specifically, as shown in figure 4, the PN junction device 13 is reverse-biased on the grid, body connecting path of the NMOS device 12,
When grid voltage is positive voltage, and reaches the threshold voltage of the NMOS device 12, NMOS device 12 opens grid voltage
Variation will affect the voltage of channel region；Since PN junction can bear larger voltage, the electric current very little of the PN junction device 13, PN are flowed through
Junction device 13 is not turned on, and is equivalent to one capacitor element of access between the grid, body of NMOS device 12, when grid voltage increases
When, channel region voltage also increases with it, and body area is connected with channel region, therefore body area voltage can be promoted centainly；Meanwhile
When increasing due to grid voltage and body area voltage, the threshold voltage of NMOS device is reduced, and driving current is also improved,
To make N-type dynamic threshold transistor operating voltage of the invention improve, reach 0.7V or so, it can be total with traditional transistor
With supply voltage, the application field of N-type dynamic threshold transistor is extended.It is wanted to meet gain and the power of RF transistors
It asks, the NMOS device 12 may include n NMOS tube in parallel, and n is the natural number more than or equal to 1, in actual design, with
Gain and the requirement of power determine the occurrence of n.
As described above, N-type dynamic threshold transistor of the invention, preparation method and the method for improving operating voltage, have
Below the utility model has the advantages that
N-type dynamic threshold transistor, preparation method and the method for improving operating voltage of the invention passes through in the connection of grid body
A reverse biased pn junction is formed on access, is carried out lifting body area voltage, is reduced threshold voltage, improves driving current, realizes operating voltage
Raising, extend N-type dynamic threshold transistor in the application value of low consumption circuit design field.
In conclusion the present invention provides a kind of N-type dynamic threshold transistor, preparation method and the side for improving operating voltage
Method, including substrat structure, NMOS device and PN junction device on the substrat structure；The channel region of the NMOS device is
P-type intrinsic region, body area are N-type heavily doped region；The PN junction device is using the channel region of the NMOS device as the area P, with described
The body area of NMOS device is as the area N；The connection in the body area in the area the P and NMOS device of the PN junction device, the PN junction device
The area N of part is connect with the grid of the NMOS device.Preparation method includes providing a substrat structure, is made on the substrat structure
Standby p-type intrinsic region；N-type heavy doping is carried out in the p-type intrinsic region to be respectively formed the source, drain region and body area of NMOS device,
It is channel region between the source of the NMOS device, drain region, the channel region of the NMOS device and body area are respectively as the area P and the area N
Form PN junction device, the area P of the PN junction device and the body Qu Xianglian of the NMOS device；In the channel region of the NMOS device
Top forms gate oxide, forms polysilicon layer on the gate oxide, carries out N-type heavy doping to the polysilicon layer with shape
At the grid of the NMOS device；The grid of the NMOS device are connected with the area N of the PN junction device with metal by through-hole.It mentions
The method of high N-type dynamic threshold transistor operating voltage includes that PN junction device, institute are connected between the area Shan Heti of NMOS device
The cathode for stating PN junction device connects the grid of the NMOS device, and the anode of the PN junction device connects the body of the NMOS device
Area；Wherein, the body area of the NMOS device is N-type heavily doped region, while the area N as the PN junction device, the NMOS device
The channel region of part is p-type intrinsic region, while the area P as the PN junction device；So that the body area voltage liter of the NMOS device
Height, and then reduce threshold voltage, improve driving current, realize the raising of operating voltage.N-type dynamic threshold crystal of the invention
Pipe, preparation method and the method for improving operating voltage carry out lifting body by forming a reverse biased pn junction on grid body connecting path
Area's voltage reduces threshold voltage, improves driving current, realizes the raising of operating voltage, extends N-type dynamic threshold transistor and exist
The application value of low consumption circuit design field.So the present invention effectively overcomes various shortcoming in the prior art and has height
Spend value of industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (8)
1. a kind of N-type dynamic threshold transistor, which is characterized in that the N-type dynamic threshold transistor includes at least:
Substrat structure, NMOS device and PN junction device on the substrat structure；
The channel region of the NMOS device is p-type lightly doped district, body area is N-type heavily doped region；The PN junction device is with described
The channel region of NMOS device is as the area P, using the body area of the NMOS device as the area N；The area P of the PN junction device with it is described
The body area of NMOS device connects, and the area N of the PN junction device is connect with the grid of the NMOS device, and the PN junction device is for mentioning
The operating voltage of the high NMOS device；
The grid include N-type heavily doped region and isolated area, and for the isolated area close to the body area, the isolated area is undoped
Polysilicon layer.
2. N-type dynamic threshold transistor according to claim 1, it is characterised in that: the substrat structure includes at least half
Conductor substrate and the oxide layer on the semiconductor base.
3. N-type dynamic threshold transistor according to claim 1, it is characterised in that: the NMOS device is n in parallel
NMOS tube, n are the natural number more than or equal to 1.
4. N-type dynamic threshold transistor according to claim 3, it is characterised in that: the PN junction device is in parallel with n
N PN junction diode connecting one to one of NMOS tube.
5. N-type dynamic threshold transistor according to claim 1 or 3, it is characterised in that: the PN junction device is 1 PN
Junction diode.
6. N-type dynamic threshold transistor according to claim 1, it is characterised in that: the NMOS device further includes being located at
Gate oxide between the channel region and grid, and source region and drain region positioned at channel region two sides；Wherein, the grid are N-type
Heavily doped region, the source region and the drain region are N-type heavily doped region.
7. N-type dynamic threshold transistor according to claim 1, it is characterised in that: the NMOS device and the PN junction
Device is connected by through-hole and metal.
8. a kind of preparation method of N-type dynamic threshold transistor, it is characterised in that: the preparation of the N-type dynamic threshold transistor
Method includes at least:
One substrat structure is provided, p-type lightly doped district is prepared on the substrat structure；
N-type heavy doping is carried out in the p-type lightly doped district to be respectively formed the source, drain region and body area of NMOS device, it is described
It is channel region between the source of NMOS device, drain region, the channel region of the NMOS device and body area are formed respectively as the area P and the area N
PN junction device, the area P of the PN junction device and the body Qu Xianglian of the NMOS device；
Gate oxide is formed above the channel region of the NMOS device, forms polysilicon layer on the gate oxide, to institute
State polysilicon layer and carry out N-type heavy doping to form the grid of the NMOS device, wherein the grid include N-type heavily doped region and every
From area, for the isolated area close to the body area, the isolated area is undoped polysilicon layer；
The grid of the NMOS device are connected with the area N of the PN junction device with metal by through-hole；
The PN junction device is used to improve the operating voltage of the NMOS device.
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| CN108198854A (en) * | 2018-01-12 | 2018-06-22 | 上海华虹宏力半导体制造有限公司 | Improve the field-effect transistor structure of RF switch characteristic |
| CN108417590B (en) * | 2018-02-02 | 2020-11-27 | 天津大学 | NMOS (N-channel metal oxide semiconductor) type grid body interconnection photoelectric detector and preparation method thereof |
| CN117176098A (en) * | 2023-11-01 | 2023-12-05 | 上海安其威微电子科技有限公司 | Amplitude limiting circuit and wireless transceiver |
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| CN104362174A (en) * | 2014-11-21 | 2015-02-18 | 中国科学院上海微系统与信息技术研究所 | SOI dynamic threshold transistor |
| CN104810406A (en) * | 2015-04-17 | 2015-07-29 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switching device structure |
| CN105161500A (en) * | 2015-08-11 | 2015-12-16 | 上海华虹宏力半导体制造有限公司 | Insulator-on-silicon (SOI) radio-frequency device structure |
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| CN101090122A (en) * | 2006-06-16 | 2007-12-19 | 中国科学院微电子研究所 | Method for grid connecting with SOI dynamic threshold transistor through anti-off schottky |
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| CN104362174A (en) * | 2014-11-21 | 2015-02-18 | 中国科学院上海微系统与信息技术研究所 | SOI dynamic threshold transistor |
| CN104810406A (en) * | 2015-04-17 | 2015-07-29 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switching device structure |
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