CN113270480A - Gallium nitride power device and preparation method thereof - Google Patents

Gallium nitride power device and preparation method thereof Download PDF

Info

Publication number
CN113270480A
CN113270480A CN202110545627.5A CN202110545627A CN113270480A CN 113270480 A CN113270480 A CN 113270480A CN 202110545627 A CN202110545627 A CN 202110545627A CN 113270480 A CN113270480 A CN 113270480A
Authority
CN
China
Prior art keywords
gallium nitride
drift region
arc
nitride layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110545627.5A
Other languages
Chinese (zh)
Other versions
CN113270480B (en
Inventor
张春伟
姚钟博
向振宇
郭海君
李阳
岳文静
高嵩
阚皞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Jinan
Original Assignee
University of Jinan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Jinan filed Critical University of Jinan
Priority to CN202110545627.5A priority Critical patent/CN113270480B/en
Publication of CN113270480A publication Critical patent/CN113270480A/en
Application granted granted Critical
Publication of CN113270480B publication Critical patent/CN113270480B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204Diodes
    • H01L29/66212Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a gallium nitride power device and a preparation method thereof, wherein the preparation method comprises the following steps: the semiconductor substrate is provided with a buffer medium layer above the semiconductor substrate, and a drift region gallium nitride layer is arranged above the buffer medium layer; the thickness of the whole area of the drift region gallium nitride layer or the set area is gradually increased along the direction from the low potential electrode to the high potential electrode under the voltage-resistant state of the device, so that the field plate effect generated by the substrate meets the requirement of electric field optimization. In the structure, the thickness of the drift region gallium nitride layer is continuously increased along the potential rising direction in the horizontal direction, so that the field plate action at a low potential position is increased, the field plate action at a high potential position is reduced, a device obtains a better electric field modulation effect, and the voltage resistance of the device is improved.

Description

Gallium nitride power device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a gallium nitride power device and a preparation method thereof.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
Gallium nitride as a third-generation semiconductor material has the characteristics of wide forbidden band width, high critical electric field, high electron mobility and the like, has unique advantages in the preparation of high-voltage power semiconductor devices, and is widely concerned and researched. However, the P-type gallium nitride is difficult to prepare, and the doping concentration is difficult to control accurately, so that the conventional device structure with the P-type body region cannot be prepared by adopting a gallium nitride material, which limits the application of the gallium nitride material. At present, gallium nitride materials are mostly used for preparing high electron mobility transistors, meanwhile, in order to increase the heat dissipation characteristic of a power device, a silicon substrate is needed for epitaxial growth of the gallium nitride high electron mobility transistors, and in order to ensure the voltage withstanding characteristic between the substrate and a drain electrode of the device, a gallium nitride buffer layer between two-dimensional electron gas of the device and the substrate needs to be kept in a high resistance state, so that the gallium nitride buffer layer is limited to be used for conducting, and the preparation difficulty of the gallium nitride buffer layer is increased.
In addition, referring to fig. 1, the high-resistance gan buffer layer of the conventional gan high-electron-mobility transistor has the same thickness under the channel region and the drain electrode of the device, and under the condition of withstand voltage, the high-resistance gan buffer layer with a larger thickness under the channel region of the device may generate leakage current under the action of a strong electric field, which may cause premature breakdown of the device.
Disclosure of Invention
In order to solve the problems, the invention provides a gallium nitride power device and a preparation method thereof, and the gallium nitride power device not only can realize higher voltage endurance and current capability, but also can reduce the electric field intensity at the edge of a grid electrode and has higher grid electrode reliability.
In some embodiments, the following technical scheme is adopted:
a gallium nitride power device, comprising: the semiconductor substrate is provided with a buffer medium layer above the semiconductor substrate, and a drift region gallium nitride layer is arranged above the buffer medium layer; the thickness of the whole area of the drift region gallium nitride layer or the set area is gradually increased along the direction from the low potential electrode to the high potential electrode under the voltage-resistant state of the device, so that the field plate effect generated by the substrate meets the requirement of electric field optimization.
Furthermore, a channel region gallium nitride layer is further arranged on the buffer medium layer, and the thickness of the whole region or the set region of the channel region gallium nitride layer is smaller than the average thickness of the drift region gallium nitride layer.
Furthermore, the boundary between the drift region gallium nitride layer and the buffer medium layer is in a circular arc shape;
alternatively, the first and second electrodes may be,
the boundary between the drift region gallium nitride layer and the buffer medium layer is an elliptic arc shape or a multi-section arc shape formed by connecting two or more than two sections of arcs.
Further, the doping concentration of the whole region or the set partial region in the drift region is related to the distance R from the corresponding position to the center of the arc or the center of the equivalent arc, specifically to
Figure BDA0003073403210000021
To
Figure BDA0003073403210000022
Wherein E iscIs the critical breakdown electric field intensity of the material of the drift region0Is a vacuum dielectric constant of ∈rTo floatAnd the relative dielectric constant of the moving area material, q is the unit charge quantity, and R is the distance from the corresponding position to the center of the circle where the circular arc is located or the distance from the corresponding position to the center of the circle where the equivalent circular arc is located.
Further, the doping concentration of the whole region or the set partial region in the drift region is related to the distance R from the corresponding position to the center of the arc or the center of the equivalent arc, specifically to
Figure BDA0003073403210000023
To
Figure BDA0003073403210000024
Wherein E iscIs the critical breakdown electric field intensity of the material of the drift region0Is a vacuum dielectric constant of ∈rAnd the relative dielectric constant of the material of the drift region, q is the unit charge quantity, and R is the distance from the corresponding position to the center of the circle where the circular arc is located or the corresponding position to the center of the circle where the equivalent circular arc is located.
Further, the radian of the circular arc is between 1/3 pi and 2/3 pi;
alternatively, the first and second electrodes may be,
the equivalent arc has a radian ranging from 1/3 pi to 2/3 pi.
Furthermore, an included angle between a connecting line formed by an end point of the arc far away from the upper surface of the gallium nitride layer in the drift region and the center of the arc and the vertical direction is more than or equal to 0 degree and less than or equal to 30 degrees;
or an included angle between a connecting line formed by an end point of the equivalent arc far away from the upper surface of the drift region gallium nitride layer and the center of the equivalent arc and the vertical direction is more than or equal to 0 degree and less than or equal to 30 degrees.
Further, the surface or the side surface of the drift region gallium nitride layer is connected with the strip-shaped drift region;
or, a surface doping layer exists on the upper surface of the drift region gallium oxide layer, and the doping concentration of the surface doping layer is determined according to the requirement.
In other embodiments, the following technical solutions are adopted:
a power management chip adopts the gallium nitride power device.
In other embodiments, the following technical solutions are adopted:
a preparation method of a gallium nitride power device comprises the following steps:
forming an etching window on the surface of the substrate by using photoresist;
etching the substrate in the etching window by using an etching technology to ensure that the etching depth of the substrate right below the center of the etching window reaches the set requirement;
continuously etching the substrate by utilizing an isotropic etching technology to etch a concave region on the substrate and remove the photoresist; the isotropic etching technology enables the boundary of the sunken area to present an arc or an elliptic arc, or a multi-section arc formed by connecting two or more than two arcs, or a circular or approximately circular shape formed by connecting a straight line section with the arc or the elliptic arc or the multi-section arc;
depositing a buffer medium layer;
depositing a gallium nitride material with a set doping concentration, wherein the doping concentrations of the materials at different deposition thicknesses are gradually changed according to design requirements, so that a drift region gallium nitride layer with gradually changed doping concentrations is formed, and the total thickness of deposition is adjusted according to the design requirements;
and removing all materials above the set plane by using a chemical mechanical polishing process, and forming a drift region gallium nitride layer with a boundary shape of circular arc or approximate circular arc by the gallium nitride material left in the original sunken region.
Compared with the prior art, the invention has the beneficial effects that:
(1) the substrate of the gallium nitride power device is connected with a fixed potential to realize the effect of a field plate and modulate the electric field distribution of the device, however, the thickness of a gallium nitride layer in a drift region of the traditional device structure is fixed, the potential in the drift region of the device is continuously changed along the horizontal direction, so that the potential difference between a low potential position and the substrate is small, the effect of the field plate is too small, the potential difference between a high potential position and the substrate is too large, and the effect of the field plate is too strong, so that the electric field modulation effect is poor; in the structure, the thickness of the drift region gallium nitride layer is continuously increased along the potential rising direction in the horizontal direction, so that the field plate action at a low potential position is increased, the field plate action at a high potential position is reduced, a device obtains a better electric field modulation effect, and the voltage resistance of the device is improved.
(2) The thickness of the gallium nitride layer in the channel region in the structure is smaller than the average thickness of the gallium nitride layer in the drift region, so that the gallium nitride layer in the channel region below the grid of the device can be prevented from penetrating through to reduce the pressure resistance of the device;
(3) when the boundary of the gallium nitride layer of the drift region in the structure is in the shape of an arc, an electric field concentration effect can be introduced into the drift region of the device, the electric field change of the drift region caused by a space electric field of the drift region can be effectively neutralized, the electric field distribution of the drift region of the device is optimized, and the voltage resistance of the device is improved;
(4) when the gallium nitride layer of the drift region in the structure is doped according to a specific doping range or a specific change rule, the electric field concentration effect introduced by the circular drift region can just neutralize the space charge of the drift region, so that the effect of uniform distribution of the electric field of the drift region is achieved, and the device has excellent pressure resistance;
(5) the channel region gallium nitride layer and the drift region gallium nitride layer of the traditional high electron mobility transistor are required to be non-conductive high-resistance regions, so that the device can obtain the capability of being turned off and withstand voltage;
(6) the structure of the invention can not contain a barrier layer, thereby reducing the preparation difficulty of the device and reducing the current collapse effect of the device;
(7) the preparation method of the gallium nitride power device can form the gallium nitride layer of the drift region with the boundary very close to the circular arc, can effectively control the doping concentration change of the drift region of the device, and has the advantages of few process steps and low cost.
Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a diagram of a conventional GaN HEMT structure;
fig. 2 is a schematic diagram of a gan hemt structure according to the present invention, wherein the thickness of the gan layer in the drift region gradually increases from the source to the drain;
fig. 3 is a schematic structural diagram of a gan transistor provided in the present invention, wherein the boundary of the gan layer in the drift region is arc-shaped;
fig. 4 is a schematic structural diagram of a gan transistor provided in the present invention, wherein barrier layers are disposed on the surfaces of the channel region gan layer and part of the drift region gan layer;
fig. 5 is a schematic structural diagram of a gan transistor according to the present invention, wherein a schottky contact is formed between the gate and the gan layer in the channel region;
fig. 6 is a schematic structural diagram of a gan transistor provided in the present invention, wherein a side surface of a gan layer of a drift region is provided with a side stripe-shaped drift region;
fig. 7 is a schematic structural diagram of a gan transistor provided in the present invention, wherein a surface doped layer is disposed on a surface of a gan layer in a drift region;
fig. 8 is a schematic structural diagram of a gan transistor provided in the present invention, wherein a contact surface between the gan layer in the drift region and the drain is in a circular arc shape;
fig. 9(a) and (b) are schematic structural diagrams of a gan transistor provided in the present invention, respectively, wherein the boundary of the gan layer in the drift region is an approximate arc formed by an elliptical arc or two elliptical arcs;
fig. 10 is a schematic structural view of a gan diode according to the present invention, wherein a schottky contact is formed between an anode and a barrier layer, and an ohmic contact is formed between a cathode and the barrier layer;
fig. 11 is a schematic structural diagram of a gan diode according to the present invention, in which a schottky contact is formed between an anode and a drift region gan layer, and an ohmic contact is formed between a cathode and the drift region gan layer;
fig. 12(a) - (e3) are schematic diagrams of a method and a process for manufacturing a gan power device according to the present invention;
the structure comprises a substrate 1, a buffer dielectric layer 2, a drift region gallium nitride layer 3, a channel region gallium nitride layer 4, a barrier layer 5, a source electrode 6, a drain electrode 7, a grid electrode 8, a lateral side strip-shaped drift region 9, a surface doped region 10, an anode 11 and a cathode 12.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Example one
According to an embodiment of the present invention, there is disclosed a gallium nitride high electron mobility transistor comprising; the transistor comprises a substrate 1, a buffer dielectric layer 2 positioned on the substrate 1, a channel region gallium nitride layer 4 and a drift region gallium nitride layer 3 positioned on the buffer dielectric layer 2, a barrier layer 5 arranged above the channel region gallium nitride layer 4 and the drift region gallium nitride layer 3, and a source electrode 6, a drain electrode 7 and a grid electrode 8 positioned between the source electrode 6 and the drain electrode 7 arranged above the barrier layer 5;
the thickness of the whole or set region of the drift region gallium nitride layer 3 is gradually increased along the direction from the source electrode 6 to the drain electrode 7, so as to optimize the optimization effect of the substrate 1 on the electric field distribution of the drift region;
it should be noted that the rate of increase of the thickness of the drift region gallium nitride layer 3 along the direction from the source 6 to the drain 7 may be set according to design requirements or process preparation requirements, and the thickness of a part of the drift region gallium nitride layer 3 in this embodiment linearly increases along the direction from the source 6 to the drain 7, as shown in fig. 2;
in this embodiment, the thickness of the channel region gallium nitride layer 4 is smaller than the average thickness of the drift region gallium nitride layer 3, so as to prevent the channel region gallium nitride layer 4 from penetrating through under the voltage-resistant state of the device and reducing the voltage-resistant capability of the device.
Example two
According to an embodiment of the present invention, there is disclosed a gallium nitride transistor, including; the transistor comprises a substrate 1, a buffer dielectric layer 2 located above the substrate 1, a drift region gallium nitride layer 3 and a channel region gallium nitride layer 4 located above the buffer dielectric layer 2, wherein a barrier layer 5 is arranged above the channel region gallium nitride layer 4 and the drift region gallium nitride layer 3, and a source electrode 6, a drain electrode 7 and a grid electrode 8 located between the source electrode 6 and the drain electrode 7 are arranged above the barrier layer 5, as shown in fig. 3.
As an alternative embodiment, the barrier layer 5 may only cover a part of the drift region gallium nitride layer 3, and the drain electrode 7 is disposed above the drift region gallium nitride layer 3, as shown in fig. 4;
as another alternative, the device may not include the barrier layer 5, and the source electrode 6 and the gate electrode 8 may be disposed above the channel region gallium nitride layer, and the drain electrode 7 may be disposed above the drift region gallium nitride layer 3, as shown in fig. 5.
In the above embodiment, all or a set part of the boundary between the drift region gallium nitride layer and the buffer dielectric layer is arc-shaped; the arc of the arc is between 1/3 pi and 2/3 pi.
As an optional implementation manner, an included angle between a connecting line of an end point of the arc far away from the upper surface of the gallium nitride layer 3 in the drift region and the center of the circle where the arc is located and the vertical direction is more than or equal to 0 degree and less than or equal to 30 degrees; preferably, the included angle is 0 °, that is, a line connecting an end point of the arc far from the upper surface of the drift region gallium nitride layer 3 and a center of the arc is a straight line in the vertical direction, when the included angle is 0 °, the drift region gallium nitride layer 3 is in a fan shape, the electric field distribution of the drift region gallium nitride layer is the same as that of the drift region in a standard circle shape, at this time, the electric field distribution is optimal, when the included angle is increased, the drift region gallium nitride layer 3 can be regarded as a part of increase/decrease on the basis of the fan shape, and the increased/decreased part can change the electric field distribution, so that the electric field distribution deviates from the optimal state, thereby reducing the voltage resistance of the device.
It should be noted that, due to the process manufacturing deviation, the boundary between the actually manufactured drift region gallium nitride layer 3 and the buffer dielectric layer 2 may slightly deviate from the standard circular arc, but the effect and the technical scheme of the implementation are the same as those of the present patent and are within the protection scope of the present patent.
Because the drift region gallium nitride layer is circular or approximately circular, an electric field concentration effect can be introduced into the device, in the embodiment, the doping concentration of the device is formed into the drift region gallium nitride layer with the concentration gradually changed according to a specific rule, so that the influence of the electric field concentration effect of the device on the electric field and the influence of the space charge region of the drift region gallium nitride layer on the electric field can be mutually offset, the electric field of the drift region gallium nitride layer of the device is uniformly distributed, and the device can obtain excellent voltage resistance.
Specifically, in the whole region or a set partial region of the drift region gallium nitride layer 3 of the present embodiment, the doping concentration at each position is set to be within
Figure BDA0003073403210000091
To
Figure BDA0003073403210000092
Wherein E iscIs the critical breakdown electric field intensity of the material of the drift region0Is a vacuum dielectric constant of ∈rQ is the unit charge quantity, and R is the distance from the corresponding position to the center of the circular arc.
As a further proposal, the doping concentration of each position in the whole area or the set partial area of the drift region gallium nitride layer 3 is
Figure BDA0003073403210000093
To
Figure BDA0003073403210000094
In the meantime.
In a further embodiment, the doping concentration at each position in the whole region or a set partial region of the drift region gallium nitride layer 3 is
Figure BDA0003073403210000095
At this time, the doping concentration of each position is in inverse proportion to the distance from the position to the center of the circle where the circular arc is located. At this time, under the condition of reverse voltage resistance of the device, the influence of space charge caused by doping impurities in the drift region of the device on the electric field can be exactly offset with the electric field concentration effect caused by the shape of the gallium nitride layer in the drift region, so that the electric field in the gallium nitride layer in the drift region can be uniformly distributed, and the device can obtain excellent voltage resistance.
Of course, under the influence of process conditions or other factors, the doping concentration of each position in the whole region or the set partial region of the drift region gallium nitride layer deviates
Figure BDA0003073403210000096
When, for example: the doping concentration of each position is
Figure BDA0003073403210000097
To
Figure BDA0003073403210000098
Or in between
Figure BDA0003073403210000099
To
Figure BDA00030734032100000910
To (c) to (d); the effect of space charge and the effect of electric field concentration can still be partially offset, so that the electric field distribution in the drift region gallium nitride layer 3 is more uniform, and the device can obtain better withstand voltageForce, doping concentration deviation
Figure BDA00030734032100000911
The more the withstand voltage is reduced.
It should be noted that the critical breakdown electric field strength Ec of the semiconductor material is influenced by the growth quality of the material and the doping of the material, and deviates from the theoretical value of the material.
For reference, this example calculates that a typical value of the critical breakdown field strength is 4.0 × 106V/cm, and a relative dielectric constant of 9, the doping concentration in the GaN layer 3 in the drift region should be
Figure DEST_PATH_IMAGE001
For example, when R is 5 μm, the doping concentration should be 3.98 × 1016cm-3
Of course, the above calculations are merely exemplary and are not intended as a limitation on the present patent protection scheme.
As an alternative embodiment, the side face of the drift region gallium nitride layer 3 is further provided with a side face strip-shaped drift region 9, as shown in fig. 6;
as an optional implementation manner, the surface of the drift region gallium nitride layer 3 is further provided with a surface strip-shaped drift region;
as an optional implementation manner, the surface of the drift region gallium nitride layer 3 is provided with a surface doped region 10, and the doping concentration of the surface doped region can be set as required, so as to reduce the on-resistance of the device surface region and increase the current capability of the device, as shown in fig. 7;
as an alternative embodiment, the contact surface between the drift region gallium nitride layer 3 and the drain electrode 7 is an inward concave arc shape to increase the contact area of the drain electrode, reduce the contact resistance, and make the electric field distribution on the entire contact surface between the drain electrode 7 and the drift region gallium nitride layer 3 more uniform, as shown in fig. 8.
EXAMPLE III
According to an embodiment of the present invention, there is disclosed a gallium nitride transistor, including; the structure comprises a substrate 1, a buffer dielectric layer 2 positioned above the substrate 1, a drift region gallium nitride layer 3 and a channel region gallium nitride layer 4 positioned above the buffer dielectric layer 2, wherein a barrier layer 5 is arranged above the channel region gallium nitride layer 4 and the drift region gallium nitride layer 3, and a source electrode 6, a drain electrode 7 and a grid electrode 8 positioned between the source electrode 6 and the drain electrode 7 are arranged above the barrier layer 5.
The difference between the structure of the gan transistor in this embodiment and that in the second embodiment is: the boundary between the drift region gallium nitride layer 3 and the buffer medium layer 2 is an elliptic arc shape, or a multi-section arc shape formed by connecting two or more than two sections of arcs.
In this embodiment, an equivalent arc is determined based on the elliptical arc or the multi-segment arc; the method for determining the equivalent circular arc can select the following three modes:
selecting an arc with the smallest area enclosed by the boundary of the drift region gallium nitride layer 3 from all arcs intersected with the boundary of the drift region gallium nitride layer 3 as an equivalent arc, as shown in fig. 9 (a);
arc with different curvature radiuses is made by taking two end points of the boundary between the drift region gallium nitride layer 3 and the buffer medium layer 2 as end points, and the arc with the smallest area enclosed by the boundary of the drift region gallium nitride layer 3 is selected as an equivalent arc;
thirdly, placing the center of a circle at the farthest point of the lower surface of the drain electrode 7 from the source electrode 6, making circles with different radiuses, cutting off the parts of the circles, which are positioned in the three areas of the substrate 1, the buffer dielectric layer 2 and the drift region gallium nitride layer 3, to form a plurality of circular arcs, and after the boundary between the drift region gallium nitride layer 3 and the buffer dielectric layer 2 is connected end to end with the plurality of circular arcs, the corresponding circular arc with the smallest enclosed area is an equivalent circular arc, as shown in fig. 9 (b).
Of course, those skilled in the art may select other ways to determine the equivalent circular arc according to actual needs, and the embodiment is not limited.
After the equivalent circular arc is determined, the doping concentration of each position in the whole region or the set partial region of the drift region gallium nitride layer 3 is the same as that in the second embodiment, except that in the determination formula of the doping concentration, R is the distance from the corresponding position to the center of the circle where the equivalent circular arc is located;
other technical solutions of this embodiment are the same as those of the second embodiment, and are not described herein again.
Example four
According to an embodiment of the present invention, there is disclosed a gallium nitride diode, including; the drift region gallium nitride based on the epitaxial growth substrate comprises a substrate 1, a buffer dielectric layer 2 located above the substrate 1, and a drift region gallium nitride layer 3 located above the buffer dielectric layer 2, wherein a barrier layer 5 is arranged above the drift region gallium nitride layer 3, and an anode 11 and a cathode 12 are arranged above the barrier layer 5, as shown in fig. 10;
as an alternative embodiment, the barrier layer 5 may only cover a part of the drift region gallium nitride layer 3, and the drain electrode 7 is disposed above the drift region gallium nitride layer 3;
as another alternative, the device may also not contain the barrier layer 5, and the source electrode 6 and the drain electrode 7 are disposed above the drift region gallium nitride layer 3, as shown in fig. 11.
In the above embodiment, all or a set part of the boundary between the drift region gallium nitride layer and the buffer dielectric layer is arc-shaped; the arc of the arc is between 1/3 pi and 2/3 pi.
As an optional implementation manner, an included angle between a connecting line of an end point of the arc far away from the upper surface of the gallium nitride layer 3 in the drift region and the center of the circle where the arc is located and the vertical direction is more than or equal to 0 degree and less than or equal to 30 degrees; preferably, the included angle is 0 °, that is, a line connecting an end point of the arc far from the upper surface of the drift region gallium nitride layer 3 and a center of the arc is a straight line in the vertical direction, when the included angle is 0 °, the drift region gallium nitride layer 3 is in a fan shape, the electric field distribution of the drift region gallium nitride layer is the same as that of the drift region in a standard circle shape, at this time, the electric field distribution is optimal, when the included angle is increased, the drift region gallium nitride layer 3 can be regarded as a part of increase/decrease on the basis of the fan shape, and the increased/decreased part can change the electric field distribution, so that the electric field distribution deviates from the optimal state, thereby reducing the voltage resistance of the device.
It should be noted that, due to the process manufacturing deviation, the boundary between the actually manufactured drift region gallium nitride layer 3 and the buffer dielectric layer 2 may slightly deviate from the standard circular arc, but the effect and the technical scheme of the implementation are the same as those of the present patent and are within the protection scope of the present patent.
Because the drift region gallium nitride layer is circular or approximately circular, an electric field concentration effect can be introduced into the device, in the embodiment, the doping concentration of the device is formed into the drift region gallium nitride layer with the concentration gradually changed according to a specific rule, so that the influence of the electric field concentration effect of the device on the electric field and the influence of the space charge region of the drift region gallium nitride layer on the electric field can be mutually offset, the electric field of the drift region gallium nitride layer of the device is uniformly distributed, and the device can obtain excellent voltage resistance.
Specifically, in the whole region or a set partial region of the drift region gallium nitride layer 3 of the present embodiment, the doping concentration at each position is set to be within
Figure BDA0003073403210000131
To
Figure BDA0003073403210000132
Wherein E iscIs the critical breakdown electric field intensity of the material of the drift region0Is a vacuum dielectric constant of ∈rQ is the unit charge quantity, and R is the distance from the corresponding position to the center of the circular arc.
As a further proposal, the doping concentration of each position in the whole area or the set partial area of the drift region gallium nitride layer 3 is
Figure BDA0003073403210000133
To
Figure BDA0003073403210000134
In the meantime.
In a further embodiment, the doping concentration at each position in the whole region or a set partial region of the drift region gallium nitride layer 3 is
Figure BDA0003073403210000135
At this time, the doping at each siteThe impurity concentration is in inverse proportion to the distance from the position to the circle center of the circular arc. At this time, under the condition of reverse voltage resistance of the device, the influence of space charge caused by doping impurities in the drift region of the device on the electric field can be exactly offset with the electric field concentration effect caused by the shape of the gallium nitride layer in the drift region, so that the electric field in the gallium nitride layer in the drift region can be uniformly distributed, and the device can obtain excellent voltage resistance.
Of course, under the influence of process conditions or other factors, the doping concentration of each position in the whole region or the set partial region of the drift region gallium nitride layer deviates
Figure BDA0003073403210000136
When, for example: the doping concentration of each position is
Figure BDA0003073403210000137
To
Figure BDA0003073403210000138
Or in between
Figure BDA0003073403210000139
To
Figure BDA00030734032100001310
To (c) to (d); the effect of space charge and the effect of electric field concentration can still be partially offset, so that the electric field distribution in the drift region gallium nitride layer 3 is relatively uniform, the device obtains better voltage endurance, and the doping concentration deviates
Figure BDA00030734032100001311
The more the withstand voltage is reduced.
It should be noted that the critical breakdown electric field strength Ec of the semiconductor material is influenced by the growth quality of the material and the doping of the material, and deviates from the theoretical value of the material.
For reference, this exampleExample it was calculated that typical values for the critical breakdown field strength of the gan layer 3 in the drift region were 4.0 x 106V/cm, and a relative dielectric constant of 9, the doping concentration in the GaN layer 3 in the drift region should be
Figure BDA00030734032100001312
Such as: when R is 5 μm, the doping concentration should be 3.98 × 1016cm-3
Of course, the above calculations are merely exemplary and are not intended as a limitation on the present patent protection scheme.
As an optional implementation manner, the side face of the drift region gallium nitride layer 3 is further provided with a side face strip-shaped drift region 9;
as an optional implementation manner, the surface of the drift region gallium nitride layer 3 is further provided with a surface strip-shaped drift region;
as an optional implementation manner, the surface of the drift region gallium nitride layer 3 is provided with a surface doped region, and the doping concentration of the surface doped region can be set according to the requirement, so as to reduce the on-resistance of the device surface region and increase the current capability of the device;
as an optional implementation scheme, the contact surface of the drift region gallium nitride layer 3 and the cathode 12 is in an inward concave arc shape to increase the contact area of the drain, reduce the contact resistance, and make the electric field distribution on the whole contact surface of the cathode 12 and the drift region gallium nitride layer 3 more uniform.
EXAMPLE five
According to an embodiment of the present invention, there is disclosed a gallium nitride diode, including; the drift region gallium nitride based on the GaN-based material comprises a substrate 1, a buffer dielectric layer 2 located above the substrate 1, and a drift region gallium nitride layer 3 located above the buffer dielectric layer 2, wherein a barrier layer 5 is arranged above the drift region gallium nitride layer 3, and an anode 11 and a cathode 12 are arranged above the barrier layer 5.
The difference between the structure of the gan diode in this embodiment and that in the fourth embodiment is: the boundary between the drift region gallium nitride layer 3 and the buffer medium layer 2 is an elliptic arc shape, or a multi-section arc shape formed by connecting two or more than two sections of arcs.
In this embodiment, an equivalent arc is determined based on the elliptical arc or the multi-segment arc; the method for determining the equivalent circular arc can select the following three modes:
selecting an arc with the smallest area enclosed by the boundary of the drift region gallium nitride layer 3 as an equivalent arc from all arcs intersected with the boundary of the drift region gallium nitride layer 3;
secondly, arcs with different curvature radiuses are made by taking two end points of the boundary of the drift region gallium nitride layer 3 as end points, and the arc with the smallest area enclosed by the boundary of the drift region gallium nitride layer 3 is selected as an equivalent arc;
thirdly, placing the circle center at the farthest point of the lower surface of the anode 12 from the cathode 11, manufacturing circles with different radiuses, cutting off the parts of the circles, which are positioned in three areas of the substrate 1, the buffer dielectric layer 2 and the drift region gallium nitride layer 3, to form a plurality of circular arcs, and after the boundary between the drift region gallium nitride layer 3 and the buffer dielectric layer 2 is connected with the plurality of circular arcs end to end, forming an equivalent circular arc corresponding to the circular arc with the smallest enclosed area.
Of course, those skilled in the art may select other ways to determine the equivalent circular arc according to actual needs, and the embodiment is not limited.
After the equivalent circular arc is determined, the doping concentration of each position in the whole region or the set partial region of the drift region gallium nitride layer 3 is the same as that in the fourth embodiment, except that in the determination formula of the doping concentration, R is the distance from the corresponding position to the center of the circle where the equivalent circular arc is located;
other technical solutions of this embodiment are the same as those of the fourth embodiment, and are not described herein again.
EXAMPLE six
According to an embodiment of the present invention, there is provided a method for manufacturing a gallium nitride power device, including the method for manufacturing a circular drift region gallium nitride layer illustrated in fig. 12(a) - (e3), since an actual semiconductor manufacturing process usually manufactures two devices with bilateral symmetry at one time, for the convenience of understanding of a skilled person, fig. 12(a) - (e3) illustrate a method for manufacturing two circular drift regions with bilateral symmetry at one time, the manufacturing method includes the following steps:
(1) forming an etching window on the surface of the substrate 1 by using photoresist, as shown in fig. 12 (a);
(2) etching the substrate 1 by using an etching technology to ensure that the etching depth of the substrate right below the center of the etching window reaches a set depth, wherein the set depth is a numerical value between 0 and the width of the etching window;
as an alternative embodiment, the etching depth of the substrate 1 at each position in the etching window range is 50% of the width of the etching window, as shown in fig. 12(b 1);
as another alternative, the etching depth of the substrate right under the center of the etching window is 50% of the width of the etching window, and the surface of the substrate 1 in the etching window is in the shape of a concave arc, as shown in fig. 12(b 2);
(3) continuing to etch the substrate 1 by using an isotropic etching technique to etch a concave region on the substrate 1, wherein the isotropic etching causes the boundary of the concave region to present an approximate arc shape, as shown in fig. 12 (c);
(4) removing the photoresist;
(5) depositing a buffer medium layer;
(6) depositing a drift region gallium nitride material with a set doping concentration, and gradually changing the doping concentration of the deposited material along with the increase of the deposition thickness so as to fill the drift region gallium nitride material with the gradually changed doping concentration in the concave region;
it should be noted that the deposition thickness of the gan material in the drift region may be set according to actual requirements, such that the recess region is completely filled, as shown in fig. 12(d1), or the recess region is not filled, as shown in fig. 12(d 2);
(7) and removing the deposited material and the substrate 1 above the set plane by using a chemical mechanical polishing process, and leaving the gallium nitride material in the original depressed area to form a drift area gallium nitride layer with the gradually changed doping concentration and the shape of the boundary being circular arc or approximate circular arc.
Those skilled in the art will understand that the position of the setting plane can be set according to actual needs; the circular arc in this embodiment refers to an arc of a standard circle; an approximate circular arc refers to an arc formed to have a shape close to a standard circle, but with some deviation, such as: an elliptical arc, or a multi-segment arc formed by connecting two or more segments of arcs, or a shape similar to an arc formed by connecting a straight segment with the arc or the elliptical arc or the multi-segment arc.
As an alternative embodiment, the plane is set to the upper surface of the original substrate, i.e., the upper surface of the substrate 1 in fig. 12(a), and based on this setting, the result of the chemical mechanical polishing in fig. 12(d1) is shown in fig. 12(e 1);
as another alternative, the plane is set to be the upper surface of the buffer dielectric layer after the buffer dielectric layer is deposited, and based on this setting, the result of chemical mechanical polishing in fig. 12(d1) is shown in fig. 12(e2), and the result of chemical mechanical polishing in fig. 12(d2) is shown in fig. 12(e 3);
as another alternative, the plane is set to be parallel to the upper surface of the substrate 1, and is located in the range from 0.2r above the upper surface of the substrate 1 to 0.2r below the upper surface of the substrate 1, where r is the radius of curvature of the arc formed by the boundary of the drift region.
The method can form the drift region gallium nitride layer with the boundary very close to the arc shape, can effectively control the doping concentration change of the drift region of the device, and has the advantages of few process steps and low cost.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.

Claims (10)

1. A gallium nitride power device, comprising: the semiconductor substrate is provided with a buffer medium layer above the semiconductor substrate, and a drift region gallium nitride layer is arranged above the buffer medium layer; the thickness of the whole area of the drift region gallium nitride layer or the thickness of the setting part area is gradually increased along the direction from the low potential electrode to the high potential electrode under the voltage-resistant state of the device, so that the field plate effect generated by the substrate meets the requirement of electric field optimization.
2. The gallium nitride power device according to claim 1, wherein a channel region gallium nitride layer is further disposed on the buffer dielectric layer, and a thickness of all or a set region of the channel region gallium nitride layer is smaller than an average thickness of the drift region gallium nitride layer.
3. The gallium nitride power device according to claim 1 or 2, wherein all or a predetermined portion of the boundary between the drift region gallium nitride layer and the buffer dielectric layer is in the shape of an arc;
alternatively, the first and second electrodes may be,
all boundaries or a set part of boundaries between the drift region gallium nitride layer and the buffer medium layer are in an elliptic arc shape, or a multi-section arc shape formed by connecting two or more than two sections of arcs.
4. A gan power device as claimed in claim 3 wherein the doping concentration of the whole or a predetermined part of the drift region is related to the distance R from the corresponding position to the center of the arc or the equivalent arc, in particular
Figure FDA0003073403200000011
To
Figure FDA0003073403200000012
Wherein E iscIs the critical breakdown electric field intensity of the material of the drift region0Is a vacuum dielectric constant of ∈rAnd q is the unit charge quantity, and R is the distance from the corresponding position to the center of the circular arc or the distance from the corresponding position to the center of the equivalent circular arc.
5. A gallium nitride power device according to claim 3, whereinCharacterized in that the doping concentration of the whole region or the set partial region in the drift region is related to the distance R from the corresponding position to the center of the arc or the center of the equivalent arc, specifically to
Figure FDA0003073403200000013
To
Figure FDA0003073403200000014
Wherein E iscIs the critical breakdown electric field intensity of the material of the drift region0Is a vacuum dielectric constant of ∈rAnd q is the unit charge quantity, and R is the distance from the corresponding position to the center of the circular arc or the distance from the corresponding position to the center of the equivalent circular arc.
6. A gallium nitride power device according to claim 3, wherein the arc of said arc is between 1/3 pi and 2/3 pi;
alternatively, the first and second electrodes may be,
the equivalent arc has a radian ranging from 1/3 pi to 2/3 pi.
7. The gallium nitride power device according to claim 3, wherein an included angle between a connecting line formed by an end point of the arc away from the upper surface of the gallium nitride layer in the drift region and a center of the arc and a vertical direction is greater than or equal to 0 ° and less than or equal to 30 °;
or an included angle between a connecting line formed by an end point of the equivalent arc far away from the upper surface of the drift region gallium nitride layer and the center of the equivalent arc and the vertical direction is more than or equal to 0 degree and less than or equal to 30 degrees.
8. The gallium nitride power device of claim 1, wherein the surface or side of the gallium nitride layer of the drift region is connected with the strip-shaped drift region;
or, a surface doping layer exists on the upper surface of the drift region gallium oxide layer, and the doping concentration of the surface doping layer is determined according to the requirement.
9. A power management chip, wherein the gallium nitride power device according to any one of claims 1 to 8 is used.
10. A preparation method of a gallium nitride power device is characterized by comprising the following steps:
forming an etching window on the surface of the substrate by using photoresist;
etching the substrate in the etching window by using an etching technology to ensure that the etching depth of the substrate right below the center of the etching window reaches the set requirement;
continuously etching the substrate by utilizing an isotropic etching technology to etch a concave region on the substrate and remove the photoresist; the isotropic etching technology enables the boundary of the sunken area to present an arc or an elliptic arc, or a multi-section arc formed by connecting two or more than two arcs, or a circular or approximately circular shape formed by connecting a straight line section with the arc or the elliptic arc or the multi-section arc;
depositing a buffer medium layer;
depositing a gallium nitride material with a set doping concentration, wherein the doping concentrations of the materials at different deposition thicknesses are gradually changed according to design requirements, so that a drift region gallium nitride layer with gradually changed doping concentrations is formed, and the total thickness of deposition is adjusted according to the design requirements;
and removing all materials above the set plane by using a chemical mechanical polishing process, and forming a drift region gallium nitride layer with a boundary shape of circular arc or approximate circular arc by the gallium nitride material left in the original sunken region.
CN202110545627.5A 2021-05-19 2021-05-19 Gallium nitride power device and preparation method thereof Active CN113270480B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110545627.5A CN113270480B (en) 2021-05-19 2021-05-19 Gallium nitride power device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110545627.5A CN113270480B (en) 2021-05-19 2021-05-19 Gallium nitride power device and preparation method thereof

Publications (2)

Publication Number Publication Date
CN113270480A true CN113270480A (en) 2021-08-17
CN113270480B CN113270480B (en) 2023-01-31

Family

ID=77231825

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110545627.5A Active CN113270480B (en) 2021-05-19 2021-05-19 Gallium nitride power device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN113270480B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916784A (en) * 2010-08-13 2010-12-15 四川长虹电器股份有限公司 SOI (Silicon on Insulator) variable buried oxide layer thickness device and preparation method thereof
CN103745996A (en) * 2013-12-31 2014-04-23 上海新傲科技股份有限公司 Lateral power device with partially insulated buried layer and manufacturing method
CN107799600A (en) * 2017-09-19 2018-03-13 西安电子科技大学 A kind of ladder high-K dielectric layer element vertical double-diffused MOS FET
CN108666366A (en) * 2018-07-05 2018-10-16 长沙理工大学 A kind of super-junction laterally high tension apparatus with ladder oxygen buried layer
CN208028069U (en) * 2018-01-23 2018-10-30 西安因变光电科技有限公司 Novel two-sided step buried oxide SOI LDMOS with buried structure
CN110429137A (en) * 2019-08-15 2019-11-08 西安电子科技大学 With partial nitridation gallium/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916784A (en) * 2010-08-13 2010-12-15 四川长虹电器股份有限公司 SOI (Silicon on Insulator) variable buried oxide layer thickness device and preparation method thereof
CN103745996A (en) * 2013-12-31 2014-04-23 上海新傲科技股份有限公司 Lateral power device with partially insulated buried layer and manufacturing method
CN107799600A (en) * 2017-09-19 2018-03-13 西安电子科技大学 A kind of ladder high-K dielectric layer element vertical double-diffused MOS FET
CN208028069U (en) * 2018-01-23 2018-10-30 西安因变光电科技有限公司 Novel two-sided step buried oxide SOI LDMOS with buried structure
CN108666366A (en) * 2018-07-05 2018-10-16 长沙理工大学 A kind of super-junction laterally high tension apparatus with ladder oxygen buried layer
CN110429137A (en) * 2019-08-15 2019-11-08 西安电子科技大学 With partial nitridation gallium/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof

Also Published As

Publication number Publication date
CN113270480B (en) 2023-01-31

Similar Documents

Publication Publication Date Title
CN102738211B (en) Approach to intergrate schottky in MOSFET and structure
US8563987B2 (en) Semiconductor device and method for fabricating the device
US11552172B2 (en) Silicon carbide device with compensation layer and method of manufacturing
US20180097069A1 (en) Semiconductor device and method of manufacturing semiconductor device
JP2017139499A (en) Method for manufacturing silicon carbide semiconductor device
US20140209999A1 (en) Semiconductor device
US10937859B2 (en) Method for manufacturing power device
CN111799322B (en) Double-groove type SiC MOSFET structure for high-frequency application and manufacturing method
US20180097102A1 (en) Semiconductor device and method of manufacturing a semiconductor device
CN112864246B (en) Superjunction device and method of manufacturing the same
KR20010102255A (en) Self-aligned silicon carbide lmosfet
CN113594255A (en) Groove type MOSFET device and preparation method thereof
CN113270481B (en) Circular drift region semiconductor device with gradually-changed doping concentration and preparation method thereof
CN112993021B (en) Lateral double-diffusion metal oxide semiconductor field effect transistor
US6355944B1 (en) Silicon carbide LMOSFET with gate reach-through protection
CN113270480B (en) Gallium nitride power device and preparation method thereof
US20220181504A1 (en) Semiconductor device and production method for semiconductor device
CN112909075A (en) Trench MOSFET with charge balance structure and manufacturing method thereof
CN110164957B (en) High-voltage semiconductor medium voltage-resistant terminal
KR102062050B1 (en) Combined gate trench and contact etch process and related structure
US8072027B2 (en) 3D channel architecture for semiconductor devices
JP2004335697A (en) Junction field effect transistor, its manufacturing method, and semiconductor device
CN111969055A (en) GaN high electron mobility transistor structure and manufacturing method thereof
CN111192915A (en) Semiconductor power device and method for manufacturing the same
US12002873B2 (en) Method for adjusting groove depth and method for manufacturing semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant