TW201340184A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A method for manufacturing a semiconductor device, wherein a gate structure part (100) including a gate insulating film (11) and a gate electrode (12) is formed on a semiconductor layer (10), and a gate sidewall film (16) that is an insulating film including a metallic material is formed on the sidewall of the gate structure part (100).

Description

Semiconductor device and method of manufacturing same Field of invention

The present invention relates to an electric field effect type semiconductor device and a method of fabricating the same.

Background of the invention

In order to reduce the power consumption of the CMOS device, the reduction of the parasitic resistance of the source/drain region (SD region) of the MOSFET has become an important technology. In recent years, in order to further reduce the parasitic resistance, the metal formation of the expanded region by the self-alignment process using a metal telluride such as nickel ruthenium is performed (for example, refer to Non-Patent Document 1). Regardless of the case of using such a metal SD structure, or an SD structure using a normal p/n junction, it is necessary to form the gate sidewall as thin as possible in order to sufficiently reduce the parasitic resistance.

Further, the metal SD structure has a problem of lowering the leakage current than when the p/n junction is used. In the metal SD structure in which the short-channel effect is suppressed and the leakage current is suppressed, a method of forming a p/n junction region in the lower portion of the metal SD region other than the expanded portion in contact with the channel is effective. (for example, Non-Patent Document 2). Therefore, it is proposed to form a very thin first gate sidewall film for reducing parasitic resistance on the sidewall of the gate and to form a second gate on the outside thereof. A semiconductor device having a double sidewall structure such as a sidewall film (for example, refer to Patent Document 1). However, even in such a case, it is necessary to form the gate side wall (first gate side wall film) as thin as possible.

Thus, either the formation of an SD region using a common p/n junction, the formation of an SD region using a metal SD, or the formation of an SD region in which a metal SD and a p/n junction are combined using a double sidewall is used. In this case, it is necessary to keep the insulating side of the side wall that is in contact with the gate to be as thin as possible. Therefore, it is necessary to have a process of forming a gate sidewall film in a well-controlled manner.

Conventionally, the gate sidewall film is generally made of an insulating film such as tantalum nitride or hafnium oxide. However, there is a problem in that the film is formed into a thin sidewall film by the RIE process (reactive ion etching process). That is, when a film species such as hafnium oxide or tantalum nitride is formed as a gate sidewall film, it may be etched to the gate insulating film and the substrate in the RIE for forming the sidewall. This is because the selection of the gate insulating film or the substrate of the gas such as trifluoromethane or carbon tetrafluoride used for the RIE for sidewall formation is smaller. This choice is smaller than this, which may cause the process boundary to be narrow and cause the substrate to be drilled. Such substrate excavation in the SD region, particularly in the case of substrate excavation in the expanded region, is expected to greatly increase the parasitic resistance of the MOEFET, increase the resistance variation of each element, and deteriorate the short channel effect. This is the main cause of deterioration or variation of part characteristics.

Advanced technical literature Patent literature

[Patent Document 1] JP-A-2005-217245

Non-patent literature

[Non-Patent Document 1] John M. Larson et al., Ieee Trans. Electron Devices, VOL. 53, No. 5 p1048

[Non-Patent Document 2] A. Kinoshita et al., 2005 Symp. VLSI Tech., 158

Summary of invention

An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can form a thin insulating film on the sidewall of a gate with good controllability without causing substrate boring or the like, and obtain characteristics improvement and variation of the component.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes a program for forming a gate structure portion including a gate insulating film and a gate electrode on a semiconductor layer, and a sidewall material including a metal material in the gate structure portion The procedure of the insulating film, that is, the gate sidewall film.

More specifically, since it is necessary to form the sidewall film with good control without causing the RIE by the RIE of the gate sidewall film formation, in order to achieve this, the sidewall film after the gate formation is performed as follows. form.

In other words, a metal material which is easily oxidized by tantalum nitride or titanium nitride and can be etched by RIE of a metal film and an oxide film (gate insulating film) with a gas having a higher selectivity than chlorine is used as a sidewall film. Deposition, and then RIE machining. Thereafter, only the metal film is oxidized by irradiating the plasma under oxygen supply, and it is used as a gate sidewall film.

Further, an electrode material which is easily oxidized such as tantalum nitride or titanium nitride is used for the gate electrode. On the other hand, the surface of the electrode is exposed in a state where the surface of the electrode after the formation of the gate electrode is exposed, and is used as an extremely thin sidewall film.

According to the present invention, since the gate sidewall film which is an insulating film containing a metal material is formed on the sidewall of the gate structure portion, a thin insulating film can be formed on the sidewall of the gate with good controllability without causing the substrate to be drilled. Therefore, an increase in the characteristics of the part, that is, a decrease in variation can be obtained.

More specifically, it has the following advantages as compared with the case of using a side wall of tantalum nitride or tantalum oxide of the prior art. In the RIE process for forming the sidewalls, the RIE selection ratio of the metal film to the oxide film (gate insulating film) is as high as about 20 or more in the case of chlorine, so that the etching of the gate insulating film caused by over-etching can be suppressed. Digging, the process has a wide range of boundaries. As a result of the foregoing, an expanded structure in which the parasitic resistance is small and the short channel effect can be suppressed can be obtained. Therefore, it is possible to realize a MOS transistor which obtains a high current with a lower gate overdrive.

10‧‧‧Semiconductor substrate

11, 51‧‧‧ gate insulation film

12, 22, 52‧‧ ‧ gate electrode

13‧‧‧ gate hard mask

14, 17‧‧‧ metal film

16‧‧‧gate sidewall film

18‧‧‧Metal-semiconductor alloy layer (metal SD structure)

19‧‧‧Source/bungee area (SD area)

26‧‧‧ Gate sidewall film (oxide film)

36‧‧‧Thicker sidewall film with thick film thickness

46‧‧‧gate sidewall film

50‧‧‧Insulated insulating film

68‧‧‧metal telluride layer

69‧‧‧Expanded area

100, 200, 300, 400, 500, 600, 700, 800‧‧‧ Gate Construction Department

1(a) to 1(d) are cross-sectional views showing the first half of the manufacturing procedure of the semiconductor device of the first embodiment.

2(a) to 2(d) are cross-sectional views showing the second half of the manufacturing procedure of the semiconductor device of the first embodiment.

3(a) to (c) show a program profile of a modification of the first embodiment. Figure.

4(a) to 4(b) are cross-sectional views showing a manufacturing procedure of the semiconductor device of the second embodiment.

5(a) to 5(d) are cross-sectional views showing a manufacturing procedure of the semiconductor device of the third embodiment.

6(a) to 6(d) are cross-sectional views showing a manufacturing procedure of the semiconductor device of the fourth embodiment.

7(a) to 7(d) are cross-sectional views showing the procedure of a modification of the fourth embodiment.

8(a) to 8(e) are cross-sectional views showing a manufacturing procedure of the semiconductor device of the fifth embodiment.

Form for implementing the invention

The details of the present invention are described below by way of embodiments shown in the drawings.

(First embodiment)

1 and 2 are cross-sectional views showing a manufacturing procedure of a semiconductor device according to the first embodiment.

First, as shown in FIG. 1(a), for example, a gate insulating film 11 having a thickness of 5 nm, for example, a gate electrode 12 having a thickness of 30 nm and a gate hard mask 13 are sequentially deposited on the semiconductor substrate 10 in the above-described order. Next, the gate hard mask 13 and the gate electrode 12 are etched by photolithography and RIE (Reactive Ion Etching). Thereby, the gate structure portion 100 is formed.

Here, the semiconductor substrate 10 may be a semiconductor including a high mobility material such as germanium or germanium, gallium arsenide, gallium antimonide, indium phosphide, indium gallium arsenide or indium arsenide. As the gate insulating film 11, an oxide or a nitride of a substance contained in the above semiconductor material can be used. Further, as the gate insulating film 11, alumina or yttrium oxide formed by in-situ atomic layer deposition (ALD) or chemical vapor deposition (CVD), physical vapor deposition (PVD) (sputtering), or the like may be used. Cerium oxide, zirconium oxide, lanthanum oxide (LaLuO ₃ ), aluminum oxide lanthanum (LaAlOx), aluminum oxide lanthanum (HfAlO), lanthanum oxide, lanthanum aluminum oxide (LaAlSiOx), amorphous yttrium (a-Si), twin An insulating film of a high dielectric constant material such as (c-Si), yttrium oxide or the like. Moreover, the gate electrode 12 may be tantalum nitride, titanium nitride, amorphous germanium, polycrystalline germanium, amorphous germanium (a-Ge), polycrystalline germanium (poly-Ge), tungsten, aluminum, palladium, titanium, chromium, Platinum, nickel, gold, nickel telluride, nickel germanium (NiGe), nickel telluride (NiSiGe), and the like. Further, the gate hard mask 13 may be tantalum nitride or tantalum oxide, polysilicon or the like.

Next, as shown in FIG. 1(b), the metal film 14 can be easily oxidized by irradiating the plasma in an oxygen atmosphere gas, and the metal film 14 is deposited by RIE using chlorine, boron trichloride, carbon tetrachloride, and hafnium tetrachloride gas. Approximately the desired film thickness (e.g., 3 nm). The metal film 14 is deposited by sputtering or CVD or the like. The material of the metal film 14 may, for example, be tantalum nitride, titanium nitride, aluminum nitride, tantalum, titanium, aluminum, nickel, tantalum, tungsten, amorphous germanium, polycrystalline germanium, amorphous germanium, polycrystalline germanium or the like.

Then, by performing RIE with a gas such as chlorine, boron trichloride, carbon tetrachloride or hafnium tetrachloride, the metal film 14 remains only on the sidewall of the gate as shown in Fig. 1(c). Here, in the RIE by a gas such as chlorine, the selection ratio of the metal film to the oxide film is extremely high at 20 or more. Therefore, the gate insulating film 11 is hardly etched, so that the semiconductor substrate 10 under the gate insulating film 11 is not etched.

Will include the metal film 14 of the gate sidewall formed by the above The gate structure portion 100 is exposed to oxygen gas, oxygen plasma, atomic oxygen, or the like for oxidation. As a result, as shown in FIG. 1(d), the metal film 14 such as tantalum nitride becomes an insulating oxide film such as tantalum oxynitride (TaNOx) or ruthenium oxide. Thereby, the gate structure portion 200 forming the extremely thin (for example, 5 nm) gate sidewall film 16 can be obtained.

Then, as shown in FIG. 2(a), the gate insulating film 11 exposed outside the gate structure portion 200 is removed. Next, as shown in FIG. 2(b), in order to form a metal-semiconductor alloy layer which is a metal-expanded region, the metal film 17 is deposited to have a thickness of, for example, 5 nm. Here, the metal film 17 may contain, for example, nickel, cobalt, titanium, platinum, palladium, tungsten, gold (AuGe), gold or the like.

Then, by annealing the alloy layer, the surface of the substrate 10 is reacted with the metal film 17, and as shown in Fig. 2(c), a metal-semiconductor alloy layer 18 (e.g., metal halide) is formed. Next, as shown in FIG. 2(d), the unreacted metal film 17 in the wet processing is removed. That is to say that the metal SD structure 18 from the self-aligning process can be obtained.

Thereafter, as in the conventional MOEFET manufacturing method, yttrium oxide or the like is deposited as an interlayer insulating layer, and contact holes are formed by photolithography, RIE, and wet processing. Further, contact is made by electrical contact with the SD region, and the MOS device is completed by wiring formation.

According to the present embodiment, the gate sidewall film 16 formed on the sidewall of the gate structure portion 100 is formed of an insulating film containing a metal material, whereby the gate sidewall controllability can be performed without causing substrate boring. A thin insulating film is formed well. Therefore, the improvement of the characteristics of the parts and the reduction of the variation can be obtained.

(Modification of the first embodiment)

As a modification of the first embodiment, an example of an SD region using p/n bonding is shown instead of a metal SD structure.

As shown in Fig. 3 (a), the gate structure portion 200 is obtained in the same manner as in the first embodiment (Fig. 1 (d)). However, in the case where the impurity is introduced by ion implantation as shown below, it is necessary to prevent the undesired doping in the channel directly under the gate caused by the gate of the impurity. Therefore, the ion implantation energy electrode 12 must be formed thicker than the first embodiment (for example, 50 nm or more).

Then, as shown in FIG. 3(b), the gate structure portion 200 is doped with impurities as a mask on the plate conductor substrate 10 by ion implantation, whereby the SD region 19 formed by p/n bonding is formed. Then, active annealing is performed. Here, in the case of an n-MOEFET, an n-type impurity is doped (for example, phosphorus or arsenic if the ruthenium or ruthenium substrate is used, and ruthenium as a III-V compound substrate such as gallium arsenide or the like). Further, in the case of the p-MOEFET, a p-type impurity is doped (for example, boron is used for the ruthenium or iridium substrate, and ruthenium is used for the III-V compound substrate such as gallium arsenide). Further, ion implantation into the expanded region or ion implantation for forming Halo may be performed.

Finally, as shown in FIG. 3(c), a metal film containing nickel, cobalt, titanium, platinum, palladium, tungsten, gold telluride, gold, or the like is formed and deuterated. Thereby, the metal germanide layer 68 is formed, and the contact resistance of the wiring layer is reduced and the resistance of the deep region of the SD region is reduced. However, 矽 in Figure 3(c) shows the expanded region 69 of ion implantation.

Thereafter, ruthenium oxide or the like is deposited as an interlayer insulating film to form a contact or the like, but the subsequent procedure is the same as that of the first embodiment, and is omitted here.

(Second embodiment)

Fig. 4 is a cross-sectional view showing a manufacturing procedure of the semiconductor device of the second embodiment. The same portions as those in the first and second portions are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 4(a), the gate structure portion 300 having the gate insulating film 11, the gate electrode 22, and the gate hard mask 13 is formed on the semiconductor substrate 10 as in the first embodiment (Fig. 4) 1(a)) is essentially the same. However, in the present embodiment, the material of the gate electrode 22 is desirably only including tantalum nitride, titanium nitride, aluminum nitride, amorphous germanium, polycrystalline germanium, amorphous germanium, polycrystalline germanium, palladium, titanium, tungsten, aluminum, Nickel, ruthenium, etc. are easily formed by oxidizing the surface of the metal such as oxygen plasma treatment.

After forming the gate structure portion 300 by using the oxidizable metal such as tantalum nitride or titanium nitride as the gate electrode 22, the gate electrode 22 is exposed to oxygen gas, oxygen plasma, atomic oxygen or the like. The side is oxidized. Further, as shown in FIG. 4(b), for example, an oxide film 26 having a thickness of 5 nm is formed. Thereby, the gate structure portion 400 forming the insulating gate sidewall film 26 is obtained.

After the gate structure portion 400 is formed, the metal SD structure 18 can be formed in the same manner as in the first embodiment. Further, since the subsequent procedures are the same as those in the first embodiment, they are omitted here.

As described above, in the present embodiment, by forming the gate sidewall film 26 by oxidizing the gate electrode 22, the substrate can be prevented from being formed when the gate sidewall film 26 is formed. Therefore, the same effects as those of the first embodiment can be obtained. Further, in the present embodiment, since the formation of the metal film 14 and the RIE are not required as compared with the first embodiment, the advantage of simplifying the manufacturing process can be obtained.

Modification of the second embodiment

As a modification of the second embodiment, an SD region formation using p/n bonding is shown instead of a metal SD structure.

It is the same as that of the second embodiment until the gate structure portion 400 is obtained. However, in the case where the p/n junction is formed by ion implantation, as described in the modification of the first embodiment, it is necessary to thicken the thickness of the gate electrode.

Then, if it is an n-MOEFET by an ion implantation method or the like, an n-type impurity is doped (for example, if the substrate is ruthenium or iridium, it is phosphorus or arsenic, and if it is a III-V compound substrate such as gallium arsenide or the like)矽) Just fine. Further, in the case of the p-MOEFET, a p-type impurity is doped (for example, boron is used for the ruthenium or iridium substrate, and ruthenium is used for the III-V compound substrate such as gallium arsenide). Further, ion implantation into the expanded region or ion implantation for forming Halo may be performed. Then, activation annealing is performed.

Then, cerium oxide is deposited as an interlayer insulating layer to form a contact layer, but the post-procedure is omitted here as in the first embodiment.

(Third embodiment)

Fig. 5 is a cross-sectional view showing a manufacturing procedure of the semiconductor device of the third embodiment. The same portions as those in the first to third embodiments are denoted by the same reference numerals, and the detailed description thereof will be omitted.

It is the same as that of the first embodiment until the gate structure having the gate side wall which is an insulating film is formed. That is, the gate structure portion 200 formed in the first embodiment is considered. However, this is also the same as the modification of the first embodiment, and the ion implantation process is performed thereafter. Therefore, the gate height must be increased to the same extent as the modification of the first embodiment.

Then, as shown in FIG. 5(a), the gate sidewall film 16 is formed. The gate structure portion (the gate structure portion 200) of the first gate film (the gate electrode film) has a gate structure portion 500 in which the gate sidewall film 36 (second gate sidewall film) is formed. Here, the gate sidewall film 36 may be an insulating film such as hafnium oxide or tantalum nitride. Further, in the formation of the gate sidewall film 36, a technique of so-called sidewall remaining which has been RIE-etched after the entire deposition of the insulating film is used may be used. The thickness of the gate sidewall film 36 may be, for example, about 20 nm, such as a diffusion length of the impurity in the lateral direction caused by ion implantation and activation after the sidewall formation.

Then, as shown in FIG. 5(b), if it is an n-MOEFET, it is doped with an n-type impurity (for example, if it is a germanium or germanium substrate, it is phosphorus or arsenic, etc., and if it is a III-V compound such as gallium indium arsenide) The substrate is 矽). Further, in the case of the p-MOEFET, a p-type impurity is doped (for example, boron is used for the ruthenium or iridium substrate, and ruthenium is used for the III-V compound substrate such as gallium arsenide). Further, the SD region 19 is formed by performing activation annealing.

Then, as shown in FIG. 5(c), the gate sidewall film 36 is removed by a wet treatment such as hydrofluoric acid or the like. Next, the gate insulating film 11 formed on the SD region 19 is removed by wet processing or the like.

Then, as shown in FIG. 5(d), the metal SD structure 18 is formed by depositing a metal material and performing annealing treatment as in the first embodiment. Here, the metal material for forming the metal-semiconductor alloy layer may be a metal of nickel, cobalt, titanium, platinum, palladium, tungsten, gold telluride, and gold. Thereby, the metal-semiconductor alloy layer 18 is formed in a self-aligned process. Next, when there is an unreacted metal, it is removed by a wet treatment or the like.

With the above procedure, the expansion is SD-metalized, and the doped region forms a p/n junction that can achieve low parasitic resistance and low leakage current. region.

According to this embodiment, the etching selectivity ratio of the first gate sidewall film 16 formed of tantalum oxide or the like and the second gate sidewall film 36 formed of tantalum oxide or the like can be increased. Therefore, when the gate sidewall film 36 is removed by etching, the gate sidewall film 16 remains in a state where it is hardly etched. Therefore, even if the structure in which the metal SD and the p/n junction are combined using the double side wall is used, the same effects as those of the first embodiment can be obtained.

(Modification of the third embodiment)

As a modification of the third embodiment, the side surface of the metal gate similar to that of the second embodiment is oxidized, and an example of a gate structure having a gate side wall of the insulating film is formed.

First, the side surface of the oxidized metal gate is formed to be the same as that of the second embodiment (Fig. 4(b)). That is, it is considered that the gate structure portion 400 of the second embodiment is formed. Hereinafter, since the metal SD region is formed by forming the second gate sidewall film 36, the third embodiment is the same, and thus the details thereof will be omitted.

(Other Modifications of Third Embodiment)

A further modification of the metal SD structure obtained as a modification of the third embodiment, which is a third embodiment, is an example in which an SD region using p/n bonding is formed.

In the modification of the third embodiment, the third embodiment is the same as the ion implantation in the doped region and the removal of the second gate sidewall film 36 (Fig. 5(c)). Then, ion implantation in the expanded region is performed while the first gate sidewall film 16 remains, and activation annealing is performed. After that, with the first embodiment In the same state, contact formation and wiring formation are performed by performing a post process. Thereby, a MOS element can be obtained.

(Fourth embodiment)

Fig. 6 is a cross-sectional view showing a manufacturing procedure of the semiconductor device of the fourth embodiment. The same portions as those in the first to third embodiments are denoted by the same reference numerals, and the detailed description thereof will be omitted.

Since the gate structure in which the side wall is not oxidized is formed in the same manner as in the first embodiment (Fig. 1 (c)), it is omitted here. Thereby, as shown in FIG. 6(a), the gate structure portion 600 in which the metal film 14 (first gate sidewall film) is formed on the gate sidewall can be regarded as being formed.

Then, as shown in FIG. 6(b), a gate structure portion 700 in which the gate sidewall film 36 is formed is formed. Here, the gate sidewall film 36 may be an insulating film such as hafnium oxide or tantalum nitride.

Then, as shown in FIG. 6(c), the source/drain region 19 is formed for the structure in which the gate structure portion 700 is formed. In other words, in the case of an n-MOEFET, an n-type impurity is implanted (for example, phosphorus or arsenic if the ruthenium or iridium substrate is used, and ruthenium is a ruthenium III-V compound substrate such as gallium arsenide or the like). Further, in the case of a p-MOEFET, a p-type impurity is implanted (for example, boron is used for a ruthenium or iridium substrate, and ruthenium or the like for a III-V compound substrate such as gallium arsenide ores). Then, activation annealing is performed.

Then, as shown in FIG. 6(d), the gate sidewall film 36 is removed by a wet treatment such as hydrofluoric acid. Here, since the metal film 14 of the gate sidewall film is exposed, the metal film 14 formed on the sidewall of the gate is oxidized by exposing it to oxygen gas, oxygen plasma, atomic oxygen or the like. By the above, the shape is obtained The gate structure portion of the gate film 16 (third gate sidewall film) which is an insulating film is formed.

Since the subsequent metal SD region forming process is the same as that of the third embodiment, it is omitted here. Further, in the same manner as in the first embodiment, a post-program is performed to form contact formation and wiring. Thereby, a MOS element can be obtained.

According to the present embodiment, in the state in which the metal film 14 of the one-gate sidewall film is formed on the sidewall of the gate structure 100, the formation of the two-gate sidewall film 36 and ion implantation, that is, the sidewall film 36 are performed. This is removed, and finally, the metal film 14 is oxidized to form the third gate insulating film 16. Thereby, the thin insulating film 16 can be formed with good controllability on the sidewall of the gate without causing substrate drilling or the like. Therefore, even in the structure in which the metal SD and the p/n junction are combined using the double side wall, the same effects as those of the first embodiment can be obtained.

(Fourth embodiment)

As shown in FIG. 7(a), the second embodiment (FIG. 4(a)) is the same as the formation of the gate structure portion 300. That is, the material of the gate electrode 22 is only easy to use oxygen oxide by including tantalum nitride, titanium nitride, aluminum nitride, amorphous germanium, polycrystalline germanium, amorphous germanium, tungsten, aluminum, nickel, germanium, and the like. It is composed of oxidized metal such as pulp.

Then, as shown in FIG. 7(b), a gate structure portion 800 in which the gate sidewall film 36 (first gate sidewall film) is formed is formed. Here, the gate sidewall film 36 may be an insulating film such as hafnium oxide or tantalum nitride. In the structure in which the gate structure portion 800 is formed, if it is an n-MOEFET, an n-type impurity is implanted (for example, if the substrate is germanium or germanium, it is phosphorus or arsenic, and the like is a III-V compound substrate such as gallium indium arsenide. then Yes, you can. Further, in the case of a p-MOEFET, a p-type impurity is implanted (for example, boron is used for a ruthenium or iridium substrate, and ruthenium or the like for a III-V compound substrate such as gallium arsenide ores). Then, activation annealing is performed. Thereby, the SD region 19 composed of the p/n junction is formed.

Then, as shown in FIG. 7(c), the gate sidewall film 36 is removed by a wet treatment such as hydrofluoric acid. In this state, since the side surface of the gate electrode 22 is exposed, oxidation is performed by oxygen plasma treatment or the like to oxidize the side surface of the gate electrode 22. Thereby, as shown in FIG. 7(d), a gate structure portion having an insulating gate sidewall film 46 (second gate sidewall film) can be formed on the sidewall of the gate electrode 22. At this time, the thickness of the gate sidewall film 46 can be formed to be extremely thin by controlling the oxidation time or the like.

The subsequent metal SD region forming process is omitted here as in the third embodiment. Further, in the same manner as in the first embodiment, contact formation and wiring formation are performed by performing a post process. Thereby, a MOS element can be obtained.

(Other Modifications of Fourth Embodiment)

As a modification of the fourth embodiment and its modifications, an example of formation of an SD region using p/n bonding is shown instead of using only an SD structure. The ion implantation in the deep region is performed in the same manner as in FIG. 7(d) until the second gate sidewall film 46 is formed (oxidized) after the first gate sidewall film 36 is removed.

Then, ion implantation is performed on the expanded region, and activation annealing is performed. Thereafter, in the same manner as in the first embodiment, contact formation and wiring formation are performed by performing a post process. Thereby, a MOS element can be obtained.

(Fifth Embodiment)

Fig. 8 is a view showing the system of the semiconductor device of the fifth embodiment; A profile view of the program. The same portions as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, in the case where the sidewall forming process shown in the first to fourth embodiments is combined and the gate electrode process is improved in the case of using a III-V group substrate such as a germanium, there is a promising replacement gate process. Example of component making.

Similarly to the first to fourth embodiments and the modifications thereof, the gate structure portion, the gate sidewall film, and the SD region are formed. Here, as an example, as shown in the procedure of FIG. 5(d) of the third embodiment, the gate insulating film 11, the gate electrode 12, and the gate hard mask 13 are used as the dummy gate structure. .

Then, as shown in FIG. 8(a), an insulating film 50 which is sufficient to sufficiently embed the yttrium oxide or the like of the dummy gate is formed by PECVD (plasma enhanced chemical vapor deposition) or the like.

Then, as shown in FIG. 8(b), CMP (Chemical Mechanical Polishing) treatment is performed to expose the head of the gate electrode 12 or the gate hard mask 13, or to reduce the gate electrode 12 and the gate hard mask 13. A few nm or so.

Then, as shown in FIG. 8(c), the gate hard mask 13, the gate electrode 12, and the gate insulating film 11 are removed by wet processing or RIE. Here, in the removal process of the gate hard mask 13 and the gate electrode 12, it is necessary to select a material having a sufficient removal selectivity from the embedded insulating film 50. For example, if the embedded insulating film 50 is yttrium oxide, the gate hard mask 13 is preferably tantalum nitride or the like, and the gate electrode 12 is preferably made of amorphous germanium or the like. This is because phosphoric acid is used if it is tantalum nitride, and tetramethylammonium hydroxide (TMAH) is used if it is polycrystalline germanium. The materials are selectively removed by etching to yttrium oxide.

Further, it is undesirable for the gate insulating film 11 to be damaged by the substrate 10 when the gate insulating film 11 is removed. Therefore, it is preferable to remove the film which can be removed only by the wet process and can be removed by etching without etching to the substrate, for example, hydrofluoric acid or the like. As such a film, cerium oxide, oxidized chlorine or the like can be exemplified.

After removing all of the dummy gate structures, as shown in FIG. 8(d), the gate insulating film 51 is again deposited by ALD or CVD. Further, the gate electrode 52 is deposited thereon by sputtering, CVD or the like. Next, as shown in FIG. 8(e), gate formation is performed by removing the gate electrode 52 on the insulating film 50 by CMP. Thereafter, by performing interlayer insulating film formation and wiring formation, a MOEFET having good interface characteristics and low parasitic resistance and low leakage current can be realized.

According to the present embodiment, by using the oxide film of a metal such as ruthenium oxynitride as the sidewall film 16 of the dummy gate structure, the remaining portion can be left in a state where the sidewall film 16 is hardly etched when the dummy gate structure is removed. . Therefore, as shown in the first to fourth embodiments, the thin side wall can be formed without the substrate being drilled. Further, the substrate can be prevented from being drilled by removing the gate insulating film 11 of the dummy gate structure by a wet process. Therefore, by combining the sidewall forming process and the replacement gate process shown in the first to fourth embodiments, it is possible to obtain an improvement in further component characteristics and a reduction in variation.

(Modification)

However, the present invention is not limited to the above embodiments.

The metal material for forming the gate sidewall film of the first embodiment is not limited to the embodiment, and may have a sufficient etching selectivity for the gate insulating film or the substrate.

In the first embodiment, the insulating gate sidewall film is formed by performing oxidation in a state where only the gate side wall is left with the metal film, but the invention is not limited thereto. For example, after the oxide film formed on the entire metal film is oxidized to form an insulating film, the insulating film is etched to leave the insulating film only on the sidewall of the gate. In this case, the material of the gate sidewall film formed of the insulating film may have a sufficient etching selectivity for the gate insulating film or the substrate.

Further, the semiconductor substrate is not necessarily limited to a bulk substrate, and may be a semiconductor layer formed on the substrate through the insulating layer.

The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. The invention and its modifications are intended to be included within the scope of the invention as defined by the appended claims.

10‧‧‧Semiconductor substrate

11‧‧‧Gate insulation film

12‧‧‧ gate electrode

13‧‧‧ gate hard mask

14‧‧‧Metal film

16‧‧‧gate sidewall film

100, 200‧‧‧ Gate Construction Department

Claims (10)

A method of manufacturing a semiconductor device is characterized in that a gate structure portion including a gate insulating film and a gate electrode is formed on a semiconductor layer, and a gate sidewall film including an insulating film of a metal material is formed on a sidewall of the gate structure portion . The method of manufacturing a semiconductor device according to claim 1, wherein the gate sidewall film is formed by forming a metal film on a sidewall of the gate structure portion, and then forming an insulating gate sidewall film by oxidizing the metal film. The method of fabricating a semiconductor device according to claim 1, wherein the gate sidewall film is formed by metal forming the gate electrode, and the insulating gate sidewall film is formed by oxidizing a side surface of the metal gate electrode. . A method of manufacturing a semiconductor device, wherein a gate structure portion including a gate insulating film and a gate electrode is formed on a semiconductor layer, and a first gate sidewall including an insulating film made of a metal material is formed on a sidewall of the gate structure portion a second gate sidewall film having a thickness different from that of the first gate sidewall film and having a thickness different from that of the first gate sidewall film, and the gate structure portion and the first portion are formed on the outer side of the first gate sidewall film 1 and the second gate sidewall film are used as a photomask, and the source/drain region is formed by doping impurities in the semiconductor layer, and the second gate sidewall film is removed after the source/drain region is formed. A method of manufacturing a semiconductor device is characterized in that a gate structure portion including a gate insulating film and a gate electrode is formed on a semiconductor layer, and a first gate sidewall film formed of a metal material is formed on a sidewall of the gate structure portion. The second gate sidewall film having a thickness smaller than that of the first gate sidewall film is formed on the outer side of the first gate sidewall film, and the gate structure portion and the first and the first a gate electrode film is used as a photomask, and a source/drain region is formed by doping impurities in the semiconductor layer, and the second gate sidewall film is removed after the source/drain region is formed, and the second gate is removed. After the pole sidewall film, an insulating third gate sidewall film is formed by oxidizing the first gate sidewall film. A method of manufacturing a semiconductor device, wherein a gate structure portion including a gate insulating film and a gate electrode formed of a metal material is formed on a semiconductor layer, and a first gate sidewall film is formed on a sidewall of the gate electrode, The gate structure portion and the first gate sidewall film are used as a photomask, and the source/drain region is formed by doping impurities in the semiconductor layer, and the first gate sidewall film is removed after the source/drain region is formed. After the first gate sidewall film is removed, the second gate sidewall film having a thickness smaller than that of the first gate sidewall film is deposited on the side surface of the gate electrode. The method of manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the substrate comprises a bismuth, antimony or III-V compound semiconductor body. The method of manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the metal material forming the gate sidewall film is made of tantalum nitride, titanium nitride, aluminum nitride, tantalum, titanium, aluminum, At least one selected from the group consisting of nickel, niobium and tungsten. The method of manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the side surface of the gate electrode is oxidized by using oxygen gas, oxygen plasma or atomic oxygen. A semiconductor device comprising a gate structure portion including a gate insulating film and a gate electrode formed on a semiconductor layer, and a gate sidewall film formed on a sidewall of the gate structure portion and comprising an insulating film of a metal material And a source/drain region formed on a surface portion of the semiconductor layer with the gate structure portion interposed therebetween.