JP2010093051A - Field-effect semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect semiconductor device assuring higher on-off ratio by controlling a leak current in the off period based on a subthreshold current without remarkable change in the existing manufacturing method. <P>SOLUTION: The field-effect semiconductor device includes a source region and a first drain region at least one of which is formed of a metal material or a polycrystal semiconductor and also includes a tunnel insulating film formed between the metal material or polycrystal semiconductor and a semiconductor channel layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a field effect semiconductor device, a metal-insulating film-semiconductor (MIS or MOS) field effect transistor (FET), and, for example, a MOS such as a complementary metal-insulating film-semiconductor (CMOS) semiconductor device. The present invention relates to a configuration of at least one of a source region and a drain region in an FET.

  Each transistor in a circuit using a conventional complementary transistor is a MIS transistor. As the integration increases, the size of the transistor is naturally reduced, and there is a demand for the power supply voltage to be as low as 1 V or less. However, even if the gate voltage is turned off, a diffusion current flows through the channel portion between the source and the drain, so that the threshold voltage cannot be lowered sufficiently.

  The occurrence of leakage in the sub-threshold region below this threshold voltage causes a great amount of power consumption during non-operation. The power consumption when used as a switch element has become ignorable. In order to avoid this, it is necessary to increase both the power supply voltage and the threshold voltage, and the current situation is that the demand for lowering the power supply voltage and lowering the threshold voltage cannot be met.

  FIG. 23 is an energy band diagram of a conventional MOSFET. Here, the state at the time of gate voltage off and drain bias is schematically shown. As shown in the figure, assuming that there is a gate electrode through a gate dielectric film in the direction perpendicular to the paper surface, an inversion layer channel is formed by applying a gate voltage to form a channel. However, minority carriers also exist in the channel portion when the gate voltage is off, and the diffusion current flows to the drain as a subthreshold current.

  Even when the gate voltage is in the off state, the channel is weakly inverted and minority carriers are generated exponentially with respect to the surface potential. Since the drain is biased in this state, an electric field is generated between the source and the drain, and the current flows by diffusion is the origin of this subthreshold current.

This current I is
I = −qAD _n (dn / dx)
_{≒ (qW c x c D n} / L c) n p0 × exp [qΨ _s (0) / kT]
Given in. Here, D _n is a carrier diffusion coefficient, A is a cross-sectional area (product of channel width W _c and effective channel thickness x _c ), n _p0 is a constant of minority carrier concentration, Ψ _s is a surface potential, and L _c is a channel. It is long. Further, q is an elementary charge, k is a Boltzmann constant, and T is an absolute temperature.
Carriers contributing to conduction are generated exponentially depending on the temperature T and the surface potential ψ _s , and this is explained by the fact that the carriers flow by diffusing the channel length.

Thus, the subthreshold current I does not depend on the drain voltage but depends on the temperature T and the surface potential Ψ _s . That is, exponentially with gate voltage _{V g,} (at room temperature ~66mV / dec or higher) proportion of q / kT is changing. Therefore, it has been shown that if the on-off ratio is to be 6 digits, at least the threshold voltage _Vth must be 396 mV or higher, and it has actually been difficult to reduce the operating voltage to 1 V or lower. For this reason, there has been a demand for a transistor that suppresses current caused by diffusion at the time of off and shifts at the time of on with an effect that has a stronger electric field dependency.

In order to meet such a demand, for example, a method using a tunnel current generated by applying a forward bias to a p ⁺ -n ⁺ junction has been reported by Banerjee et al. (See, for example, Non-Patent Document 1). When forward bias is applied to the p ⁺ -n ⁺ junction, the tunnel current is maximized when the Fermi energies of the n ⁺ type semiconductor and the p ⁺ type semiconductor coincide with each other, and the current decreases as the bias is further increased. Thus, this device operates with a negative differential resistance region.

Thereafter, a method of making such a p ⁺ -n ⁺ junction tunnel device a VMOS (V-groove MOS) type has been proposed (for example, see Patent Document 1). The current density J _bt of the band-to-band tunnel of this p ⁺ -n ⁺ junction is
J _bt = A [E _j ² / (E _g ) ^1/2 ] V × exp [−B (E _g ) ^3/2 / E _j ]
Given in. Where A and B are
A = (2m ^* ) ^1/2 q ³ / [4π ³ (h / 2π) ² ]
B = 4 (2 m ^* ) ^1/2 / [3q (h / 2π)]
Ej is a junction electric field.

Even if the p ⁺ -n ⁺ junction is a step-like junction, E _j depends on the square root of the applied voltage V. As a result, even if V is increased, the current does not change so much. According to the report by Literature 1, the on-off ratio of this device was not as high as about 5 (at the time of room temperature operation).

  In addition, Hideki Matsumura sandwiched a metal oxide with a short distance between the source and drain, provided a gate electrode on this metal oxide, and modulated the electric potential in this metal oxide by the electric field effect. Have proposed MITT (Metal Insulator Tunnel Transistor) that is operated by a tunnel current flowing through a metal oxide (see, for example, Patent Document 2).

In this proposal, a metal oxide is prepared as an insulator, and the potential barrier at the source and drain ends is modulated by an external gate electrode to change the tunnel current. Therefore, for convenience, the conductive part in the metal oxide is called a tunnel channel. Here, it is disclosed that a Cu / CuO _x film, a Zn / ZnO _x film, an Al / AlO _x film, or an Nb / NbO _x film is used in order to make the source-drain a short distance (16 nm). In this case, the source-drain must be brought close to each other with the tunnel channel interposed therebetween, which is difficult to manufacture.

To explain the operation principle of this device again, a gate electrode is provided in the tunnel channel to change the electric field of the tunnel barrier. That is, the tunnel current at the metal / metal oxide junction having the barrier barrier φ _ox is adjusted by the gate voltage. The tunnel current generated here is roughly classified into a Fowler-Nordheim (FN) tunnel current and a direct tunnel current. Here, a technique for controlling the FN current is used.

FN tunnel current density J _FN is J _FN = A′E _ox ² × exp [−B′φ _ox ^3/2 / E _ox ]
Given in. Where A ′ and B ′ are
A ′ = q ² / [16π ² (h / 2π) φ _ox ]
B ′ = A (2m ^* q) ^1/2 / [2 (h / 2π)]
E _ox is the electric field of the insulating film (tunnel channel).

In this device, when charge carriers are tunneled between the source and the drain, not only is E _ox determined from the voltage applied between the source and the drain, but also by the gate voltage applied to the gate electrode provided in the tunnel channel. The effective E _ox is modulated to achieve a state where more tunnel current flows. Since the FN current strongly depends on E _ox and φ _ox , it is expected that the on-off ratio can be increased.

  In addition, a method has been proposed in which a source / drain diffusion layer electrode periphery of a silicon MOS transistor is surrounded by an insulating film layer and a barrier against leakage is provided between the electrode and the channel (substrate). In this prototype, there is a report on a device named by Schwwchu et al. As TETRAN (Tunnel emitter transistor) (see, for example, Non-Patent Document 2). Ruzylo reports a similar device named “Surface Oxide Translator” (see, for example, Non-Patent Document 3).

  FIG. 24 is an energy band diagram of such a tunnel barrier MOSFET, FIG. 24 (a) is a schematic energy band diagram at the time of gate voltage off and drain bias, and FIG. 24 (b) is a gate voltage. on, a schematic energy band diagram at the time of drain bias.

As shown in FIG. 24A, since the tunnel insulating film is sandwiched between the channel and the drain, no current flows through the drain. Further, even when the gate voltage is off, carriers exist on the drain / tunnel film side due to the drain bias voltage _Vds . When this voltage V _ds is small, the number of carriers is small and tunnel current does not flow. However, when large V _ds is applied, tunnel current flows according to the value of V _ds .

As shown in FIG. 24B, a gate voltage is applied to the channel portion to form an inversion layer.
A tunnel insulating film is sandwiched between the source and the channel and between the channel and the drain. However, the source-drain bias V _ds causes an oxide film electric field in the tunnel film to reduce the effective film thickness. Current flows and the switch is turned on.

Hisamoto et al. Gave a method for fabricating a vertical MOS using a polysilicon channel with the channel portion of the diffusion layer electrode as a Schottky junction. In one example, a tunnel insulating film made of titanium oxide (TiO _x ) was used. A (MeSIS) stacked structure of a conductive region, a channel region, a tunnel insulating film, and a metal conductive region is proposed (see, for example, Patent Document 3). In addition, Baba et al. Have proposed a surface tunnel transistor (see, for example, Patent Document 4), and Tamura has proposed a dielectric base transistor (see, for example, Patent Document 5).

  As described above, a transistor having a high on-off ratio by suppressing a leakage current caused by the MOSFET sub-threshold current has been used so far by using a Schottky junction barrier or a tunnel film barrier in the source / drain portion. Was also made. By this method, a sharper junction than a semiconductor pn junction was formed, which was suitable for miniaturization.

  In addition, in a device having a channel length of several tens of nanometers, the carrier transport of the channel has become close to ballistic (non-collision) conduction, and the carrier injection speed into the channel can be modulated by focusing on the transport speed of the carrier alone. Attention was focused on conducting it.

In addition, it is difficult to fabricate a device having a channel length of several tens of nanometers on the surface by providing a source / drain by a shallow junction technique. Attention has been focused on nanowires.
JP 54-058378 A JP 08-264794 A JP 2001-028443 A JP 05-175514 A Japanese Patent Laid-Open No. 04-361534 EDL, Vol. 8, p. 347, 1987 SSE, Vol. 16, p. 213, 1973 EDL, Vol. 1, p. 197, 1980

However, a transistor manufactured using a tunnel film barrier in the source / drain portion, such as MeSIS described above, has been proposed.
(1) Structure that realizes low voltage operation with a sufficiently low off current and high on-off ratio (2) A method for realizing a complementary switch and a method for manufacturing a circuit such as a CMOS using the complementary switch are disclosed. Was not.

  The above-mentioned Patent Document 3 discloses a method for manufacturing a CMOS by changing the conductivity type of the silicon channel portion. However, the conductivity type of the silicon channel portion is used as a source / drain conductive region using a refractory metal. Only the configuration of the changed complementary gain cell circuit (CMOS inverter-like) is disclosed.

  Further, in the above-described tunnel barrier film transistor, a material combination of a wiring (conductive) region, a tunnel insulating film, a channel region, a tunnel insulating film, and a drain of the wiring (conductive) region is sequentially formed from the source wiring. In this past document, there is a conductive region of a refractory metal and a tunnel insulating film of an oxide or nitride of a refractory metal, and only the point of using materials such as titanium, tungsten, platinum, cobalt, and nickel has been disclosed.

  In addition, it should be noted that no efforts have been made regarding the low off-current, and in the past literature, the same material was used for the source and drain conductive regions.

  However, as a result of intensive studies by the present inventors, the disclosed configuration / material selection is not an optimal selection for low voltage operation with a sufficiently low off current and a high on-off ratio, and The source and drain materials were not shown to be good.

  In addition, as a method for manufacturing a complementary switch, only a method for changing the conductivity type of the channel is disclosed, and there is a problem that the manufacturing method is largely limited. Furthermore, there is a problem that a manufacturing method for suppressing the current at the time of off is not disclosed.

  Therefore, an object of the present invention is to increase the on-off ratio by suppressing the leakage current at the time of off due to the subthreshold current without significantly changing the conventional manufacturing method.

  From one aspect of the present invention, at least one of the first source region and the first drain region is made of the first metal or the first polycrystalline semiconductor, and the first metal or the first polycrystalline semiconductor and the first semiconductor channel layer. And a first tunnel insulating film formed between the first and second layers.

  From another viewpoint of the present invention, at least one of the first source region and the first drain region is made of the first metal or the first polycrystalline semiconductor, and the first metal or the first polycrystalline semiconductor and And an n-channel field effect transistor having a first tunnel insulating film formed between the first semiconductor channel layer and at least one of the second source region and the second drain region is made of a second metal or a second polycrystalline semiconductor. And a complementary transistor in which a p-channel field effect transistor having a second tunnel insulating film formed between the second metal or the second polycrystalline semiconductor and the second semiconductor channel layer is connected in series. A field effect semiconductor device is provided.

  According to the disclosed field effect semiconductor device, since a tunnel insulating film is provided on at least one of the source and drain, a high on-off ratio can be obtained with a low off current, and a large-scale operation with a low voltage is possible. Realization of a semiconductor integrated circuit device has become possible.

  Further, when a complementary field effect semiconductor device is configured, by using two or more kinds of sources or drains made of two or more kinds of metals, and two or more kinds of tunnel insulating films, the p-channel type transistor and the n-channel type transistor are used. A high on-off ratio can be obtained with a low off current.

  Here, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an energy band diagram of a tunnel barrier insulated gate field effect semiconductor device according to the present invention. FIG. 1 (a) is a schematic energy band diagram at the time of gate voltage off and drain bias. (B) is a schematic energy band diagram when the gate voltage is on and the drain bias is applied.

As shown in FIG. 1A, a bias voltage V _ds is applied between the source and the drain. At the gate voltage off, the channel portion is depleted, and the tunnel current is very small because the number of carriers in the channel portion is small. In addition, the barrier against majority carriers in the channel portion is also increased. That is, when the bias voltage V _ds between the source and the drain is small, the tunnel current does not flow, but when a large V _ds is applied, the tunnel current is caused to flow exponentially large according to the value of V _ds. Can do. This is because the tunnel insulating film is sandwiched between the channel and the drain, so that the drain current can be made extremely low even when a large V _ds is applied at the time of OFF.

As shown in FIG. 1B, a gate voltage is applied to the channel portion so that the channel portion is inverted and an inversion layer is formed. Since the tunnel barrier for majority carriers in the channel portion in the inverted state is low, the tunnel current easily flows. As a result, a tunnel insulating film is sandwiched between the source and the channel and between the channel and the drain, but an electric field is generated in the tunnel film due to the source-drain bias V _ds . Since a current flows at least as a tunnel current component between the drains, it acts as an on state as a switch in which the source-drain is brought into conduction by the gate voltage.

  Since the present invention is characterized by the type of tunnel insulating film and the type of metal used for the source region and the drain region, the circumstances will be described. FIG. 2 is a schematic energy band diagram near the tunnel barrier. As shown in FIG. 2A, when a tunnel current is caused to flow using electrons as carriers, the tunnel barrier barrier is lower when a material having a low effective work function of the material provided in the source or drain region is used. Suitable for becoming. On the other hand, as shown in FIG. 2B, when a tunnel current is caused to flow using holes as carriers, a material having a high effective work function of a material provided in a source or drain region has a higher tunnel barrier barrier. It is self-evident that it is suitable because of lowering.

  Therefore, in the present invention, in the case of an n-channel MOSFET, a material having a low work function is used on the source side so that the tunnel barrier barriers on the source side and the channel side can be lowered when the gate voltage is turned on. A material having a high work function is used on the drain side. On the other hand, in the case of a p-channel MOSFET, a material having a high work function is used on the source side, and a material having a low work function is used on the drain side. With such a configuration, it is possible to obtain a high on-current with a low standby leak and to increase the on-off ratio as compared with the case where the material type is not selected.

  In other words, in the conventional MOSFET, the source or drain and the off channel form a pn junction. Or even in the case of a Schottky junction, the junction on the source side is a junction having a rectifying action, and the switch is turned off by biasing the junction in the reverse direction. Therefore, the carrier flow from the channel to the drain portion is forward and there is no barrier. Therefore, the subthreshold current flows as described above.

  However, in the present invention, the subthreshold current from the channel to the drain stops flowing due to the tunnel insulating film provided in the channel-drain portion, and the current at the time of off can be lowered. Since this tunnel current strongly depends on the electric field generated at both ends of the tunnel insulating film, including the tunnel barrier barrier generated at the channel-drain, the barrier is lowered when on, and the tunnel current flows greatly due to the effect of the electric field. . In addition, since the tunnel current depends on the electric field, it is possible to operate with a high on-off ratio by generating a high electric field even at a low voltage by providing a thin tunnel film.

  In the complementary switch combinational logic circuit, the direction of the current from the source to the drain is determined in most elements except the transfer gate, so the work function of the source and drain materials adjusts the tunnel barrier. However, it was found that the leakage suppression and current drive performance are better.

  That is, in this complementary switch, since the current switch is controlled by a tunnel current at the drain portion, electron tunneling is considered in the n-channel FET, and hole tunneling is considered in the p-channel FET. If the height of the barrier is increased, the current at the time of off can be reduced, but the voltage needs to be increased in order to obtain the current at the time of on. For this reason, it is desirable to employ a metal / insulating film combination that forms separate barrier barriers for the source and drain in accordance with the direction of current from the source to the drain, that is, the source and drain of each transistor.

  Therefore, it is desirable to prepare two or more metals having different work functions so as to be a combination of metal / insulating film serving as separate barrier barriers. In addition, by preparing insulating films having different band gaps and changing the barrier height, the on-current can be increased with a low voltage due to the tunnel current.

  In the complementary FET, it is desirable to use a common metal material as the source of one FET and the drain of the other FET constituting the node in order to simplify manufacturing. That is, in the combination of NFET and PFET, the material is changed between the source of NFET and the drain of PFET, and the drain of NFET and the source of PFET.

  The channel portion can be used if the carrier transport efficiency can be changed. In other words, the structure using the semiconductor channel described above is a MISIM (Metal-Insulator-Semiconductor-Insulator-Metal) structure or a MOSOM (Metal-Oxide-Semiconductor-Oxide-Metal) structure, but is another structure. May be. For example, an MIM or MOM structure that tunnels without using a conductor channel, or an MIIIM structure or MOOOM structure that becomes a dielectric base or an insulator channel may be used. Further, MIMIM may be used with the channel portion as a metal.

  Note that in the case where the channel region is formed of a semiconductor such as Si, the conventional integrated circuit device can be manufactured without drastically changing the manufacturing method. In other words, in the manufacture of a normal MOSFET, the source, drain, and channel portions have been changed by doping silicon with impurities to change the conductivity type. However, the fine structure has a problem that it is difficult to produce a steep junction while performing high-concentration doping. However, since the present invention does not require high-concentration doping, miniaturization is facilitated. .

  Further, as shown in FIG. 3, the tunnel barrier may be provided on only one side of the source or the drain. FIG. 3 is a schematic energy band diagram of the off state of the tunnel barrier MOSFET in which the tunnel barrier is provided only on the drain side.

  It is necessary to select a suitable tunnel insulating film used for the tunnel barrier. For example, a titanium oxide film or a tantalum oxide film may be used for the tunnel insulating films on the source side of the n-channel FET and the drain side of the p-channel FET. This is because these oxide films have a relatively low barrier to conduction band silicon of about 0.3 eV to 0.5 eV, so that a Fowler-Nordheim (FN) tunnel current can easily flow from n-type silicon.

  Here, when the titanium oxide film (about 0.3 eV) and the tantalum oxide film (about 0.5 eV) are compared, the barrier barrier is different by about 0.2 eV, and thus a difference is also seen in the tunnel current. FIG. 4 shows the electric field (horizontal axis) dependence of the tunnel current (vertical axis) when the tunnel insulating film is changed from a titanium oxide film with a thickness of 4 nm to a tantalum oxide film with a thickness of 4 nm. In particular, in the case of a titanium oxide film, considering the operation at room temperature or higher, the barrier barrier is only 0.3 eV, and the current due to thermionic emission becomes significant. Difficult to take ratio. Thus, when the barrier barrier height is 0.3 eV or less, the off current tends to increase, which is not desirable.

Therefore, considering the operation from room temperature to high temperature, a hafnium oxide film (about 1.gV) has a barrier barrier of about 1 eV to 2 eV higher than the barrier barrier of these oxide films and can suppress thermionic emission current. 5 eV). In addition, SrSiO, ZrSiO, HfSiO, ZrO ₂ , SrTiO ₃ , BiTiO ₃ , La ₂ O ₃ , T ₂ O ₃ , LaAlO ₃ , LaScO ₃ , Al ₂ O ₃ , Gd ₂ O ₅ , (La _x Y _{1 -x) 2 O 3, (Sm} x Y 1-x) 2 O 3, (Ce x Y 1-x) 2 O 3, and the like _{(Gd x Y 1-x)} 2 O 3.

  On the other hand, if the barrier barrier is as high as 3 eV or more, it is difficult to obtain a high electric field at a low voltage, and a tunnel current cannot flow. Therefore, it is desirable to configure the tunnel film with a material that becomes a barrier barrier of 0.3 eV to 3 eV or less.

  Even if the same tunnel insulating film is used, the barrier barrier can be changed by using a metal having a work function of about 4.0 eV such as aluminum or magnesium as the metal constituting the source or drain as described above. In this case, tantalum or titanium having a low work function can be used as the metal constituting the source or drain. In addition, a nitride containing a tantalum or titanium metal or a carbide containing the metal can be used.

When gold or the like having a high work function is used, an STO (SrTiO ₃ ) film or the like can be used as the tunnel insulating film. Besides _{that, SrSiO, ZrSiO, HfSiO, ZrO} 2, BiTiO 3, La 2 O 3, T 2 O 3, LaAlO 3, LaScO 3, Al 2 O 3, Gd 2 O 5, (La x Y 1-x) ₂ O ₃ , (Sm _x Y _1-x ) ₂ O ₃ , (Ce _x Y _1-x ) ₂ O ₃ , (Gd _x Y _1-x ) ₂ O _{3 and the} like.

  On the other hand, a silicon nitride film can be used for the tunnel insulating films on the source side of the p-channel FET and the drain side of the n-channel FET. Since the barrier barrier of the tunnel is increased and thereby the tunnel current is also decreased, the tunnel insulating film can be adjusted by reducing the thickness. In this case, molybdenum or platinum having a high work function can be used as the metal constituting the source or drain. In addition, a nitride containing a metal such as molybdenum, hafnium, or tungsten can be used.

If the tunnel current at the time of OFF is to be lowered to about 1 pA / μm ² or less, a lower limit is set for the barrier barrier. This is because the current due to heat release cannot be ignored. The heat emission current decreases exponentially with the barrier barrier height. In general, the barrier barrier height needs to be about 0.9 eV under the condition of 1 pA / 1 μm ² or less near room temperature. Considering the operating temperature up to about 150 ° C., about 1.3 eV is required.

On the other hand, since the tunnel current changes by changing the effective thickness of the tunnel film, that is, by the electric field of the tunnel insulating film, in the junction where the barrier barrier height is 3.1 eV, an electric field of 8 MV / cm is 5 × Only 10 ^-15 A / μm ² flows. However, if the barrier height of the barrier is changed and lowered to about 1 eV, the current is about 1 pA / 1 μm ² when an electric field of 1 MV / cm is applied, and the current increases exponentially as the electric field is increased. To do. As described above, if the insulation deterioration is not caused so as to function as an insulating film in a low electric field, the tunnel current can be controlled so that the tunnel current does not flow even in the off state.

  Note that in order to increase the tunnel current, a high electric field may be applied to the insulating film, and by reducing the size of the transistor (switch) to several tens of nanometers, the potential generation region is increased. This can be achieved by narrowing the gap.

  The above guidelines for the combination of the electrode and the tunnel insulating film can be obtained from literature values. FIG. 5 summarizes the band gaps of various reported insulators (if necessary, Robertson, J. Vac. Sci. Technol., Vol. B18, p. 1785, 2000 and Afanas'ev, J. Appl.Phys., Vol.102, p.081301, 2007).

  In the figure, Gap indicates the energy gap between the valence band and the conduction band, and EA indicates the electronegativity, indicating the energy difference from the valence band to the vacuum level. ing. Therefore, an offset (CB offset) from the conduction band of Si is obtained, which becomes an electron barrier barrier against silicon. Moreover, since an offset (VB offset) from the valence band on the hole side of silicon is also obtained based on the gap energy, this becomes a barrier for holes.

  FIG. 6 is a bar graph showing the barrier barriers for the valence band and the conduction band of various insulating films with respect to the band gap of Si and Ge shown at the left end. In the figure, the energy of the valence band of Si is represented as 0, and the work function corresponds to 5.1 eV. FIG. 7 shows VB offset at the interface between various metals and Si.

  As described above, according to the present invention, the tunnel insulating film and the metal material to be used are appropriately selected in accordance with the n-channel MOSFET and the p-channel MOSFET on the drain side and the source side, thereby being high with low standby leakage. An on-current can be obtained and the on-off ratio can be increased.

  Based on the above, next, the tunnel barrier FET according to the first embodiment of the present invention will be described with reference to FIGS. In addition, the upper figure in each figure is a top view, and the lower figure is sectional drawing along the dashed-dotted line which connects AA 'in an upper figure. First, as shown in FIG. 8A, an STI element isolation region 12 is formed on a silicon substrate 11 and then B is introduced to form a p-type well region 13. Next, after sequentially forming the gate insulating film 14 and the gate electrode 15, the sidewall 16 is formed by anisotropically etching the insulating film deposited on the entire surface.

  Next, as shown in FIG. 8B, the exposed portion of the p-type well region 13 is etched using the resist pattern 17, the sidewall 16, and the STI element isolation region 12 as a mask to form a recess 18 having a depth of, for example, 10 nm. Form.

Next, as shown in FIG. 9C, after removing the resist pattern 17, a new resist pattern 19 exposing the source region is formed, and the resist pattern 19 is used as a mask to form a thickness of 2 to 5 nm. A tunnel insulating film 20 made of ₂ nm of HfO ₂ is deposited. Subsequently, Al having a thickness of, for example, 10 nm is deposited. Thereafter, Al deposited on the resist in the step of removing the resist pattern 19 is peeled off to form the metal source 21.

Next, as shown in FIG. 9D, after the resist pattern 19 is removed, a new resist pattern 22 that exposes the drain region is formed. Using this resist pattern 22 as a mask, a thickness of 2 to 5 nm, for example, A tunnel insulating film 23 made of ₂ nm of HfO ₂ is deposited. Subsequently, Pt having a thickness of, for example, 10 nm is deposited. Thereafter, Al deposited on the resist in the step of removing the resist pattern 22 is peeled off to form a metal drain 24.

  Next, as shown in FIG. 10E, an insulating film 25 is formed on the entire surface, and then contact holes 26 to 28 are formed in the insulating film 25. Next, as shown in FIG. 10 (f), the contact holes 26 to 28 are filled with tungsten, and tungsten other than the contact plug portion is removed by chemical mechanical polishing (CMP), whereby the source electrode 29, the drain electrode 30, And it becomes a plug of the gate extraction electrode 31. By wiring to these electrodes, the basic configuration of the tunnel barrier FET of Example 1 of the present invention is completed.

  Thus, in Example 1 of the present invention, in the tunnel barrier n-channel FET, the metal source 21 is formed of Al having a work function of about 4 eV, and the metal drain 24 is formed of Pt having a work function of about 5 eV. Therefore, electrons are likely to flow through the tunnel due to the bias between the gate and the source, and a leak current hardly flows with the bias between the gate and the drain.

  Therefore, it is possible to obtain a high on-current with low standby leakage and to increase the on-off ratio. In addition, since it is not necessary to form source / drain regions and extension regions by ion implantation, the impurity concentration is not required to be controlled and the structure is suitable for miniaturization.

In Example 1, since the tunnel insulating films 20 and 23 are made of HfO ₂ having a barrier barrier of about 1.5 eV, the thermionic emission current can be suppressed. The tunnel insulating films 20 and 23 are not limited to pure HfO ₂ and may be any Hf-containing oxide film, and may contain Si or Al. The metal source made of Al may be silicide such as HfSi or TaSi, or nitride thereof. Further, HfN, TiN, or RuN may be used as the metal drain made of Pt.

  Next, a tunnel barrier MOSFET according to Example 2 of the present invention will be described with reference to FIGS. First, as shown in FIG. 11A, an STI element isolation region 12 is formed on a silicon substrate 11 and then B is introduced to form a p-type well region 13. Next, the gate insulating film 14 and the gate electrode 15 are sequentially formed.

Next, as shown in FIG. 11B, the exposed portion of the p-type well region 13 is etched using the resist pattern 17 and the STI element isolation region 12 as a mask to form a recess 32 having a depth of, for example, 10 nm. Then, a tunnel insulating film 33 made of HfO _{2 having} a thickness of ₂ to 5 nm, for example, 2 nm is deposited.

  Next, as shown in FIG. 11C, after the resist pattern 17 is removed, an Al film 34 having a thickness of 10 to 100 nm, for example, 10 nm is deposited by tilted ion beam irradiation. Next, as shown in FIG. 12D, a Pt film 35 having a thickness of 10 to 100 nm, for example, 10 nm is deposited by tilted ion beam irradiation from the opposite direction.

  Next, as shown in FIG. 12E, by removing the Al film 34 and the Pt film 35 deposited on the undesired portions, the remaining Al film 34 as a main part is used as the metal source 36, and the remaining portions are left. A portion having the Pt film as a main part is referred to as a metal drain 37.

  Next, as shown in FIG. 12 (f), after forming an insulating film 25 on the entire surface, a contact hole is formed in the insulating film 25, and then the contact hole is filled with tungsten to form a source electrode 29, a drain electrode 30, By forming the gate extraction electrode 31, the basic configuration of the tunnel barrier MOSFET according to the second embodiment of the present invention is completed.

  Thus, also in Example 2 of the present invention, in the tunnel barrier n-channel MOSFET, the metal source 36 is formed of Al having a work function of about 4 eV, and the metal drain 37 is formed of Pt having a work function of about 5 eV. Therefore, electrons easily flow through the tunnel due to the bias between the gate and the source, and the leak current hardly flows with the bias between the gate and the drain.

Also in Example 2, the tunnel insulating film 33 is formed of HfO ₂ having a barrier barrier of about 1.5 eV, so that the thermionic emission current can be suppressed. The tunnel insulating film 33 is not limited to pure HfO ₂ and may be any Hf-containing oxide film and may contain Si or Al. Further, this tunnel insulating film is also formed by using a tilted ion beam deposition method so that the source side tunnel insulating film is made of TiO ₂ or the like having a low barrier barrier, and the drain side tunnel insulating film is made of HfO ₂ or the like having a high barrier barrier. The tunnel insulating film may be formed of different insulating films.

  In Example 2 of the present invention, since the metal source and the metal drain are formed by the tilted ion beam deposition method, the resist pattern is formed twice when the metal source and the metal drain are formed of different metals. Since the process becomes unnecessary, the process is simplified. However, in this case, the direction of the source and drain with respect to the gate needs to be unified in the layout.

  Next, a tunnel barrier MOSFET according to a third embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 13A, an STI element isolation region 12 is formed on a silicon substrate 11 and then B is introduced to form a p-type well region 13. Next, the gate insulating film 14 and the gate electrode 15 are sequentially formed. Next, as shown in FIG. 13B, the exposed portion of the p-type well region 13 and the STI element isolation region 12 are etched using the resist pattern 38 as a mask.

Next, as shown in FIG. 13C, after removing the resist pattern 38, a tunnel insulating film 39 made of TiO _{2 having} a thickness of ₂ to 5 nm, for example, 2 nm, using a tilted ion beam deposition method from one direction. To deposit. Next, as shown in FIG. 13D, a tunnel insulating film 40 made of HfO _{2 having} a thickness of ₂ to 5 nm, for example, 2 nm, is deposited by irradiation with a tilted ion beam from the opposite direction.

  Next, as shown in FIG. 14E, an Al film 41 having a thickness of 10 to 100 nm, for example, 10 nm is deposited again using a tilted ion beam deposition method from one direction. Next, as shown in FIG. 14F, a Pt film 42 having a thickness of 10 to 100 nm, for example, 10 nm is deposited by irradiation with a tilted ion beam from the opposite direction.

  Next, as shown in FIG. 14 (g), the Al film 41 and the Pt film 42 deposited on the unnecessary portion are removed, so that the portion having the remaining Al film 41 as the main part becomes the metal source 43, and the remaining Pt A portion having the film 42 as a main part is a metal drain 44.

  Next, as shown in FIG. 14 (h), after forming an insulating film 25 on the entire surface, a contact hole is formed in the insulating film 25, and then the contact hole is filled with tungsten to form a source electrode 29, a drain electrode 30, By forming the gate extraction electrode 31, the basic configuration of the tunnel barrier FET according to the third embodiment of the present invention is completed.

  In the third embodiment of the present invention, since the metal source and metal drain forming portion including the STI element isolation region 12 is flattened, the surface of the vicinity of the STI element isolation region 12 is completely and double with a tunnel insulating film. It is not covered and exposed, and even if a metal film is deposited in the region, there is no short circuit with the semiconductor substrate, and no leakage current flows.

  Next, an inverter using the tunnel barrier FET according to the fourth embodiment of the present invention will be described with reference to FIG. 15. However, since the basic manufacturing process is the same as that of the first embodiment, only the final structure is shown. . FIG. 15A is a plan view of a tunnel barrier FET inverter according to the fourth embodiment of the present invention, and FIG. 15B is a cross-sectional view taken along the alternate long and short dash line connecting AA ′ in FIG. It is.

  As shown in the figure, after forming an STI element isolation region 53 reaching the insulating film 52 on an SOI substrate in which a silicon layer is formed on the silicon substrate 51 via the insulating film 52, B is introduced to introduce a p-type field region 55. , P are introduced to form the n-type field region 54. Next, after sequentially forming the gate insulating film 56 and the gate electrodes 57 and 58, the sidewalls 59 and 60 are formed.

Next, using the resist pattern (not shown) as a mask, the exposed portions of the p-type field region 55 and the n-type field region 54 are etched to form recesses. Next, after removing the resist pattern, the resist pattern (not shown) having an opening exposing only the concave portion formed near the STI element isolation region 53 of the p-type field region 55 is used as a mask with a thickness of 2 to 5 nm. For example, a tunnel insulating film 61 made of ₂ nm of HfO ₂ is deposited. Subsequently, a metal source 62 is formed by depositing an Al film having a thickness of 10 to 100 nm, for example, 10 nm.

Next, HfO _{2 having} a thickness of 2 to ₅ nm, for example, 2 nm, is newly formed using as a mask a resist pattern (not shown) having an opening that exposes only the recess provided between both gate electrodes 57 and 58. A tunnel insulating film 63 made of is deposited. Subsequently, a metal film 64 is formed by depositing a Ti film having a thickness of 10 to 100 nm, for example, 10 nm.

Next, a resist pattern (not shown) having an opening that exposes only a recess formed in the n-type field region 54 near the STI element isolation region 53 is used as a mask to form a thickness of 2 to 5 nm. For example, a tunnel insulating film 65 made of ₂ nm of HfO ₂ is deposited. Subsequently, a metal drain 66 is formed by depositing a Pt film having a thickness of 10 to 100 nm, for example, 10 nm.

  Next, after an insulating film 67 is formed on the entire surface, a contact hole is formed in the insulating film 67, and then the contact hole is filled with tungsten to form a source electrode 68, a drain electrode 69, gate lead electrodes 70 and 71, and an output. By forming the electrode 72, the basic configuration of the tunnel barrier FET inverter of Example 4 of the present invention is completed.

  A metal having a large work function, such as Pt, can reduce leakage current when used as a drain of an n-channel FET, and facilitates injection of holes when used as a source of a p-channel FET. become. In the fourth embodiment of the present invention, Ti is used as the metal node for the drain of the n-channel FET and the source of the p-channel FET, taking advantage of such characteristics, thereby simplifying the manufacturing process. Is done.

  Next, a tunnel barrier FET inverter according to the fifth embodiment of the present invention will be described with reference to FIG. Since the basic manufacturing process is the same as in the first embodiment, only the final structure is shown. FIG. 16A is a plan view of the tunnel barrier FET inverter according to the fifth embodiment of the present invention, and FIG. 16B is a cross-sectional view taken along the alternate long and short dash line connecting AA ′ in FIG. It is.

  As shown in the figure, after forming an STI element isolation region 53 reaching the insulating film 52 on an SOI substrate in which a silicon layer is formed on the silicon substrate 51 via the insulating film 52, B is introduced to introduce a p-type field region 55. , P are introduced to form the n-type field region 54. Next, after sequentially forming the gate insulating film 56 and the gate electrodes 57 and 58, the sidewalls 59 and 60 are formed.

Next, using a resist pattern (not shown) as a mask, only the exposed portion between both gate electrodes 57 and 58 is etched so as to reach the insulating film 52 to form a recess. Next, a tunnel insulating film 63 made of HfO _{2 having} a thickness of ₂ to 5 nm, for example, 2 nm is deposited. Subsequently, a Ti film having a thickness of 10 to 100 nm, for example, 10 nm is deposited to form a metal node 64 for output of the inverter.

  Next, an Al film having a thickness of 10 to 100 nm, for example, 10 nm is deposited in a region near the STI element isolation region 53 of the p-type field region 55 using a new resist pattern to form an electrode 73 connected to a circuit power supply. .

  Next, a Pt film having a thickness of 10 to 100 nm, for example, 10 nm is deposited in a region near the STI element isolation region 53 of the n-type field region 54 using a new resist pattern to form an electrode 74 connected to circuit ground. .

  Next, after an insulating film 67 is formed on the entire surface, a contact hole is formed in the insulating film 67, and then the contact hole is filled with tungsten to form a source electrode 68, a drain electrode 69, gate lead electrodes 70 and 71, and an output. By forming the electrode 72, the basic configuration of the tunnel barrier FET inverter according to the fifth embodiment of the present invention is completed.

In the fifth embodiment of the present invention, similarly to the fourth embodiment, Al or Pt is used as a metal node taking advantage of the work function characteristics, and Ti is shared as the drain of the n-channel FET and the source of the p-channel FET. Therefore, the manufacturing process is simplified. In the fifth embodiment, since the tunnel insulating film is not provided on the source on the V _ss side and the drain on the V _dd side, the process is simplified from this point.

  Next, a tunnel barrier FET inverter according to the sixth embodiment of the present invention will be described with reference to FIG. FIG. 17A is a plan view of a tunnel barrier FET inverter according to the sixth embodiment of the present invention, and FIG. 17B is a cross-sectional view taken along the alternate long and short dash line connecting AA ′ in FIG. FIG. 17C is a cross-sectional view taken along the alternate long and short dash line connecting B-B ′ in FIG.

  As shown in the figure, after a silicon layer having a thickness of, for example, 50 nm is formed on a silicon substrate 81 via an insulating film 82, two band-shaped silicon regions having a width of 50 nm, a length of 200 nm, and a distance of 200 nm are formed. 83 and 84 are formed. One silicon region 83 is doped with P, and the other silicon region 84 is doped with B.

By thermally oxidizing the band-shaped silicon, oxidation of the end of the band-shaped silicon proceeds, and silicon nanowires surrounded by the oxide film are formed. The silicon oxide film can be selectively removed by HF. Alternatively, the oxide film in the SOI or the element isolation trench is excessively eroded by an oxide film removing process that forms ammonia fluoride on the surface of dry H ₂ plasma / NF ₃ , NH ₃ / NF ₃ , NH ₃ / HF, or the like. It is removed without.

Next, after depositing an HfO ₂ film having a thickness of 2 to ₅ nm, for example, 4 nm on the entire surface, a gate electrode material is deposited and etched into a predetermined shape, thereby forming the gate insulating film 85 and the gate electrode 86. . In this case, the HfO ₂ film remaining on the end face in the length direction of the silicon nanowire made of the silicon regions 83 and 84 becomes the tunnel insulating film 87. The tunnel insulating film 87 at the end face is thinner and is 2 nm or less.

  Next, a metal node 88 is formed by selectively depositing a Pt film on one end face of two silicon nanowires using the resist pattern as a mask. Next, a metal source 89 is formed by selectively depositing an Al film on the other side end face of one silicon nanowire (83) using a new resist pattern as a mask. Next, a metal drain 90 is formed by selectively depositing a Pt film or an Al film on the other end face of the other silicon nanowire (84) using the new resist pattern as a mask.

  Next, after forming an insulating film (not shown) on the entire surface, a contact hole is formed in this insulating film, and then the contact hole is filled with tungsten to form a source electrode 91, a drain electrode 92, a gate lead electrode 93, and By forming the output electrode 94, the basic configuration of the tunnel barrier FET inverter according to the sixth embodiment of the present invention is completed.

In Example 6 of the present invention, since silicon nanowires are used, an ultrafine inverter can be configured. Further, in this case, since two silicon nanowires arranged in parallel are used, an etching process requiring processing accuracy when forming the metal node is not required. In Example 6, the V _ss side tunnel insulating film and the V _dd side tunnel insulating film may be omitted.

  Next, a static random access memory (SRAM) using a tunnel barrier FET inverter according to the seventh embodiment of the present invention will be described with reference to FIG. FIG. 18 is a plan view of an SRAM using a tunnel barrier CMOS according to a seventh embodiment of the present invention, in which two tunnel barrier FET inverters shown in FIG. It is a thing.

In this case, the bit line B and the word line W are used for access to the metal node 88. For the transfer, normal FETs 95 and 96 are used, and the metal node 88 is connected by the local wiring layers 97 and 98. . Incidentally, the tunnel insulating film and the V _dd side of the tunnel insulating film also V _ss side in the seventh embodiment may be omitted.

Next, a vertical tunnel barrier FET inverter according to an eighth embodiment of the present invention will be described with reference to FIGS. In each figure, the left figure is a plan view, and the right figure is a cross-sectional view taken along the alternate long and short dash line connecting AA 'in the left figure. First, as shown in FIG. 19A, after forming an STI element isolation region 102 on an n-type silicon substrate 101, As is introduced to form an n ⁺ -type drain region 103, and B is introduced to form a p ⁺ -type. A source region 104 is formed.

Next, as shown in FIG. 19B, after depositing a SiO ₂ film, two openings 105 and 106 having a diameter of, for example, 20 nm are formed to form a selective growth mask 107. In the opening of the selective growth mask, a silicon-melting metal such as Au that progresses nanowire growth is formed. Next, as shown in FIG. 19C, silicon nanowires 108 and 109 made of single crystal silicon having a height of, for example, 100 nm are selectively grown in the openings 105 and 106 using the selective growth mask 107 as a mask.

  When silane gas is supplied to gold fine particles or the like, molten silicide is formed, reaching the solid solubility limit, and crystal silicon is deposited to push up the gold fine particles. A nanowire grows by such a growth mechanism using a three-phase interface of Liquid-Vapor-Solid (LVS).

  Further, the silicon nanowire 108 is doped with As to be n-type, and the silicon nanowire 109 is doped with B to be p-type. Further, the substrate side of the nanowire is highly doped so as to be in ohmic contact.

  Next, as shown in FIG. 20D, a gate insulating film 110 and a conductive film 111 made of a silicide film, a polycide film, or a metal material are deposited on the entire surface. Next, as shown in FIG. 20E, the conductive film 111 is removed by etching to a predetermined height to form the gate electrode 112.

  Next, as shown in FIG. 20F, the gate insulating film 110 deposited on the top surfaces of the silicon nanowires 108 and 109 is selectively removed by anisotropic etching. At this time, the exposed portions of the gate insulating film 110 and the selective growth mask 107 deposited in the peripheral region are also removed.

Next, as shown in FIG. 21G, a resist mask 113 is formed to bury the silicon nanowires 108 and 109 so that the tops are exposed. Next, an HfO ₂ film having a thickness of 2 to ₅ nm, for example, 2 nm, and an Al film having a thickness of 10 to 100 nm, for example, 10 nm are sequentially deposited to form tunnel insulating films 114 and 115, a metal source 116, and a metal drain 117. Are formed on the top surfaces of the silicon nanowires 108 and 109.

  Next, as shown in FIG. 21 (h), for example, Co is deposited on the entire surface by using a highly directional deposition method from above, and then the node electrode 118 is formed by silicidation by heat treatment. Next, unreacted Co is removed, thereby preventing a short circuit between each electrode and the node electrode 118.

  Next, as shown in FIG. 21 (i), after removing the resist mask 113, a film having a high directivity such as a collimated sputtering method, vapor deposition method, or plasma CVD method is used, for example, with a thickness of 30 nm. A silicon oxide film 119 is deposited. Next, the silicon oxide film 119 is isotropically etched in a small amount to remove the thin silicon oxide film attached around the nanowire (the surface of the gate electrode 112). As a result, the surface of the gate electrode 112 is exposed, and separation between the buried insulating film 120 and the silicon oxide film 119 on the upper surface of the nanowire can be ensured.

  Next, as shown in FIG. 22J, a conductive film, for example, an Al film 121 having a thickness of 26 nm is deposited on the entire surface by using a deposition method with high directivity from above. At this time, an Al film 121 separated from the outside of the nanowire and the upper end of the nanowire is formed. Next, the Al film 121 is patterned using photolithography to form the gate electrode wiring 122. The gate electrode wiring 122 is patterned so as to surround the silicon nanowires 108 and 109 and to extend on the STI element isolation region 102 at the right end of the cell.

  Next, as shown in FIG. 22 (k), the silicon oxide film 119 deposited on the upper end of the nanowire is removed by etching, and at the same time, the Al film 121 thereon is lifted off and removed. Next, after depositing an insulating film 123 so as to embed the metal source 116 and the metal drain 117, planarization is performed by CMP polishing to expose the surfaces of the metal source 116 and the metal drain 117.

  Next, as shown in FIG. 22L, after an interlayer insulating film 124 is deposited on the insulating film 123, via holes reaching the node electrode 118, the metal source 116, the metal drain 117, and the gate electrode wiring 122 are formed. After that, the via hole is filled with Al to form the source electrode 125, the drain electrode 126, the node extraction electrode 127, and the gate extraction electrode 128, thereby forming the basics of the vertical tunnel barrier FET inverter according to the eighth embodiment of the present invention. The configuration is complete.

  As described above, in the eighth embodiment of the present invention, since the inverter made of silicon nanowires is vertically formed, the overall configuration becomes three-dimensional, and the degree of integration can be further improved.

  In Example 8, the nanowire is formed of silicon, but is not limited to silicon, and a nanowire made of a compound semiconductor, or a carbon nanotube can also be used. As is well known, these nanowires and nanotubes can be formed using a catalyst in addition to selective growth.

  The embodiments of the present invention have been described above, but the present invention is not limited to the conditions shown in the embodiments, and is applied to, for example, a single p-channel FET. Furthermore, the connection state of the p-channel FET and the n-channel FET is not limited to the inverter connection, and a transmission gate may be configured.

In Example 8 described above, since the general selective growth is used, the node electrode is formed as a silicide electrode straddling the n ⁺ -type drain region and the p ⁺ -type source region. A metal node having a large work function, such as Pt, may be used.

In this case, after providing a silicon substrate or metal node in a predetermined shape, a tunnel insulating film such as HfO ₂ is provided thereon, and then a growth mask as shown in FIG. Silicon nanowires may be formed by repeating the steps of depositing a Si thin film by plating and crystallization by laser annealing.

Here, the following supplementary notes are disclosed with respect to the embodiments of the present invention including Examples 1 to 8.
(Supplementary Note 1) At least one of the first source region and the first drain region is made of the first metal or the first polycrystalline semiconductor, and between the first metal or the first polycrystalline semiconductor and the first semiconductor channel layer. A field effect semiconductor device comprising a formed first tunnel insulating film.
(Appendix 2) At least one of the first source region and the first drain region is made of the first metal or the first polycrystalline semiconductor, and between the first metal or the first polycrystalline semiconductor and the first semiconductor channel layer. And an n-channel field effect transistor having a first tunnel insulating film formed on the substrate, and at least one of the second source region and the second drain region is made of a second metal or a second polycrystalline semiconductor, and the second metal or A field effect semiconductor device comprising a complementary transistor in which a p-channel field effect transistor having a second tunnel insulating film formed between the second polycrystalline semiconductor and a second semiconductor channel layer is connected in series.
(Supplementary Note 3) The two complementary transistors are arranged in a hanging manner so that one gate electrode is connected to the other node, and a separate field effect transistor for access is connected to both gate electrodes to statically connect them. The field effect semiconductor device according to appendix 2, wherein a random access memory is configured.
(Additional remark 4) The field effect type semiconductor device of Additional remark 2 or 3 which provided the said tunnel insulating film only in the source region and drain region which comprise the node of the said complementary transistor.
(Supplementary note 5) The field effect semiconductor device according to supplementary note 1, wherein the first semiconductor channel layer is formed of a first semiconductor nanowire having a width of 100 nm or less.
(Supplementary note 6) The field effect semiconductor device according to supplementary note 5, wherein the first semiconductor nanowire is a cylindrical nanowire.
(Supplementary Note 7) Both the first source region and the first drain region are made of the first metal or the first polycrystalline semiconductor, and the first metal or the first polycrystalline semiconductor and the first semiconductor channel layer. Item 3. The field effect semiconductor device according to Item 1 or 2, wherein a height of a tunnel barrier with respect to electrons of the first tunnel insulating film formed between is 0.3 eV to 3.0 eV.
(Supplementary Note 8) Both the second source region and the second drain region are made of the second metal or the second polycrystalline semiconductor, and the second metal or the second polycrystalline semiconductor and the second semiconductor channel layer. 3. The field effect semiconductor device according to appendix 2, wherein a height of a tunnel barrier with respect to holes of the second tunnel insulating film formed between the first and second tunnel insulating films is 0.3 eV to 3.0 eV.
(Supplementary note 9) The field effect semiconductor device according to supplementary note 7, wherein the first metal constituting the source region and the first metal constituting the drain region are made of metals having different work functions.
(Supplementary note 10) The insulated gate field effect according to supplementary note 7, wherein the first tunnel insulating film provided on the first source region side and the first tunnel insulating film provided on the first drain region side are made of different insulating films. Type semiconductor device.

It is an energy band diagram of the tunnel barrier field effect type semiconductor device of the present invention. It is a typical energy band diagram of the tunnel barrier vicinity. It is an energy band diagram of the tunnel barrier field effect type semiconductor device of the modification of this invention. It is explanatory drawing of the work function dependence of the tunnel insulating film of a tunnel current-electric field characteristic. It is explanatory drawing of the band gap of the various insulators currently reported. It is explanatory drawing of the barrier barrier with respect to the valence band and conduction band of various insulating films with respect to Si and Ge. It is explanatory drawing of VB offset in the interface of various metals and Si. It is explanatory drawing of the manufacturing process to the middle of the tunnel barrier FET of Example 1 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 8 after the tunnel barrier FET of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 9 of tunnel barrier FET of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle of the tunnel barrier FET of Example 2 of this invention. FIG. 12 is an explanatory diagram of the manufacturing process of FIG. 11 and subsequent drawings of the tunnel barrier FET of Example 2 of the present invention. It is explanatory drawing of the manufacturing process to the middle of the tunnel barrier FET of Example 3 of this invention. It is explanatory drawing of the manufacturing process after FIG. 13 of the tunnel barrier FET of Example 3 of this invention. It is explanatory drawing of the tunnel barrier FET inverter of Example 4 of this invention. It is explanatory drawing of the tunnel barrier FET inverter of Example 5 of this invention. It is explanatory drawing of the tunnel barrier FET inverter of Example 6 of this invention. It is a top view of SRAM which used the tunnel barrier FET of Example 7 of this invention. It is explanatory drawing of the manufacturing process to the middle of the vertical tunnel barrier FET of Example 8 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 19 of the vertical tunnel barrier FET of Example 8 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 20 or subsequent of the vertical tunnel barrier FET of Example 8 of this invention. It is explanatory drawing of the manufacturing process after FIG. 21 of vertical tunnel barrier FET of Example 8 of this invention. It is an energy band diagram of a conventional MOSFET. It is an energy band diagram of a tunnel barrier FET.

Explanation of symbols

11 Silicon substrate 12 STI element isolation region 13 P-type well region 14 Gate insulating film 15 Gate electrode 16 Side walls 17, 19, 22, 38 Resist patterns 18, 32 Recesses 20, 23, 33, 40 Tunnel insulating films 21, 36, 43 Metal source 24, 37, 44 Metal drain 25 Insulating film 26 to 28 Contact hole 29 Source electrode 30 Drain electrode 31 Gate extraction electrode 34, 41 Al film 35, 42 Pt film 39 Tunnel insulating film 51 Silicon substrate 52 Insulating film 53 STI Element isolation region 54 n-type field region 55 p-type field region 56 Gate insulating film 57, 58 Gate electrode 59, 60 Side wall 61, 63, 65 Tunnel insulating film 62 Metal source 64 Metal node 66 Metal drain 67 Insulating film 68 Source electrode 69 Drain electricity Electrode 70, 71 Gate extraction electrode 72 Output electrode 73, 74 Electrode 81 Silicon substrate 82 Insulating film 83, 84 Silicon region 85 Gate insulating film 86 Gate electrode 87 Tunnel insulating film 88 Metal node 89 Metal source 90 Metal drain 91 Source electrode 92 Drain Electrode 93 Gate extraction electrode 94 Output electrodes 95, 96 FET
97, 98 Local wiring layer 101 n-type silicon substrate 102 STI element isolation region 103 n ⁺ -type drain region 104 p ⁺ -type source region 105, 106 opening 107 selective growth mask 108, 109 silicon nanowire 110 gate insulating film 111 conductive film 112 Gate electrode 113 Resist mask 114, 115 Tunnel insulating film 116 Metal source 117 Metal drain 118 Node electrode 119 Silicon oxide film 120 Embedded insulating film 121 Al film 122 Gate electrode wiring 123 Insulating film 124 Interlayer insulating film 125 Source electrode 126 Drain electrode 127 Node Extraction electrode 128 Gate extraction electrode

Claims (7)

At least one of the first source region and the first drain region is made of a first metal or a first polycrystalline semiconductor, and is formed between the first metal or the first polycrystalline semiconductor and the first semiconductor channel layer. A field-effect semiconductor device having one tunnel insulating film. At least one of the first source region and the first drain region is made of the first metal or the first polycrystalline semiconductor, and is formed between the first metal or the first polycrystalline semiconductor and the first semiconductor channel layer. An n-channel field effect transistor having a first tunnel insulating film, and at least one of the second source region and the second drain region is made of a second metal or a second polycrystalline semiconductor, and the second metal or the second A field effect semiconductor device comprising a complementary transistor in which a p-channel field effect transistor having a second tunnel insulating film formed between a crystalline semiconductor and a second semiconductor channel layer is connected in series. 2. The field effect semiconductor device according to claim 1, wherein the first semiconductor channel layer is formed of a first semiconductor nanowire having a width of 100 nm or less. Both the first source region and the first drain region are made of the first metal or the first polycrystalline semiconductor, and between the first metal or the first polycrystalline semiconductor and the first semiconductor channel layer. 3. The field effect semiconductor device according to claim 1, wherein a height of a tunnel barrier with respect to electrons of the formed first tunnel insulating film is 0.3 eV to 3.0 eV. Both the second source region and the second drain region are made of the second metal or the second polycrystalline semiconductor, and between the second metal or the second polycrystalline semiconductor and the second semiconductor channel layer. The field effect semiconductor device according to claim 2, wherein a height of a tunnel barrier with respect to holes of the formed second tunnel insulating film is 0.3 eV to 3.0 eV. 5. The field effect semiconductor device according to claim 4, wherein the first metal constituting the source region and the first metal constituting the drain region are made of metals having different work functions. 5. The insulated gate field effect semiconductor device according to claim 4, wherein the first tunnel insulating film provided on the first source region side and the first tunnel insulating film provided on the first drain region side comprise different insulating films. .

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