JP2005079413A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a highly reliable semiconductor device manufacturing method without damaging a diffusion layer in connection with resist film removal. <P>SOLUTION: A plurality of gate electrodes 2 are formed on a semiconductor substrate 1, an impurity is injected with the gate electrodes 2 as a mask to form an N<SP>-</SP>diffusion layer 5, a third resist film 11 is formed to partially cover the semiconductor substrate 1 except the middle portion of the N<SP>-</SP>diffusion layer 5, and an N<SP>+</SP>diffusion layer 12 with a higher concentration than that of the N<SP>-</SP>diffusion layer 5 is formed in the middle portion of the N<SP>-</SP>diffusion layer 5 with the third resist film 11 as a mask. When forming an offset region C wherein no gate electrode 2 is present in the upper portion but only the N<SP>-</SP>diffusion layer 5 is present, after the formation of the N<SP>-</SP>diffusion layer 5 and before the formation of the third resist film 11, a second protecting film 10 composed of a thin film and having properties different from those of the third resist film 11 is formed on the semiconductor substrate 1, and impurity injection is performed via the second protecting film 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  According to the present invention, in a method of manufacturing a semiconductor device having a medium and high breakdown voltage transistor, deterioration of transistor characteristics, particularly Ids value, due to hot electrons is minimized, and reliability is improved.

  In a conventional method for manufacturing a semiconductor device, a gate insulating film is formed on a first conductive semiconductor layer, a gate electrode is formed on the gate insulating film, and a second conductive impurity is formed perpendicular to the semiconductor substrate using the gate electrode as a mask. Is implanted to form a low-concentration second conductivity type impurity region, and the second conductivity type impurity is ion-implanted from an angle perpendicular to the gate width direction of the gate electrode and with respect to the surface of the semiconductor substrate. A concentration second conductivity type impurity region is formed (see, for example, Patent Document 1).

JP-A-6-45349

Although the conventional semiconductor device is configured as described above, an offset region is required when forming a semiconductor device for medium and high withstand voltage. In that case, after forming the gate electrode, an N ⁻ diffusion layer and a P ⁻ diffusion layer are formed on the surface of the silicon active region by photolithography and ion implantation. Next, the insulating film is deposited on the entire surface, and sidewalls are formed by etch back on the entire surface. Next, an N ⁺ diffusion layer and a P ⁺ diffusion layer are formed by photolithography and ion implantation. In the above steps, the resist film used for photolithography at the time of forming the diffusion layer is subjected to an ashing process to be removed after ion implantation.

The problem to be solved is that the offset region is damaged by the ashing process used when removing the resist film, the crystallinity of silicon is broken, dangling bonds are generated, and impurity levels are generated at the silicon interface. Happens. For this reason, when the transistor operation is performed, the generated hot carriers are trapped on the N ⁻ diffusion layer or P ⁻ diffusion layer (the surface of the silicon active region) serving as the offset region. Carrier traps lead to a decrease in drain current and decrease the driving performance of the transistor. Furthermore, there has been a problem that reliability deteriorates.

  The present invention has been made to solve the above-described problems, and reduces damage (etching damage) on the surface of the silicon active region or eliminates damage (etching damage) on the surface of the silicon active region. An object of the present invention is to obtain a method for manufacturing a semiconductor device with excellent reliability for reducing impurity levels.

  A method for manufacturing a semiconductor device according to the present invention includes forming a plurality of gate electrodes on a semiconductor substrate, implanting impurities into the semiconductor substrate using the gate electrodes as a mask to form a diffusion layer, and forming a diffusion layer on a central portion of the diffusion layer of the semiconductor substrate. A resist film is formed so as to cover the portion excluding, and the resist film is used as a mask to implant impurities into the central portion of the diffusion layer so that the impurity concentration is higher than that of the diffusion layer, thereby forming a high concentration diffusion layer and forming a gate on the top. In a manufacturing method of a semiconductor device that forms an offset region in which only a diffusion layer exists without an electrode, a thin film is formed on a semiconductor substrate after the diffusion layer is formed and before the resist film is formed. Forms protective films having different characteristics, and impurities are implanted through the protective film.

  A method for manufacturing a semiconductor device according to the present invention includes forming a plurality of gate electrodes on a semiconductor substrate, implanting impurities into the semiconductor substrate using the gate electrodes as a mask to form a diffusion layer, and forming a diffusion layer on a central portion of the diffusion layer of the semiconductor substrate. A resist film is formed so as to cover the portion excluding, and the resist film is used as a mask to implant impurities into the central portion of the diffusion layer so that the impurity concentration is higher than that of the diffusion layer, thereby forming a high concentration diffusion layer and forming a gate on the top. In a manufacturing method of a semiconductor device that forms an offset region in which only a diffusion layer exists without an electrode, a thin film is formed on a semiconductor substrate after the diffusion layer is formed and before the resist film is formed. Forms a protective film with different characteristics, and impurities are implanted through the protective film, so that the protective film remains on the diffusion layer when the resist film is removed. In which it is possible to obtain a method of manufacturing a semiconductor device having excellent reliability because there is not caused over di.

Embodiment 1 FIG.
1 to 3 are cross-sectional views showing a method of manufacturing a semiconductor device having a medium and high breakdown voltage transistor according to Embodiment 1 of the present invention. A method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. First, a semiconductor substrate having a first region A in which, for example, a P-type impurity is implanted as a first conductivity type, and a second region B in which, for example, an N-type impurity is implanted as a second conductivity type. A plurality of gate electrodes 2 made of, for example, a gate insulating film and a doped polysilicon film are formed on the first and second regions A and B on the substrate 1 (FIG. 1A). Next, a first protective film 3 made of an oxide film having a thickness of about 10 nm is stacked on the semiconductor substrate 1 by, eg, CVD (FIG. 1B). The first protective film 3 formed at this time may be a film having characteristics different from those of the first and second resist films formed later. Further, the film thickness of the first protective film 3 may be appropriately set within a range in which impurity implantation performed later can be performed.

Next, the first resist film 4 is formed so as to cover the second region B. Next, using the first resist film 4 and the gate electrode 2 as a mask, a second conductivity type (N-type) impurity is implanted into the semiconductor substrate 1 in the first region A to form N ⁻ as a second conductivity type diffusion layer. A diffusion layer 5 is formed (FIG. 1C). Next, the first resist film 4 is removed by, for example, an ashing process. At this time, since the N ⁻ diffusion layer 5 is covered with the first protective film 3, the N ⁻ diffusion layer 5 is not directly damaged. Next, a second resist film 6 is formed so as to cover the first region A. Next, using the second resist film 6 and the gate electrode 2 as a mask, a first conductivity type (P-type) impurity is implanted into the semiconductor substrate 1 in the second region B to form P ⁻ as a first conductivity type diffusion layer. A diffusion layer 7 is formed (FIG. 1D). Next, the second resist film 6 is removed by, for example, an ashing process. At this time, since the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are covered with the first protective film 3, the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are directly damaged. There is no.

  Next, for example, an oxide film 8 is laminated on the entire surface of the semiconductor substrate 1 (FIG. 2A). Next, etch back is performed, and the first protective film 3 and the oxide film 8 are formed on the side walls of the gate electrodes 2. Is formed (FIG. 2B). At this time, the first protective film 3 on the diffusion layers 5 and 7 is removed. Next, a second protective film 10 made of an oxide film having a thickness of about 10 nm is stacked on the semiconductor substrate 1 by, eg, CVD (FIG. 2C). The second protective film 10 formed at this time may be a film having different characteristics from the first and second resist films to be formed later. In addition, the thickness of the second protective film 10 may be appropriately set within a range in which impurity implantation performed later can be performed.

Next, a third resist film 11 is formed so as to cover the second region B of the semiconductor substrate 1 and the portion of the first region A except for the central portion of the N ⁻ diffusion layer 5. Then, N the third resist film 11 as a mask ^- impurity implantation of impurity concentration than the diffusion layer 5 higher concentrations become as second conductivity type (N-type) ^- N in the center of the diffusion layer 5 An N ⁺ diffusion layer 12 is formed as a second conductivity type high concentration diffusion layer. Then, an offset region C in which the gate electrode 2 and the side wall 9 do not exist and only the N ⁻ diffusion layer 5 exists is formed (FIG. 2D). Next, the third resist film 11 is removed by, for example, an ashing process. At this time, since the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are covered with the second protective film 10, the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are directly damaged. There is no.

Next, a fourth resist film 13 is formed so as to cover portions of the first region A and the second region B of the semiconductor substrate 2 except for the central portion of the P ⁻ diffusion layer 7. Then, P a fourth resist film 13 as a mask ^- P in the central portion of the diffusion layer 7 ^- impurity concentration than the diffusion layer 7 is implanting an impurity of a high concentration so as to first conductivity type (P-type) A P ⁺ diffusion layer 14 as a first conductivity type high-concentration diffusion layer is formed, and an offset region C in which only the P ⁻ diffusion layer 7 exists without the gate electrode 2 and the side wall 9 is formed (FIG. 3). (A)). Next, the fourth resist film 13 is removed by, for example, an ashing process (FIG. 3B). At this time, since the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are covered with the second protective film 10, the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are directly damaged. There is no.

  In the manufacturing method of the semiconductor device according to the first embodiment configured as described above, each resist film is covered with each protective film when removing each resist film. When the film is removed, the crystallinity of silicon is broken and the generation of dangling bonds can be reduced, and the generation of impurity levels at the silicon interface can be reduced. For this reason, when the transistor is operated, the generated hot carriers are reduced from trapping carriers in the offset region, so that the drain current can be prevented from being lowered, and the transistor driving performance is not deteriorated. A semiconductor device having excellent properties can be obtained.

  In the first embodiment, an example in which the first and second protective films are formed of oxide films formed by the CVD method has been described. However, the present invention is not limited to this, and for example, 800 to 900 under reduced pressure. An example in which a thermal oxide film is formed by a thermal oxidation method using heat treatment at a temperature not higher than ° C. is also conceivable. In that case, the impurity level generated in the semiconductor substrate by the thermal energy at the time of formation can be reduced. Therefore, a semiconductor device with even higher reliability can be obtained. Further, if the semiconductor substrate is cleaned by wet processing immediately before the thermal oxide film is formed, the effect of reducing the impurity level is further improved. In the following embodiments, the protective film can be formed of a thermal oxide film, and the description thereof will be omitted as appropriate in order to achieve the same effect.

Embodiment 2. FIG.
4 is a cross-sectional view showing a method of manufacturing a semiconductor device having a medium and high breakdown voltage transistor according to the second embodiment of the present invention. A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings. First, similarly to the first embodiment, the first region A into which, for example, a P-type impurity as a first conductivity type is implanted, and the first region into which, for example, an N-type impurity, as a second conductivity type, is implanted. A plurality of gate electrodes 2 made of, for example, a gate insulating film and a doped polysilicon film are formed on the first and second regions A and B on the semiconductor substrate 1 having two regions B, respectively. Next, a first protective film 3 made of an oxide film having a thickness of about 10 nm is stacked on the semiconductor substrate 1 by, eg, CVD. The first protective film 3 formed at this time may be a film having characteristics different from those of the first and second resist films formed later. Further, the film thickness of the first protective film 3 may be appropriately set within a range in which impurity implantation performed later can be performed.

Next, the first resist film 4 is formed so as to cover the second region B. Next, using the first resist film 4 and the gate electrode 2 as a mask, a second conductivity type (N-type) impurity is implanted into the semiconductor substrate 1 in the first region A to form N ⁻ as a second conductivity type diffusion layer. The diffusion layer 5 is formed. Next, the first resist film 4 is removed by, for example, an ashing process. At this time, since the N ⁻ diffusion layer 5 is covered with the first protective film 3, the N ⁻ diffusion layer 5 is not directly damaged. Next, a second resist film 6 is formed so as to cover the first region A. Next, using the second resist film 6 and the gate electrode 2 as a mask, a first conductivity type (P-type) impurity is implanted into the semiconductor substrate 1 in the second region B to form P ⁻ as a first conductivity type diffusion layer. A diffusion layer 7 is formed. Next, the second resist film 6 is removed by, for example, an ashing process. At this time, since the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are covered with the first protective film 3, the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are directly damaged. There is no.

Next, for example, an oxide film 8 is laminated on the entire surface of the semiconductor substrate 1. Next, etch back is performed to form a side wall 9 made of the first protective film 3 and the oxide film 8 on the side wall of each gate electrode 2. At this time, the oxide film 3 is not etched up to the top of the semiconductor substrate 1 but is etched so as to remain at a desired thickness, that is, about 10 nm, for example, in a range where impurity implantation can be performed later. Then, the remaining protective film 3a on the diffusion layers 5 and 7 remains without being removed. Therefore, in forming the sidewalls 9, since the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are covered with the remaining protective film 3 a, the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are directly connected to each other. No damage is caused (FIG. 4 (a)). Next, a third resist film 11 is formed so as to cover the second region B of the semiconductor substrate 1 and the portion of the first region A except for the central portion of the N ⁻ diffusion layer 5.

Then, N the third resist film 11 as a mask ^- impurity implantation of impurity concentration than the diffusion layer 5 higher concentrations become as second conductivity type (N-type) ^- N in the center of the diffusion layer 5 An N ⁺ diffusion layer 12 is formed as a second conductivity type high concentration diffusion layer. Then, an offset region C in which the gate electrode 2 and the side wall 9 do not exist and only the N ⁻ diffusion layer 5 exists is formed (FIG. 2D). Next, the third resist film 11 is removed by, for example, an ashing process. At this time, P ^- because it is covered with the diffusion layer 5 on the remaining protective film 3a, P ^{- -} upper diffusion layer 7 and the N diffusion layer 7 above and N ^- diffusion layer 5 above does not occur directly damage .

Next, a fourth resist film 13 is formed so as to cover portions of the first region A and the second region B of the semiconductor substrate 2 except for the central portion of the P ⁻ diffusion layer 7. Then, P a fourth resist film 13 as a mask ^- P in the central portion of the diffusion layer 7 ^- impurity concentration than the diffusion layer 7 is implanting an impurity of a high concentration so as to first conductivity type (P-type) A P ⁺ diffusion layer 14 as a first conductivity type high-concentration diffusion layer is formed, and an offset region C in which only the P ⁻ diffusion layer 7 exists without the gate electrode 2 and the side wall 9 is formed (FIG. 3). (A)). Next, the fourth resist film 13 is removed by, for example, an ashing process (FIG. 3B). At this time, P ^- because it is covered with the diffusion layer 5 on the remaining protective film 3a, P ^{- -} upper diffusion layer 7 and the N diffusion layer 7 above and N ^- diffusion layer 5 above does not occur directly damage .

  The manufacturing method of the semiconductor device according to the second embodiment configured as described above has an effect that a semiconductor device having excellent reliability can be obtained as in the first embodiment. Since the etching damage in the formation of the wall can also be reduced, a semiconductor device with higher reliability can be obtained. Furthermore, it can be performed only by forming the protective film once, and the increase in the number of steps can be minimized.

Embodiment 3 FIG.
5 and 6 are cross-sectional views showing a method of manufacturing a semiconductor device provided with a medium and high breakdown voltage transistor according to the third embodiment of the present invention. A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to the drawings. First, as in each of the above embodiments, the first region A in which, for example, a P-type impurity as a first conductivity type is implanted, and the first region in which, for example, an N-type impurity as a second conductivity type is implanted. A plurality of gate electrodes 2 made of, for example, a gate insulating film and a doped polysilicon film are formed on the first and second regions A and B on the semiconductor substrate 1 having two regions B, respectively. Next, a first protective film 30 made of a nitride film having a thickness of about 10 nm is stacked on the semiconductor substrate 1 by, eg, CVD (FIG. 5A). The first protective film 30 formed at this time may be a film having different characteristics from the first and second resist films to be formed later. Further, the thickness of the first protective film 30 may be set as appropriate within a range in which impurity implantation performed later can be performed. Further, here, a film having characteristics different from those of the film for forming the sidewall is formed.

Next, the first resist film 4 is formed so as to cover the second region B. Next, using the first resist film 4 and the gate electrode 2 as a mask, a second conductivity type (N-type) impurity is implanted into the semiconductor substrate 1 in the first region A to form N ⁻ as a second conductivity type diffusion layer. A diffusion layer 5 is formed (FIG. 5B). Next, the first resist film 4 is removed by, for example, an ashing process. At this time, since the N ⁻ diffusion layer 5 is covered with the first protective film 30, the N ⁻ diffusion layer 5 is not directly damaged. Next, a second resist film 6 is formed so as to cover the first region A. Next, using the second resist film 6 and the gate electrode 2 as a mask, a first conductivity type (P-type) impurity is implanted into the semiconductor substrate 1 in the second region B to form P ⁻ as a first conductivity type diffusion layer. A diffusion layer 7 is formed (FIG. 5C). Next, the second resist film 6 is removed by, for example, an ashing process. At this time, since the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are covered with the first protective film 30, the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are directly damaged. There is no.

Next, for example, an oxide film 8 is laminated on the entire surface of the semiconductor substrate 1 (FIG. 5D). Next, etch back is performed, and the first protective film 30 and the oxide film 8 are formed on the side walls of the gate electrodes 2. A side wall 90 is formed. At the same time, since the first protective film 30 is formed of a nitride film having different characteristics from the oxide film 8, it also functions as an etching stopper in etch back and remains on the semiconductor substrate 1 after the sidewall 90 is formed. Will be. Therefore, in forming the sidewalls 90, the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are covered with the first protective film 30, and thus the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are formed. Does not cause direct damage (FIG. 6A).

Next, a third resist film 11 is formed so as to cover the second region B of the semiconductor substrate 1 and the portion of the first region A except for the central portion of the N ⁻ diffusion layer 5. Then, N the third resist film 11 as a mask ^- impurity implantation of impurity concentration than the diffusion layer 5 higher concentrations become as second conductivity type (N-type) ^- N in the center of the diffusion layer 5 An N ⁺ diffusion layer 12 is formed as a second conductivity type high concentration diffusion layer. Then, an offset region C in which the gate electrode 2 does not exist on the upper side and only the N ⁻ diffusion layer 5 exists is formed (FIG. 6B). Next, the third resist film 11 is removed by, for example, an ashing process. At this time, since the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are covered with the first protective film 30, the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are directly damaged. There is no.

Next, a fourth resist film 13 is formed so as to cover portions of the first region A and the second region B of the semiconductor substrate 2 except for the central portion of the P ⁻ diffusion layer 7. Then, P a fourth resist film 13 as a mask ^- P in the central portion of the diffusion layer 7 ^- impurity concentration than the diffusion layer 7 is implanting an impurity of a high concentration so as to first conductivity type (P-type) A P ⁺ diffusion layer 14 as a first conductivity type high concentration diffusion layer is formed, and an offset region C in which only the P ⁻ diffusion layer 7 exists without the gate electrode 2 being formed is formed (FIG. 6C). . Next, the fourth resist film 13 is removed by, for example, ashing (FIG. 6D). At this time, since the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are covered with the first protective film 30, the P ⁻ diffusion layer 7 and the N ⁻ diffusion layer 5 are directly damaged. There is no.

  The manufacturing method of the semiconductor device according to the third embodiment configured as described above has an effect that a semiconductor device having excellent reliability can be obtained as in the second embodiment. It can be performed only by forming the protective film at a certain degree, and the increase in the number of steps can be minimized, and further, it functions as an etching stopper when forming the sidewall.

  In the third embodiment, an example in which the first protective film is formed of a nitride film has been described. However, the present invention is not limited to this, and the first protective film may be a thermal oxide film or a nitride film, for example. A case of a laminated film is also conceivable. In this case, both the effect on the thermal oxide film and the effect on the nitride film can be obtained.

  In each of the above embodiments, an example in which the first region and the second region exist has been described. However, the present invention is not limited to this, and one of the regions exists and an offset region is formed. If a protective film is formed and a resist film is formed and impurities are implanted before the high concentration diffusion layer is formed, the offset region can be protected against the removal of the resist film at this time. Therefore, it goes without saying that a highly reliable semiconductor device can be obtained.

It is sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Gate electrode, 3,30 1st protective film, 3a Remaining protective film,
4 first resist film, 5 N ^- diffusion layer, 6 a second resist film, 7 P ^- diffusion layers,
9, 90 sidewalls, 10 second protective film, 11 third resist film,
12 N ⁺ diffusion layer, 13 fourth resist film, 14 P ⁺ diffusion layer, A first region,
B second region, C offset region.

Claims (6)

Excluding a step of forming a plurality of gate electrodes on a semiconductor substrate, a step of implanting impurities into the semiconductor substrate using the gate electrodes as a mask to form a diffusion layer, and a portion above the central portion of the diffusion layer of the semiconductor substrate Forming a resist film so as to cover the portion, and using the resist film as a mask, an impurity is implanted into a central portion of the diffusion layer so that the impurity concentration is higher than that of the diffusion layer to form a high concentration diffusion layer. And a step of forming an offset region in which only the diffusion layer is present without the gate electrode formed thereon, and after forming the diffusion layer and before forming the resist film. Forming a protective film made of a thin film on the semiconductor substrate and having different characteristics from the resist film, and implanting the impurities through the protective film Method of manufacturing location. A plurality of first and second regions on the semiconductor substrate having a first region implanted with an impurity of the first conductivity type and a second region implanted with an impurity of the second conductivity type. A step of forming a gate electrode; a step of forming a first resist film so as to cover the second region of the semiconductor substrate; and the first resist film and the gate electrode as a mask. Implanting the second conductivity type impurity into the semiconductor substrate in the region to form a second conductivity type diffusion layer; removing the first resist film; and the first region of the semiconductor substrate. Forming a second resist film so as to cover, and implanting the first conductivity type impurity into the semiconductor substrate in the second region using the second resist film and the gate electrode as a mask. 1 Conduction type diffusion layer is formed And a step of removing the second resist film, and a third resist film so as to cover a portion of the second region and the first region except for the portion above the central portion of the second conductivity type diffusion layer. And a step of forming the second conductivity type so that the impurity concentration is higher than that of the second conductivity type diffusion layer at the center of the second conductivity type diffusion layer using the third resist film as a mask. Implanting impurities to form a second conductivity type high-concentration diffusion layer, forming an offset region in which only the second conductivity type diffusion layer is present without the gate electrode, and the third resist film; A step of removing, a step of forming a fourth resist film so as to cover a portion of the first region and the second region other than the central portion of the first conductivity type diffusion layer, and the fourth region Using the resist film as a mask, the central portion of the first conductivity type diffusion layer Impurities of the first conductivity type are implanted so that the impurity concentration is higher than that of the first conductivity type diffusion layer to form a first conductivity type high concentration diffusion layer, and the gate electrode does not exist above the first conductivity type diffusion layer. In a method of manufacturing a semiconductor device comprising a step of forming an offset region in which only one conductivity type diffusion layer is present and a step of removing the fourth resist film, the first electrode is formed after the gate electrode is formed. Before forming the first resist film and the second resist film, a protective film made of a thin film and having different characteristics from the first and second resist films is formed on the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the impurity implantation in forming the diffusion layer and the second conductivity type diffusion layer is performed through the protective film. After forming the first conductivity type diffusion layer and the second conductivity type diffusion layer, before forming the third resist film and the fourth resist film, sidewalls are formed on the side walls of the gate electrodes. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of forming the offset region, wherein the offset region is a region where the sidewall does not exist on the upper portion. 4. The semiconductor device according to claim 2, wherein impurities are implanted through the protective film in forming the first conductivity type high concentration diffusion layer and the second conductivity type high concentration diffusion layer. 5. Production method. When the protective film on the semiconductor substrate is removed during the formation of the sidewall, after the sidewall is formed, before the third resist film and the fourth resist film are formed, the protective film is formed on the semiconductor substrate. A second protective film made of a thin film and having different characteristics from the third and fourth resist films is formed, and impurities are implanted in the formation of the first conductivity type high concentration diffusion layer and the second conductivity type high concentration diffusion layer. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step is performed through the second protective film. 7. The protective film according to claim 1, wherein the protective film comprises an oxide film, a thermal oxide film, a nitride film, or a laminated film of a thermal oxide film and a nitride film. Semiconductor device manufacturing method.

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