JP2007005691A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a long hot carrier lifetime by which a gate drain current is reduced. <P>SOLUTION: A sidewall formed at a side wall of a gate electrode is made to include a stopper layer which is constituted by a material having an etching selectivity to a gate insulating film. At the time of forming the sidewall, the sidewall can be formed without eliminating any gate insulating film, and consequently a plasma damage to the gate insulating film can be prevented. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to improvement of the hot carrier lifetime.

Along with the high integration of semiconductor devices such as MOS LSIs, semiconductor devices such as MOSFETs are being miniaturized. Also in MOSFETs, the gate insulating film is becoming thinner, and there is a problem that the electric field between the gate and the drain becomes large and tunneling is likely to occur. In MOSFET operation, the electric field from the drain to the source along the channel is not uniform and is maximum at the drain end. Particularly in the case of the saturation region operation, since the channel does not reach the drain diffusion layer, a depleted region, that is, a pinch-off region is formed on the drain side. Since most of the source / drain voltage is supported by this narrow region, the electric field is very high. When the electric field is 10 ⁵ V / cm or more, an impact ionization phenomenon is observed.

Electrons injected into the channel region are accelerated by a high electric field in the pinch-off region near the channel electric field and the drain, and obtain kinetic energy sufficient to cause impact ionization to generate electron / hole pairs. Most of the generated electrons are absorbed by the drain and become a drain current, but some of the hot electrons (electrons with high energy: hot electrons) enter the gate insulating film as gate current (I _G ). Observed. Almost all of the generated holes are absorbed by the silicon substrate and become a substrate current.

  As described above, in the MOSFET operating in the saturation region, hot carriers are generated by the impact ionization phenomenon, causing various reliability problems. For example, since some of the electrons injected into the gate insulating film are trapped by traps in the gate insulating film, the threshold voltage and mutual conductance of the MOSFET are changed, and various electrical characteristics are changed in the MOS LSI. Become. In a floating gate type MOS memory or the like in which the gate electrode is not connected to the outside, injected electrons are accumulated in the gate electrode, and so-called soft write failure is caused. It has also been reported that a small part of holes are injected into the gate insulating film and cause various deterioration.

  Thus, with the miniaturization of MOS devices, the hot carrier life has become a serious problem. Therefore, an LDD structure in which a low-concentration impurity diffusion region is formed in the source / drain region has been proposed in order to reduce the electric field between the gate and the drain and suppress the leakage current from the gate to the drain (Patent Document 1).

In this method, for example, as shown in FIGS. 6A to 6D, the gate electrode is formed, and after the gate electrode is used as a mask, low concentration ion implantation is performed to form a low concentration diffusion region. A method is used in which a side wall is formed on the side wall of the gate electrode, and ion implantation for forming a source / drain region is performed using the gate electrode formed with the side wall as a mask.
In this method, a gate insulating film 2 made of a silicon oxide film is formed on the surface of the silicon substrate 1 by a thermal oxidation method, and a gate electrode 3 made of a polycrystalline silicon film is formed thereon (FIG. 6A). .
Then, surface oxidation is performed to form a silicon oxide film 4 on the entire surface including the gate electrode 3.
Thereafter, low concentration ion implantation is performed using the gate electrode 3 as a mask to form low concentration diffusion regions 5L and 6L (FIG. 6B).
Then, a silicon oxide film 7 is formed by the CVD method (FIG. 6C), the sidewall is left by anisotropic etching, a sidewall made of the silicon oxide film is formed, and ion implantation is performed using this sidewall as a mask. The source and drain regions 5 and 6 are formed by annealing, and the MOSFET shown in FIG. 1 is obtained (FIG. 6D).

Japanese Patent Laid-Open No. 11-163317

  As described above, in the conventional MOSFET, when the LDD structure is formed, post oxidation is performed after forming the gate electrode, ion implantation is performed using the gate electrode as a mask, a low concentration impurity region is formed, and then a silicon oxide film is formed. A method is employed in which the film is left on the side wall of the gate electrode by anisotropic etching to form a side wall, and ion implantation for forming a source / drain region is performed using this as a mask.

  However, the gate insulating film is etched in the etching process for forming the sidewall. For this reason, the surface of the silicon substrate is exposed and may cause roughness.

  In addition, since etching is performed up to the gate insulating film, in plasma etching that is usually used as anisotropic etching, charging damage is caused by plasma from the end portion, that is, the end surface of the gate insulating film exposed under the edge of the gate electrode, There was a problem that hot carrier resistance deteriorated.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a long hot carrier life by reducing a gate drain current.

  Accordingly, a method of the present invention is a method of manufacturing a semiconductor device in which an LDD structure MOS device is formed on the surface of a semiconductor substrate, the step of forming a gate electrode on the surface of the semiconductor substrate via a gate insulating film, A step of oxidizing the surface to form a post oxide film, a step of performing low concentration impurity diffusion using the gate electrode as a mask to form a low concentration diffusion region, and a gate insulating film on the post oxide film. Forming a sidewall including a stopper layer made of a material having etching selectivity, and performing impurity diffusion using the gate electrode and the sidewall as a mask, thereby providing a source / drain having a higher concentration than the low concentration diffusion region. Forming a region.

  With this configuration, since the sidewall including the stopper layer made of a material having etching selectivity with respect to the gate insulating film is formed, the gate insulating film remains around the gate electrode, and the gate Since the gate insulating film can be formed at the edge of the electrode without etching, not only damage to the substrate but also damage to the substrate to the gate insulating film, resulting in deterioration of characteristics such as increased transistor leakage current Therefore, it is possible to provide a semiconductor device that can be formed and has high hot carrier resistance.

  Further, the method of the present invention includes the above method, wherein the step of forming the sidewall includes a step of forming a silicon nitride film.

  With this configuration, patterning can be performed under conditions having etching selectivity with respect to silicon oxide of the gate insulating film, and reliability can be improved.

  In addition, the method of the present invention includes the above method, wherein the step of forming the sidewall includes a step of forming a conductive film through a post oxide film covering the periphery of the gate electrode.

  With this configuration, patterning can be performed under conditions having etching selectivity with respect to silicon oxide of the gate insulating film, and reliability can be improved.

  Moreover, the method of the present invention includes the above method, wherein the conductive film is a silicon-based conductive film.

  In addition, the method of the present invention includes the above method, wherein the conductive film is a polycrystalline silicon film.

  In addition, the method of the present invention includes the above method, wherein the conductive film is an amorphous silicon film.

  With this configuration, it can be formed at the same time as a wiring formation process in another region of the integrated circuit, and a desired LDD structure can be formed while suppressing an increase in man-hours.

  Further, the method of the present invention includes the above method, wherein the conductive film is a metal film.

  With this configuration, as in the case of a silicon-based conductive film such as a polycrystalline silicon film, it can be formed at the same time as a wiring forming process in other regions of the integrated circuit, and a desired LDD while suppressing an increase in man-hours. A structure can be formed.

  Further, the method of the present invention includes the above method, wherein the side wall forming step includes a step of forming the stopper layer and a step of forming a silicon oxide film on the stopper layer.

  With this configuration, by using a stopper layer such as a silicon nitride film or a polycrystalline silicon film, a commonly used silicon oxide film can be used for the sidewall, and a highly reliable semiconductor device can be obtained without greatly changing the process. It becomes possible to form.

  Further, the method of the present invention includes the above method, wherein the gate electrode is a gate electrode of a MOSFET.

  With this configuration, it is possible to form a MOSFET with a long hot carrier resistance life and high reliability even when miniaturized.

  In the present invention, the sidewall formed on the sidewall of the gate electrode includes a stopper layer made of a material having etching selectivity with respect to the gate insulating film.

  With this configuration, the sidewall can be formed without removing the gate insulating film, and plasma damage to the gate insulating film can be prevented.

  Further, the present invention includes the above apparatus, wherein the sidewall is formed of a silicon nitride film.

  With this configuration, since the gate insulating film can be left when the sidewall is formed, plasma damage to the gate insulating film can be prevented.

  Further, the present invention includes the above device, wherein the sidewall is formed of a conductive film formed on the side wall of the gate electrode through an insulating film covering the surface of the gate electrode.

  Moreover, the present invention includes the above apparatus, wherein the conductive film is a silicon-based conductive film.

  Further, the present invention includes the above apparatus, wherein the conductive film is a polycrystalline silicon film.

  Further, the present invention includes the above apparatus, wherein the conductive film is an amorphous silicon film.

  The present invention includes the above device, wherein the conductive film is a metal film.

  Further, the present invention includes the above device, wherein the sidewall includes the stopper layer and a silicon oxide film formed on an upper layer of the stopper layer.

  Further, the present invention includes the above device, wherein the gate electrode is a MOSFET gate electrode.

  Further, the present invention includes the above device, wherein a solid-state imaging device including a photoelectric conversion unit and a charge transfer unit is arranged on the surface of the semiconductor substrate, and the MOSFET constitutes an amplifier circuit. .

  According to the above configuration, it is possible to provide a highly reliable semiconductor device in which the lifetime for hot carriers is increased and leakage current is suppressed.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)

  A MOSFET will be described as the semiconductor device of this embodiment. As shown in the enlarged view of FIG. 1, the MOSFET includes a gate electrode 3 formed of a doped polycrystalline silicon film on a surface of a silicon substrate 1 via a gate insulating film 2 formed of a silicon oxide film, and a gate electrode. A MOSFET having an LDD structure in which a source diffusion layer 5 and a drain diffusion layer 6 are formed through a channel formed below, and a side wall 7 formed on a side wall of the gate electrode 3 is formed of a silicon nitride film. It is characterized by that. Reference numerals 5L and 6L denote low-concentration impurity diffusion regions formed in the source and drain, respectively. In the present embodiment, the gate insulating film 2 serves as an etching stopper and remains on the substrate surface during anisotropic etching for forming the sidewall, so that the substrate surface and the side surface of the gate insulating film are plasma damaged under the gate electrode. It is possible to provide a MOSFET that is well maintained without being subjected to heat and has a lifetime against hot carriers.

Next, a method for manufacturing this MOSFET will be described.
First, for example, a gate insulating film 2 made of a silicon oxide film having a thickness of about 200 nm is formed on the surface of an n-type silicon substrate 1 having an impurity concentration of about 1.0 × 10 ¹⁶ cm ⁻³ by a thermal oxidation method. A polycrystalline silicon film 3 is formed by low pressure CVD. In film formation, doping is performed after the polycrystalline silicon film 3 is formed by a low pressure CVD method. The substrate temperature at this time shall be 800-950 degreeC. Then, a resist pattern for patterning the gate electrode is formed by photolithography. Then, anisotropic etching (RIE) is performed using the resist pattern as a mask to form a pattern of the gate electrode 3 (FIG. 2A).

  Thereafter, thermal oxidation is performed at 950 ° C. for about 30 minutes to form silicon oxide 4 having a thickness of about 10 nm around the gate electrode and on the surface of the silicon substrate 1 (post-oxidation). Thereafter, shallow ion implantation is performed at a low concentration using the gate electrode 3 as a mask to form low concentration impurity diffusion regions 5L and 6L (FIG. 2B).

Then, the silicon nitride film 7 is formed by the CVD method. (FIG. 2 (c)).
Thereafter, the silicon nitride film on the flat portion is removed by etching while leaving the silicon nitride film on the sidewall of the gate electrode 3 by anisotropic etching. At this time, the post oxide film 4 and the silicon oxide of the gate insulating film act as an etching stopper, thereby preventing the surface of the silicon substrate 1 from being exposed.

  Thereafter, p-type impurities are ion-implanted using the gate electrode 3 and the side-wall silicon nitride film 7 as a mask, and annealing is performed to form source and drain regions 5 and 6 (FIG. 2D). In this way, the MOSFET shown in FIG. 1 is obtained.

  In this way, the state in which the surface of the semiconductor substrate 1 is covered with the gate insulating film 2 can be easily maintained without being etched only by changing the material of the sidewall from the silicon oxide film to the silicon nitride film. Thus, it is possible to provide a semiconductor device having high hot carrier resistance without causing deterioration of characteristics such as damage to the edge portion of the gate insulating film and increase in leakage current of the transistor.

  In the above embodiment, a polycrystalline silicon film is used as the electrode, but an amorphous silicon film may be used instead.

(Embodiment 2)
Next, a second embodiment of the present invention will be described.
In the above embodiment, the silicon nitride film is used as the sidewall. However, instead of the silicon nitride film, a conductive film 7M such as a polycrystalline silicon film may be used as shown in FIG. Others are formed in the same manner as in the first embodiment.
In this case, when forming a semiconductor integrated circuit, it may be formed in the same process as other wiring layers, and can be formed without increasing the number of steps. In addition to a silicon-based conductive film such as an amorphous silicon film, other metal films such as tungsten, titanium, and aluminum may be used.

(Embodiment 3)
Next, a third embodiment of the present invention will be described.
In the present embodiment, as shown in FIG. 4, the sidewall itself is formed of the silicon oxide film 10, but a silicon nitride film is interposed as the stopper film 8. The rest is the same as in the first and second embodiments.

  In manufacturing, as shown in FIGS. 5A to 5E, a step of forming a silicon nitride film as the stopper film 8 is added to the steps shown in FIGS. 6A to 6D shown in the conventional example. Just do it.

  That is, as shown in FIGS. 6A and 6B, post oxidation is performed to form a silicon oxide film 4 around the gate electrode, and then a silicon nitride film 8 having a thickness of about 15 nm is formed by plasma CVD. (FIG. 5C).

Then, a silicon oxide film 9 is formed by the CVD method. (FIG. 5 (d)).
Thereafter, the silicon oxide film in the flat portion is removed by etching while leaving the silicon oxide film on the side wall of the gate electrode 3 by anisotropic etching. At this time, the silicon nitride film 8 as a stopper film acts as a stopper, and the surface of the silicon substrate 1 can be prevented from being exposed.

  Thereafter, the silicon nitride film 8 on the surface of the silicon substrate is removed by etching using the silicon oxide film 9 as a side wall formed in this way as a mask. Then, p-type impurities are ion-implanted using the gate electrode 3 and the silicon oxide film 9 on the side wall as a mask, and annealed to form source and drain regions 5 and 6 (FIG. 5E). The MOSFET shown in FIG. 4 is obtained.

  In this way, by forming a base film (stopper film) serving as a stopper prior to the formation of the sidewalls, the state in which the surface of the semiconductor substrate 1 is covered with the gate insulating film 2 without being etched is maintained. Therefore, it is possible to provide a semiconductor device having high hot carrier resistance without causing deterioration of characteristics such as damage to the edge portion of the gate insulating film and increase in leakage current of the transistor.

  This structure is particularly effective when it is necessary to reduce the thermal process for other element regions, such as a semiconductor integrated circuit, for example, a MOSFET formed in an amplifier circuit of a solid-state imaging element. Since it suffices to form the wiring layer and the like in the same process, it can be formed without increasing the number of steps.

  Although the MOSFET has been described in the above embodiment, the present invention can be applied to various semiconductor devices such as a memory device such as a floating gate type MOS memory in addition to a memory such as a DRAM using the MOSFET as a switching transistor.

  According to this configuration, since a MOS device having a long hot carrier life can be formed, it can be applied to various MOS LSIs including an amplifier circuit of a solid-state imaging device.

The figure which shows MOSFET of Embodiment 1 of this invention The figure which shows the manufacturing process of MOSFET of Embodiment 1 of this invention. The figure which shows MOSFET of Embodiment 2 of this invention The figure which shows MOSFET of Embodiment 3 of this invention The figure which shows the manufacturing process of MOSFET of Embodiment 3 of this invention. The figure which shows the manufacturing process of MOSFET of a prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate insulating film 3 Gate electrode 4 Silicon oxide film 5 Source region 6 Drain region 5L Low concentration impurity diffusion region 6L Low concentration impurity diffusion region 7 Silicon nitride film 8 Silicon nitride film (stopper)
9 Silicon oxide film

Claims (19)

A method of manufacturing a semiconductor device for forming a MOS device having an LDD structure on a surface of a semiconductor substrate,
Forming a gate electrode on the semiconductor substrate surface via a gate insulating film;
Oxidizing the surface of the gate electrode to form a post oxide film;
A step of performing low concentration impurity diffusion using the gate electrode as a mask to form a low concentration diffusion region;
Forming a sidewall including a stopper layer made of a material having etching selectivity with respect to the gate insulating film on the post oxide film; and
Forming a source / drain region having a concentration higher than that of the low concentration diffusion region by performing impurity diffusion using the gate electrode and the sidewall as a mask. A method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the step of forming the sidewall includes a step of forming a silicon nitride film. A method of manufacturing a semiconductor device according to claim 1,
The step of forming the sidewall includes a step of forming a conductive film through a post oxide film covering the periphery of the gate electrode. A method of manufacturing a semiconductor device according to claim 3,
The method for manufacturing a semiconductor device, wherein the conductive film is a silicon-based conductive film. The semiconductor device according to claim 4,
The method for manufacturing a semiconductor device, wherein the conductive film is a polycrystalline silicon film. The semiconductor device according to claim 4,
The method for manufacturing a semiconductor device, wherein the conductive film is an amorphous silicon film. The semiconductor device according to claim 4,
The method for manufacturing a semiconductor device, wherein the conductive film is a metal film. The semiconductor device according to claim 1,
The sidewall forming step includes a step of forming the stopper layer and a step of forming a silicon oxide film on the stopper layer. A method of manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the gate electrode is a gate electrode of a MOSFET. A semiconductor device in which a MOS device having an LDD structure is formed on the surface of a semiconductor substrate,
A semiconductor device including a stopper layer in which a sidewall formed on a sidewall of a gate electrode is made of a material having etching selectivity with respect to a gate insulating film. The semiconductor device according to claim 10,
The sidewall is a semiconductor device composed of a silicon nitride film. The semiconductor device according to claim 10,
The side wall is a semiconductor device composed of a conductive film formed on a side wall of a gate electrode via an insulating film covering the surface of the gate electrode. The semiconductor device according to claim 12,
The semiconductor device, wherein the conductive film is a silicon-based conductive film. The semiconductor device according to claim 13,
The semiconductor device, wherein the conductive film is a polycrystalline silicon film. The semiconductor device according to claim 13,
The semiconductor device, wherein the conductive film is an amorphous silicon film. The semiconductor device according to claim 12,
The semiconductor device, wherein the conductive film is a metal film. The semiconductor device according to claim 10,
The side wall is a semiconductor device including the stopper layer and a silicon oxide film formed in an upper layer of the stopper layer. A semiconductor device according to any one of claims 10 to 17,
The semiconductor device, wherein the gate electrode is a gate electrode of a MOSFET. The semiconductor device according to claim 18,
A solid-state imaging device having a photoelectric conversion unit and a charge transfer unit is arranged on the surface of the semiconductor substrate,
The MOSFET is a semiconductor device that constitutes an amplifier circuit.

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