JPH06291269A - Filed-effect transistor - Google Patents

Abstract

PURPOSE:To improve short channel effect and further reduce the entire occupied area. CONSTITUTION:A first semiconductor layer 21 forming a field-effect transistor FET1 of a first conductive channel and a second semiconductor layer 22 forming a field-effect transistor FET2 of a second conductive channel are laminated via an insulation layer. First and second insulation gate electrodes 31, 32 are formed on the surface in the mutual reverse side of the first and second semiconductor layers 21, 22 in a mutual opposed location. A common third insulation gate electrode 33 with respect to both transistors FET1, FET2 is disposed between the first and second semiconductor layers 21, 22 and opposed to each of the first and second insulation gate electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a so-called CMOS having an insulated gate type p channel type field effect transistor and an n channel type field effect transistor.

[0002]

2. Description of the Related Art An ordinary CMOS has a p-channel type M
Since the OS and the n-channel MOS are arranged in a plane, there is a limit to the improvement of the integration density.

If the MOS is miniaturized and the channel is shortened in order to improve the integration density, the problem of the short channel effect arises.

On the other hand, a so-called double gate MOS
Or, it is known that the XMOS can completely deplete the channel, has a good S factor, that is, a weak inversion characteristic, and improves the short channel effect.

This double gate MOS or XMOS
6, a channel layer 1c is formed of a semiconductor layer 1 having a low impurity concentration, and a source region 1s and a drain region 1d are formed on both sides of the channel layer 1c with the semiconductor layer 1 having a low impurity concentration interposed therebetween. Insulated gate electrodes 2g ₁ and 2g ₂ are arranged on both surfaces of the channel layer 1c of the layer 1 so as to face each other with gate insulating layers 2i ₁ and 2i ₂ interposed therebetween.

Such double gate MOS or X
If the MOS is applied to the CMOS, the short channel effect can be improved due to the miniaturization of the MOS.

[0007]

As described above, the present invention aims to improve the short channel effect by adopting the double gate MOS structure in which the insulating gates are formed on both surfaces of the channel layer, as described above. The overall occupied area is reduced.

[0008]

According to the present invention, a first conductivity type, for example, a p-channel field effect transistor FET ₁ is formed as shown in FIG. Semiconductor layer 21 and a second semiconductor layer 22 having a second conductivity type, for example, an n-channel field effect transistor FET ₂ formed thereon, are stacked with an insulating layer in between, and the first and second semiconductor layers 21 and The first and second insulated gate electrodes 31 are provided on the opposite surfaces of the first electrode 22 and the second insulated gate electrode 31.
And 32 are formed, and a common third insulated gate electrode 33 for both transistors FET ₁ and FET ₂ is provided between the first and second semiconductor layers 21 and 22 so as to face each of the first and second insulated gate electrodes. It will be arranged.

Further, the present invention has a structure in which the first and second insulated gate electrodes 31 and 32 are electrically connected to each other in the above-mentioned structure, as shown in the circuit structure of FIG.

Further, according to the present invention, as shown in the circuit configuration of FIG. 3, first and second insulated gate electrodes 31 and 32 are provided.
And the third insulated gate electrode 33 are electrically connected together.

[0011]

According to the above-described structure of the present invention, since the p-channel type MOS and the n-channel type MOS forming the CMOS are stacked, the total occupied area is reduced and each MOS is formed. Since each is a double gate type MOS, the short channel effect can be avoided, each MOS can be miniaturized, and the density of CMOS can be increased.

Further, both transistors of the CMOS have a structure in which they are laminated in spite of both being a double gate type MOS. Further, this laminated structure makes it possible to configure one of the gates in common. Can be simplified and reduced.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION As described above, the present invention is based on FIG.
P-channel field effect transistor
FET₁The first semiconductor layer 21 in which
Nell type field effect transistor FET₂ The second formed
And the semiconductor layer 22 of are stacked via an insulating layer.
And the surfaces of the second semiconductor layers 21 and 22 opposite to each other.
The first and second insulated gate electrodes 3 at positions facing each other.
1 and 32 are formed, and the first and second semiconductor layers 21 and
And 22 between both transistor FET₁And FET ₂ Against
The common third insulated gate electrode 33 is
It is arranged so as to face the edge gate electrode.

Further, the present invention has a structure in which the first and second insulated gate electrodes 31 and 32 are electrically connected to each other in the above structure, as shown in the circuit structure of FIG.

Further, according to the present invention, as shown in the circuit configuration of FIG. 3, the first and second insulated gate electrodes 31 and 32 are provided.
And the third insulated gate electrode 33 are electrically connected together.

An embodiment of the field effect transistor according to the present invention will be described with reference to FIG. 4 together with an example of its manufacturing method.

In this example, as shown in FIG. 4A, the substrate 4
1. For example, a Si semiconductor substrate, a quartz substrate or the like is prepared, and when the substrate 41 has conductivity, an insulating layer (not shown) such as SiO ₂ is formed by CVD or the like. A first insulated gate electrode 31 is formed on this. The gate electrode 31 is made of, for example, polycrystalline Si formed over the entire surface to a thickness of about 2000 Å, and is formed by photolithography using, for example, R
A desired pattern is formed by anisotropic etching by IE (reactive ion etching).

A thickness of, for example, 20 is formed on the gate electrode 31.
A first gate insulating layer 51 of SiO ₂ of 0Å is entirely formed by, for example, high temperature CVD.

Then, the first semiconductor layer 21 is formed over the entire surface. The first semiconductor layer 21 is crystallized by forming Si to a thickness of 500 Å by CVD and performing laser annealing by laser light irradiation.

Thereafter, as shown in FIG. 4B, the first semiconductor layer 21 is patterned into a required pattern. Further, a first intermediate gate insulating layer 5 is formed on the entire surface thereof.
3 is formed. The first intermediate gate insulating layer 53 is formed by the same method and thickness as the above-mentioned first gate insulating layer 51. Then, the third insulated gate electrode 33 is formed directly on the first insulated gate electrode 31 on the first intermediate gate insulating layer 53. The third insulated gate electrode 33 can be formed by a method similar to that of the first insulated gate electrode 31.

Next, using the third insulated gate electrode 33 as a mask, the first semiconductor layer 21 is doped with, for example, boron B of a first conductivity type, for example, p-type impurity, for example, 20 ke.
At V, ions are implanted with a dose amount of 2 × 10 ¹⁵ ions / cm ² to form high-concentration source / drain regions 61a and 62b of the first MOS transistor FET ₁ , and a gate electrode between these regions 61a and 61b. A low-concentration first channel forming portion 71 is formed below which impurities are not ion-implanted.

As shown in FIG. 4C, a second intermediate gate insulating layer 54 is formed on the entire surface. The formation of the second intermediate gate insulating layer 54 is performed by the above-described first gate insulating layer 5
It can be formed by a method similar to that of 3.

Then, the first MOS transistor FET
_One of the source / drain regions, for example, region 6
An opening 55 is formed in the insulating layers 53 and 54 on the surface 1a to expose a part of the region 61a to the outside, and the region 61a is electrically contacted through the opening 55 to entirely cover the second semiconductor layer 22. Form. This second semiconductor layer 22
Also, for example, Si is formed to a thickness of 500 Å by CVD, and laser annealing is performed by laser light irradiation to crystallize. Then, the second semiconductor layer 2 is patterned into a required pattern.

Further, the first gate insulating layer 52 is formed on the entire surface by the same method and thickness as the above-mentioned first gate insulating layer 51. Then, the second insulated gate electrode 32 is formed directly on the first and third insulated gate electrodes 31 on the second gate insulating layer 53. The formation of the second insulated gate electrode 32 is performed by the formation of the first insulated gate electrode 3
It can be formed by the same method as 1.

Using the second gate electrode 32 as a mask, a second conductivity type, for example, n, is applied to the second semiconductor layer 22.
Type impurities, eg As, at 20 keV, 2 × 1
The second M is formed by ion implantation with a dose of 0 ¹⁵ ions / cm ^2.
The high-concentration source / drain regions 62a and 62b of the OS transistor FET ₂ are formed, and a low-concentration second channel forming portion 72 in which impurities are not ion-implanted is formed under the gate electrode 32 between these regions 62a and 62b.

As shown in FIG. 4D, a protective insulating layer 8 is formed on the entire surface.
0 through the through holes 83 and 84 reaching both source / drain regions 62a and 62b of the second semiconductor layer 21 through the protective insulating layer 80 on the regions 62a and 62b and the gate insulating layer 53 therebelow. Make a hole. In addition, a through hole 85 reaching the second semiconductor layer 22 and the other source / drain region 61b not in contact with the second semiconductor layer 22 and the source / drain region 62a is formed on the protective insulating layer 80 on the region 61B. The gate insulating layers 52, 54, and 53 below are formed so as to penetrate.

On the other hand, in advance, for example, as shown in FIG. 5 which is a cross-sectional view orthogonal to the plane of FIG. 4D and crossing the gate portion, the above-mentioned first and second gate electrodes 31 and 32 are led out to portions other than the gate portion. Are contacted with each other, and a through hole 81 reaching the extended portion of the second gate electrode 31 is formed in the protective insulating layer 80 on this contact portion.

Also regarding the third gate electrode 33,
As shown in FIG. 5, an extending portion extending to another portion is formed in advance, and a through hole 82 reaching this extending portion is formed in each gate insulating layer and protective insulating layer 80 thereabove. .

Then, as shown in FIGS. 5 and 4D, each of the through holes 81 to 85 is filled with a conductor such as W or WSi, that is, a so-called plug-in is performed, and wiring layers 91 to 95 of Al etc. are further formed on these. And terminal t ₁
Carry out the derivation of ~t _5.

The circuit configuration according to this configuration can form the inverter circuit shown in FIG. 2, and in this case, the terminal t ₁
As an input terminal, the terminal t ₃ as an output terminal, a fixed voltage such as a ground voltage is applied to the terminal t ₂ , and the terminals t ₄ and t ₅ are power supply terminals V _DD and V _SS .

In this case, the terminal t ₂ can be used as an input terminal and a fixed voltage can be applied to the terminal t ₁ .

In the above-mentioned example, the predetermined source / drain regions 61a and 62a of the first and second semiconductor layers are connected through the opening 55 as described with reference to FIG. 4C. As shown in FIG.
It is also possible to connect by etc.

In the example described above, the terminal t ₂ is derived from the third insulated gate electrode 33, but this electrode 33 is the first and second insulated gate electrodes 31 and 32.
As shown in FIG. 3, a common terminal t ₁ can be derived as a pattern in which the extension portions directly contact each other.

The present invention is not limited to the above-described example. For example, in the above-mentioned example, the semiconductor layers 21 and 22 are crystallized by laser annealing. Can also be applied.

Further, the first to third gate electrodes 31 to 33
Is not limited to polycrystalline Si, and various modifications and changes can be made, for example, a structure in which a metal silicide is laminated on a polycrystalline Si layer to reduce resistance.

[0036]

According to the above-described configuration of the present invention, since the p-channel type MOS and the n-channel type MOS constituting the CMOS are stacked, the total occupied area is reduced and Since each MOS is a double gate type MOS, each short channel effect can be avoided, each MOS can be miniaturized, and the density of CMOS can be increased.

Further, both transistors of the CMOS have a structure in which they are laminated in spite of both being a double gate type MOS, and further, due to this laminated structure, one of the gates can be commonly configured. Can be simplified and reduced.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing the basic structure of a field effect transistor according to the present invention.

FIG. 2 is a circuit configuration diagram of the present invention.

FIG. 3 is another circuit configuration diagram of the present invention.

FIG. 4 is a process drawing of an example of a method of manufacturing the field effect transistor according to the present invention.

FIG. 5 is a process drawing in another cross section of one process in FIG. 4;

FIG. 6 is a schematic cross-sectional view of a conventional field effect transistor.

[Explanation of symbols]

 21 first semiconductor layer 22 second semiconductor layer 31 first insulated gate electrode 32 second insulated gate electrode 33 third insulated gate electrode

Claims (3)

[Claims] 1. A first semiconductor layer having a field-effect transistor of a first conductivity type channel formed therein and a second semiconductor layer having a field-effect transistor of a second conductivity type channel forming an insulating layer 23. And the first and second insulated gate electrodes are formed on the opposite surfaces of the first and second semiconductor layers at positions facing each other, and between the first and second semiconductor layers. A field effect transistor, wherein a third insulated gate electrode 33 common to both transistors is arranged to face the first and second insulated gate electrodes. 2. The field effect transistor according to claim 1, wherein the first and second insulated gate electrodes are electrically connected. 3. The first and second insulated gate electrodes,
The field effect transistor according to claim 1, wherein the third insulated gate electrode is electrically connected together.