JP2000150892A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that has SOI structure such as SOI MOSFET with superior characteristics, and its manufacturing method. SOLUTION: In a semiconductor device with SOI structure, an insulator in the SOI structure is allowed to project at the side of a semiconductor layer, and the thickness of the semiconductor layer of the part is set smaller than that of the semiconductor layer around the part. In SOI MOSFET, the separation oxide film 2 between elements directly below a gate electrode 5 is allowed to project at the side of an Si activation layer 3, and the thickness of the Si activation layer 3 directly below the gate electrode 5 is set smaller than that of the Si activation layer 3 of source and drain regions 7 and 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an SOI (Siliconon Insu).
lator) structure.

[0002]

2. Description of the Related Art In a MOSFET having an SOI structure (hereinafter referred to as "SOI MOSFET"), the thickness of a Si active layer immediately below a gate electrode is thin as a parameter affecting device characteristics such as a threshold voltage. It is desirable to increase the thickness of the Si active layer in the source region and the drain region as a parameter affecting their parasitic resistance.

As described above, there is a so-called trench gate as a structure in which the thickness of an Si active layer is locally changed in an SOI MOSFET. As a formation method, a so-called LOCOS (Local Oxidation of Silicon) method is used. Known processes (eg, IEEE
Electron Device Lett., Vol.15, pp.22-24). That is, in this method, first, an oxidation mask having a gate electrode formation site opened is formed on an SOI substrate, and then the Si active layer is thermally oxidized using the oxidation mask to selectively oxidize the gate electrode formation site. Form a film. Next, this oxide film is removed by etching. This removes the Si active layer at the gate electrode formation site. A gate electrode is formed at the bottom of the thus formed groove via a gate insulating film.

[0004] SOI MOS formed by this method
FIGS. 13, 14 and 15 show an example of the structure of the FET. Here, FIG. 13 is a sectional view of the SOI MOSFET parallel to the channel length direction, and FIG.
FIG. 15 is a plan view of the SFET, and FIG. 15 is a sectional view taken along the line XV-XV in FIG. FIG. 13 shows XIII-XI of FIG.
It is an expanded sectional view which follows an II line.

[0005] As shown in FIGS. 13, 14 and 15, in this conventional SOI MOSFET, the Si
On a substrate 101, an Si active layer 103 is formed surrounded by an element isolation oxide film. A groove 103a is formed on the surface of the Si active layer 103 at the gate electrode portion by removing an oxide film formed by selectively oxidizing the Si active layer 103 by the LOCOS method.
Are formed. A gate electrode 105 is formed at the bottom of the groove 103a with a gate insulating film 104 interposed therebetween. A side wall 106 is formed on a side wall of the gate electrode 105. In the Si active layer 103,
The source region 10 is self-aligned with the gate electrode 105.
7 and the drain region 108 are formed. The source region 108 and the drain region 109 are formed in a lower portion of the side wall 106 at a low impurity concentration portion 107.
a, 108a and a so-called LDD (Lightly Doped
Drain) structure. Further, metal silicide films 109 and 110 are formed above the source region 107 and the drain region 108, respectively.

According to this SOI MOSFET, FIG.
As shown in FIG. 3, the trench 103a is formed in the Si active layer 103 by removing the oxide film formed by the LOCOS method, so that the Si active layer 103 becomes thin only in a portion immediately below the gate electrode 105. In this sense, a desired structure is obtained.

[0007]

However, in the above-described SOI MOSFET, when the oxide film formed by the LOCOS method is removed by etching, the S
The surfaces of the i-active layer 103 and the isolation oxide film 102 are also etched by over-etching. In particular, FIG.
In FIG. 15, an oxide film is easily formed at the time of oxidation by the LOCOS method, and the Si active layer 103 is also etched from the side surface of the inter-element isolation oxide film 102 where over-etching proceeds. As described above, the thickness of the end portion of the Si active layer 103 becomes particularly small.

As a result, when this SOI MOSFET is operated, an electric field is excessively concentrated in a portion indicated by a dotted-line circle in FIG. There is a high possibility that the device characteristics such as the kink phenomenon will be adversely affected.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a semiconductor device having an SOI structure such as an SOI MOSFET having good characteristics and a method of manufacturing the same.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor device having an SOI structure, wherein an insulator partially extends toward a semiconductor layer in the SOI structure. In addition, the thickness of the semiconductor layer in the portion where the insulator protrudes is smaller than the thickness of the semiconductor layer in the peripheral portion.

Here, the term “SOI” means a semiconductor layer (Semiconductor on Insulator) on an insulator, including a Si layer (Silicon on Insulator) on the insulator (the same applies hereinafter).

In the first invention, typically, the SOI
The semiconductor layer forming the structure is surrounded by an insulator and is electrically insulated from the outside. Typically, a plurality of semiconductor layers constituting the SOI structure are provided separately from each other, and an insulator protrudes on at least one of these semiconductor layers.

In the first invention, typically, a MIS transistor is provided in a semiconductor layer. And
The insulator immediately below the gate electrode of the MIS transistor overhangs the semiconductor layer side, and the thickness of the semiconductor layer at the portion where the insulator overhangs is the thickness of the semiconductor layer at the source and drain regions of the MIS transistor. Less than.

In one typical example of the first invention, full-depletion (Full-depletion) is applied to the semiconductor layer on which the insulator has protruded.
A Depletion MIS transistor is provided, and a Partial Depletion MIS transistor is provided in a semiconductor layer where an insulator does not protrude. Here, the full depletion type MIS transistor means a MIS transistor in which a depletion layer reaches the vicinity of an insulator below a semiconductor layer during operation, and is said to have a steep subthreshold characteristic. Also,
A partial depletion type MIS transistor means a MIS transistor in which a depletion layer does not reach the vicinity of an insulator below a semiconductor layer during operation, and is relatively resistant to variation in the thickness of a semiconductor layer which is an active layer. It is said.

In another example of the first invention, the thickness of the semiconductor layer at the portion where the insulator protrudes changes in the channel width direction of the MIS transistor. The MIS transistor has a full depletion MIS transistor portion and a partial depletion MIS transistor portion. That is, since the thickness of the semiconductor layer changes in the channel width direction of the MIS transistor,
A portion having a small thickness can be a full depletion MIS transistor portion, and a portion having a large thickness can be a partial depletion MIS transistor portion.

According to a second aspect of the present invention, there is provided an SOI structure in which an insulator partially protrudes to the semiconductor layer side and a thickness of the semiconductor layer in a portion where the insulator protrudes. In a method for manufacturing a semiconductor device, the thickness of which is smaller than the thickness of a semiconductor layer in a peripheral portion thereof, a step of forming an SOI substrate, and a step of partially removing a semiconductor layer near an interface between the insulator and the semiconductor layer in the SOI substrate. And a step of forming

In the second invention, typically, the SO
After partially ion-implanting oxygen into the semiconductor layer near the interface between the insulator and the semiconductor layer in the I-substrate, heat treatment is performed to oxidize the portion of the semiconductor layer into which oxygen has been ion-implanted to form a portion of the semiconductor layer. It becomes an insulator. More specifically, for example, a mask in which a gate electrode formation site is opened is formed on an SOI substrate, oxygen is ion-implanted using the mask, the mask is removed, and then a gate insulating film is formed over the semiconductor layer. To form a gate electrode. Alternatively, a mask having a gate electrode formation site opened on an SOI substrate is formed,
Oxygen is ion-implanted using the mask, a gate electrode is formed in an opening of the mask via a gate insulating film, and then the mask is removed. In the latter method, a portion of the semiconductor layer to be an insulator, that is, a portion of the SOI structure where the insulator protrudes toward the semiconductor layer and the gate electrode can be formed in a self-aligned manner.

According to the first aspect of the present invention configured as described above, the insulator partially extends to the semiconductor layer side, and the thickness of the semiconductor layer at the portion where the insulator extends is reduced. Since the thickness is smaller than the thickness of the semiconductor layer in the peripheral portion, for example, when an SOI MOSFET is formed in this semiconductor layer, it is possible to secure a favorable sub-threshold characteristic and improve current driving capability. Moreover, the semiconductor layer is locally thinned by overhanging the insulator to the semiconductor layer side, and the oxide layer formed on the semiconductor layer by the LOCOS method is removed to locally thin the semiconductor layer. It is possible to avoid a problem in the technology, that is, a problem of deterioration of characteristics due to a concentration of an electric field at the end of the semiconductor layer being thinned.

According to the second aspect of the present invention, S
The semiconductor layer in the vicinity of the interface between the insulator and the semiconductor layer in the OI substrate is partially made into an insulator, so that the insulator partially projects to the semiconductor layer side, and the portion of the insulator where the insulator projects is formed. A structure in which the thickness of the semiconductor layer is smaller than the thickness of the semiconductor layer in the peripheral portion can be easily formed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

FIGS. 1 to 3 show an SOI MOSFET according to an embodiment of the present invention. Here, FIG.
2 is a cross-sectional view of the IMOSFET parallel to the channel length direction, FIG. 2 is a plan view of the SOI MOSFET, and FIG. 3 is a cross-sectional view taken along the line III-III of FIG. FIG. 1 is FIG.
FIG. 2 is an enlarged sectional view taken along line II of FIG.

As shown in FIGS. 1, 2 and 3, in the SOI MOSFET according to this embodiment, S
An island-shaped Si active layer 3 having a flat surface is formed on an i-substrate 1 by being surrounded by an element isolation oxide film 2 made of, for example, a SiO ₂ film. A gate electrode 5 is formed on the Si active layer 3 with a gate insulating film 4 interposed therebetween. As the gate insulating film 4, for example, an SiO ₂ film is used. The gate electrode 5 is made of polycrystalline Si doped with impurities.
It is composed of a film, a polycide film on which a refractory metal silicide film is laminated. On the side wall of the gate electrode 5, a side wall 6 made of an insulator such as SiO ₂ is provided. In the Si active layer 3, a source region 7 and a drain region 8 are formed in self-alignment with the gate electrode 5. Source region 7 and drain region 8 are n-type when this SOI MOSFET is an n-channel, and are p-type when this SOI MOSFET is a p-channel. The source region 7 and the drain region 8 have low impurity concentration portions 7a and 8a in a portion below the sidewall 6, and have an LDD structure. Further, metal silicide films 9 and 10 such as a Ti silicide film and a Co silicide film are formed on the source region 7 and the drain region 8, respectively.

In this embodiment, the gate electrode 5
Is formed on the element isolation oxide film 2 immediately below the gate electrode 5 so that the thickness of the Si active layer 3 immediately below the gate electrode 5 is reduced to other portions. Is smaller than the thickness of the Si active layer 3. In this case, S in the portion immediately below the gate electrode 5
The thickness of the i-active layer 3 is designed to be sufficiently thin with respect to parameters such as a depletion layer width during operation, in consideration of device characteristics such as a threshold voltage. Further, the Si active layer 3 in a portion immediately below the source region 7 and the drain region 8
The thickness of the source region 7 and the drain region 8
Is set to a sufficient thickness so as to reduce the parasitic resistance.

Although illustration is omitted, in practice this S
An interlayer insulating film is formed so as to cover the OI MOSFET, a predetermined contact hole is formed in the interlayer insulating film, and an upper wiring is formed.

Next, a description will be given of a first example of a method of manufacturing the SOI MOSFET according to the embodiment having the above-described configuration.

In the first example, first, as shown in FIG. 4, the S
An Si active layer 3 surrounded by an isolation oxide film 2 is formed on an i-substrate 1. Various processes are known as the SOI substrate manufacturing process.
So-called SIMOX (Separation by Implanted Oxyge
n) This is called the law. In this method, oxygen is ion-implanted into the Si substrate 1, and a layered oxide film is formed by oxidizing the oxygen-implanted layer.
By forming a lateral element isolation oxide film on an I substrate, that is, a SIMOX substrate by a LOCOS method,
An Si active layer 3 surrounded by an isolation oxide film 2 is formed on an i-substrate 1.

Next, on this SOI substrate, a mask 1 made of, for example, a photoresist having an opening at a gate electrode formation site.
After forming the mask 11 by lithography, the mask 11
Is used to implant oxygen ions into the Si active layer 3. In this ion implantation, the acceleration energy is set so that the implanted oxygen reaches the vicinity of the interface between the Si active layer 3 and the element isolation oxide film 2, and the dose is set to the finally formed element isolation oxide film 2. Active layer 3 in the area of the overhang 2a
Is set to have an appropriate value. Due to the oxygen ion implantation, the oxygen implanted layer 1
2 are formed (in FIG. 4, the implanted oxygen is indicated by +). In order to prevent the surface of the Si active layer 3 from being roughened by the ion implantation of oxygen, an oxide film is previously formed on the surface of the Si active layer 3 before the ion implantation of oxygen. Oxygen ion implantation may be performed through a film.

Next, after removing the mask 11 by plasma ashing or the like, a heat treatment is performed to oxidize the oxygen injection layer 12 formed in the Si active layer 3. The temperature of this heat treatment is, for example, about 1300 ° C. as in the case of producing the SIMOX substrate. As a result, as shown in FIG. 5, an overhang portion 2a is formed in the element isolation oxide film 2 in a portion immediately below the gate electrode formation site.

Next, as shown in FIG. 6, the surface of the Si active layer 3 is oxidized by, for example, a thermal oxidation method to form a gate insulating film 4, and a gate is formed on the gate insulating film 4 by, for example, a CVD method. After forming films made of materials for forming electrodes, these films are subjected to, for example, reactive ion etching (R).
The gate electrode 5 is formed by patterning by the IE) method. Before performing the ion implantation of oxygen,
When an oxide film is formed on the surface of the active layer 3, the oxide film is removed before forming the gate insulating film 4.

Next, using this gate electrode 5 as a mask,
Impurities of the same conductivity type as the channel conductivity type are ion-implanted into the Si active layer 3 at a low concentration. Next, for example, C
After forming the SiO ₂ film by VD method, by etching back the SiO ₂ film by RIE, as shown in FIG. 1, to form a side wall 6 to the side walls of the gate electrode 5. Next, using the side wall 6 and the gate electrode 5 as a mask, impurities of the same conductivity type as the channel conductivity type are ion-implanted into the Si active layer 3 at a high concentration. Thereafter, heat treatment for electrically activating the implanted impurities is performed as necessary. Thus, source region 7 and drain region 8 are formed in Si active layer 3 in a self-aligned manner with respect to gate electrode 5.

Next, the upper portions of the source region 7 and the drain region 8 are silicided by a normal silicidation method to form metal silicide films 9 and 10, respectively.

Thereafter, through necessary steps such as formation of an interlayer insulating film, formation of a contact hole, and formation of an upper wiring,
Complete the target SOI MOSFET.

Next, a description will be given of a second example of a method of manufacturing the SOI MOSFET according to the embodiment configured as described above.

In the second example, first, as shown in FIG. 7, a Si active layer 3 surrounded by an inter-element isolation oxide film 2 is formed on a Si substrate 1 by a method similar to the first example. Form.

Next, after forming a mask 11 made of, for example, an inorganic material having a gate electrode formation site opened on the SOI substrate, the mask 11 is used to form a Si active layer 3 in the Si active layer 3 in the same manner as described in the first example. The oxygen implantation layer 12 is formed at the bottom of the Si active layer 3 by ion implantation of oxygen under appropriate conditions. Specifically, an oxide film, for example, a nitrogen silicate glass (NSG) film is used as a material of the mask 11. As in the case of the first example, before performing the oxygen ion implantation, an oxide film is formed on the surface of the Si active layer 3 at the opening of the mask 11 in advance, and the oxide film is formed through the oxide film. Oxygen ion implantation may be performed.

Next, the oxygen injection layer 12 formed in the Si active layer 3 is oxidized. The temperature of this heat treatment is, for example, about 1300 ° C. as in the first example. As a result, FIG.
As shown in FIG. 5, an overhang 2a is formed in the inter-element isolation oxide film 2 just below the gate electrode formation site.

Next, the gate insulating film 4 is formed by oxidizing the surface of the Si active layer 3 in the opening of the mask 11 by, for example, a thermal oxidation method. The heat treatment for forming the gate insulating film 4 may also serve as a heat treatment for oxidizing the oxygen-implanted layer 12 to form the overhang portion 2a of the inter-element isolation oxide film 2.

Next, after a film for forming a gate electrode is formed on the entire surface of the substrate by, for example, the CVD method, the film is etched back by the RIE method until the mask 11 is exposed, or by the CMP (Chemical Mechanical Polishing) method. The portion other than the opening of the mask 11 is removed by polishing or the like. Thereby, as shown in FIG.
The gate electrode 5 is formed in the opening of the mask 11. In this case, the gate electrode 5 is formed in a self-aligned manner with respect to the opening of the mask 11, and the overhanging portion 2 a of the inter-element isolation oxide film 2 is formed in a self-aligned manner with the opening of the mask 11. Therefore, the gate electrode 5 is formed in a self-aligned manner with respect to the overhang portion 2a of the inter-element isolation oxide film 2.

Next, after the mask 11 is removed by etching by RIE or the like, the steps subsequent to the formation of the sidewall 6 are advanced in the same manner as in the first example, and the SOI shown in FIG.
Complete the MOSFET.

According to the manufacturing methods of the first and second examples described above, the overhang portion 2a can be easily formed in the element isolation oxide film 2 in a portion immediately below the gate electrode 5, whereby The thickness of the Si active layer 3 immediately below the gate electrode 5 can be locally reduced. Further, in particular, according to the second example, since the gate electrode 5 can be formed in a self-aligned manner with respect to the overhang portion 2a of the inter-element isolation oxide film 2, controllability of FET characteristics is improved. And is advantageous in miniaturizing the element.

As described above, according to this embodiment,
The following various advantages can be obtained. That is,
The element isolation oxide film 2 just below the gate electrode 5 is made of Si.
The protrusion to the active layer 3 side allows the gate electrode 5
The thickness of the Si active layer 3 immediately below the gate electrode can be locally reduced sufficiently, and the FET such as a sub-threshold characteristic can be formed.
The controllability of characteristics can be improved. Further, since the thickness of the Si active layer 3 in the source region 7 and the drain region 8 can be locally increased sufficiently, the parasitic resistance of the source region 7 and the drain region 8 can be sufficiently reduced. In addition, FET characteristics such as current driving capability can be improved. That is, when the thickness of the Si active layer 3 is designed to be uniform, both of them, which are in a trade-off relationship, can be simultaneously achieved by the local thickness control technique of the Si active layer 3.

In this embodiment, the overhanging portion 2a is provided in the inter-element isolation oxide film 2 so that
By reducing the thickness of the Si active layer 3 immediately below the gate electrode 5, the conventional SOIM
As in the case of the OSFET, a problem that occurs when the thickness of the Si active layer immediately below the gate electrode is reduced by etching an oxide film formed on the Si active layer by the LOCOS method, Can be prevented from becoming thinner, electric field concentration occurs in that portion, and the characteristic is degraded.

Further, for example, in the SOI MOS LSI, the SOI MOSFET according to the embodiment in which the thickness of the Si active layer 3 in the portion immediately below the gate electrode 5 is reduced is used for a part of the SOI MOSFET, and the other SOI MOSFET is used. In the MOSFET, the S active layer 3 having a uniform thickness is used.
By using the OI MOSFET, the thickness of the Si active layer 3 in the portion immediately below the gate electrode 5 can be controlled for each element. Then, for example, the SOI MOSFET according to this embodiment is replaced with a full depletion type S
Since an SOI MOSFET having a uniform thickness of the Si active layer 3 can be used as a partial depletion type SOI MOSFET, these full depletion type SOI MOSFETs can be used.
A circuit utilizing characteristics of the MOSFET and the partial depletion type SOI MOSFET can be configured, and the range of LSI design can be expanded.

More specifically, for example, a full depletion type SOI MO having excellent subthreshold characteristics is provided.
Some SOIs based on SFETs and driving high loads
MOSFET is DTMOS (Dynamic Threshold MOS)
FET) makes it possible to design an LSI that can achieve high speed and low power consumption. here,
DTMOS is a partial depletion type SO
This is a short-circuit connection between the body terminal and the gate terminal of the IMOSFET. FIG. 10 shows an equivalent circuit of the DTMOS. FIGS. 11 and 12 show an example of a DTMOS structure. Here, FIG. 11 is a plan view, and FIG. 12 is a cross-sectional view along line XII-XII in FIG. In FIGS. 11 and 12, reference numeral 13 denotes a wiring in contact with the Si active layer 3 and is electrically connected to the gate electrode 5.

Furthermore, the SOI according to this embodiment is
In the MOSFET, the height of the overhang portion 2a of the inter-element isolation oxide film 2 is changed in the channel width direction, and the thickness of the Si active layer 3 immediately below the gate electrode 5 is changed in the channel width direction. One SOI MOSF
Partially full depletion type SOIMO in ET
SFET and partial depletion type SOI
MOSFETs can be built.

As described above, one embodiment of the present invention has been specifically described. However, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. .

For example, the structures, materials, processes, and the like described in the above embodiment are merely examples, and different structures, materials, processes, and the like may be used as necessary.

Specifically, in the above-described embodiment, the case where the present invention is applied to the SOI MOSFET having the LDD structure has been described.
Needless to say, the present invention can be applied to an SOI MOSFET having no DD structure. In this case, the sidewall 6 does not need to be formed unless it is necessary to use it for another purpose.

In the above-described embodiment, the Si
Although the case where the SOI MOSFET is formed on the active layer 3 has been described, in some cases, the SOI MOSFET may be formed on the Si active layer 3.
A MESFET may be formed. Further, an active layer made of a compound semiconductor such as GaAs is used in place of the Si active layer 3, and the active layer is formed of SOI GaAs MESFE.
T or the like may be formed.

[0050]

As described above, according to the semiconductor device of the present invention, the insulator partially extends to the semiconductor layer side, and the thickness of the semiconductor layer at the portion where the insulator overhangs is reduced. Since the thickness is smaller than the thickness of the semiconductor layer in the peripheral portion, for example, an SOI MOSFET
When forming, it is possible to ensure good sub-threshold characteristics and improve current drive capability,
The problem of characteristic deterioration due to electric field concentration due to the thinner end portion of the semiconductor layer can be solved.

According to the method of manufacturing a semiconductor device of the present invention, the semiconductor layer near the interface between the insulator and the semiconductor layer in the SOI substrate is partially made into an insulator, so that the insulator becomes closer to the semiconductor layer. A structure in which the thickness of the semiconductor layer at the portion where the insulator overhangs and the thickness of the semiconductor layer at the peripheral portion is smaller than the thickness of the semiconductor layer at the peripheral portion can be easily formed. Can be easily manufactured.

[Brief description of the drawings]

FIG. 1 shows an SOI MOSF according to an embodiment of the present invention.
It is sectional drawing which shows ET.

FIG. 2 shows an SOI MOSF according to an embodiment of the present invention;
It is a top view showing ET.

FIG. 3 is a sectional view taken along the line III-III in FIG. 2;

FIG. 4 is an SOI MOSF according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view for describing a first example of a method for manufacturing an ET.

FIG. 5 shows an SOI MOSF according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view for describing a first example of a method for manufacturing an ET.

FIG. 6 shows an SOI MOSF according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view for describing a first example of a method for manufacturing an ET.

FIG. 7 shows an SOI MOSF according to an embodiment of the present invention.
It is sectional drawing for demonstrating the 2nd example of the manufacturing method of ET.

FIG. 8 shows an SOI MOSF according to an embodiment of the present invention.
It is sectional drawing for demonstrating the 2nd example of the manufacturing method of ET.

FIG. 9 shows an SOI MOSF according to an embodiment of the present invention.
It is sectional drawing for demonstrating the 2nd example of the manufacturing method of ET.

FIG. 10 is an equivalent circuit diagram of a DTMOS.

FIG. 11 is a plan view of a DTMOS.

FIG. 12 is a sectional view taken along the line XII-XII in FIG. 11;

FIG. 13 is a sectional view showing a conventional SOI MOSFET.

FIG. 14 is a plan view showing a conventional SOI MOSFET.

FIG. 15 is a sectional view taken along the line XV-XV in FIG. 14;

[Explanation of symbols]

1 ... Si substrate, 2 ... element isolation oxide film, 2a ...
・ Overhang, 3 ・ ・ ・ Si active layer, 4 ・ ・ ・ Gate insulating film, 5 ・ ・ ・ Gate electrode, 7 ・ ・ ・ Source region, 8 ・
..Drain region, 11 ... mask, 12 ... oxygen injection layer

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) HK05 HM02 HM15 NN02 QQ11

Claims (14)

[Claims] In a semiconductor device having an SOI structure, in the SOI structure, an insulator partially protrudes toward a semiconductor layer, and a thickness of the semiconductor layer in a portion where the insulator protrudes is smaller than that of the semiconductor layer. A semiconductor device having a thickness smaller than a thickness of the semiconductor layer in a peripheral portion. 2. The semiconductor device according to claim 1, wherein a plurality of semiconductor layers constituting the SOI structure are provided separately from each other, and the insulator protrudes toward at least one of the semiconductor layers. The semiconductor device according to claim 1. 3. An MIS transistor is provided on the semiconductor layer, wherein the insulator at a portion immediately below a gate electrode of the MIS transistor extends toward the semiconductor layer, and a MIS transistor at a portion where the insulator overhangs. 2. The semiconductor device according to claim 1, wherein a thickness of the semiconductor layer is smaller than a thickness of the semiconductor layer in a source region and a drain region of the MIS transistor. 4. An MIS transistor is provided in the semiconductor layer, and the insulator at a portion immediately below a gate electrode of the MIS transistor extends toward the semiconductor layer, and a MIS transistor at a portion where the insulator overhangs. 3. The semiconductor device according to claim 2, wherein a thickness of the semiconductor layer is smaller than a thickness of the semiconductor layer in a source region and a drain region of the MIS transistor. 5. A full depletion type MIS transistor is provided on the semiconductor layer on which the insulator extends, and a partial depletion type MIS transistor is provided on the semiconductor layer on which the insulator does not extend. 3. The semiconductor device according to claim 2, wherein: 6. The semiconductor device according to claim 3, wherein the thickness of the semiconductor layer at a portion where the insulator protrudes changes in a channel width direction of the MIS transistor. 7. The semiconductor device according to claim 6, wherein said MIS transistor has a full depletion type MIS transistor part and a partial depletion type MIS transistor part. 8. The semiconductor device according to claim 1, wherein said semiconductor layer is a Si active layer. 9. The semiconductor device according to claim 3, wherein upper portions of said source region and said drain region are silicided. 10. An SOI structure in which an insulator partially extends to the semiconductor layer side, and a thickness of the semiconductor layer at a portion where the insulator extends is set to a peripheral portion thereof. A method of manufacturing a semiconductor device having a thickness smaller than the thickness of the semiconductor layer, wherein a step of forming an SOI substrate and partially converting the semiconductor layer in the vicinity of the interface between the insulator and the semiconductor layer in the SOI substrate into an insulator And a method of manufacturing a semiconductor device. 11. An ion implantation of oxygen into the semiconductor layer in the vicinity of an interface between an insulator and a semiconductor layer in the SOI substrate, and then performing a heat treatment on a portion of the semiconductor in which the oxygen is ion implanted. 11. The method according to claim 10, wherein the layer is oxidized to partially insulate the semiconductor layer. 12. The method of manufacturing a semiconductor device according to claim 11, wherein a mask having an opening at a predetermined portion is formed on the SOI substrate, and the oxygen is ion-implanted using the mask. 13. A mask in which a gate electrode formation site is opened is formed on the SOI substrate, the oxygen is ion-implanted using the mask, the mask is removed, and a gate insulating film is formed on the semiconductor layer. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the gate electrode is formed through the gate. 14. A mask having a gate electrode formation site opened on the SOI substrate, the oxygen is ion-implanted using the mask, and a gate electrode is formed in the opening of the mask via a gate insulating film. The method according to claim 11, wherein the mask is removed after the formation.