KR100192470B1 - Structure of cmos inverter and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims abstract 4
- 238000000151 deposition Methods 0.000 claims abstract 4
- 238000005530 etching Methods 0.000 claims abstract 2
- 239000002184 metal Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 13
- 239000012535 impurity Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
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Abstract
본 발명은 종래의 CMOS에 있어서, 웰 형성을 위해 넓은 면적이 필요했던 단점을 보완하고 게이트를 공유하게하여, 집적도를 향상시킬 수 있는 CMOS 인버터 구조 및 제조방법에 관한 것으로, 제1도전형의 기판에 제1도전형과 반대되는 제2도전형의 모스트랜지스터를 형성하고, 그 위에 게이트를 공유하고 제2도전형 모스트랜지스터의 소오스/드레인과 연결된 제1도전형의 소오스/드레인을 갖는 제1도전형의 모스트랜지스터가 형성된 CMOS 구조로써, 그 제조 방법은, 제1도전형의 기판위에 게이트를 형성하고 제1도전형과 반대되는 제2도전형의 소오스/드레인을 형성하여 제2도전형의 모스트랜지스터를 형성하는 공정과, 전표면에 격리용막을 증착하고 제2도전형 모스트랜지스터의 드레인 콘택홀을 형성하는 공정과,상기 드레인 콘택홀에 전도체층을 선택적으로 형성하여 평탄화하고 상기 게이트 표면까지 에치백하는 공정과, 제1도전형의 모스트랜지스터 형성을 위한 게이트 산화막을 상기 전도체층 위를 제외한 부분에 형성하고 제2도전형으로 도핑된 폴리실리콘을 증착하는 공정과, 상기 중착된 폴리실리콘에 채널영역을 정의하여 제1도전형의 소오스드레인을 형성하여 제1도전형의 모스트랜지스터를 형성하는 공정으로 이루어진다.The present invention relates to a CMOS inverter structure and a manufacturing method which can improve the degree of integration by compensating for the disadvantage that a large area was required for forming a well in a conventional CMOS and sharing a gate. Forming a second transistor of the second conductivity type opposite to the first conductivity type, sharing a gate thereon, and having a source / drain of the first conductivity type connected to the source / drain of the second conductivity type MOS transistor; A CMOS structure in which a morph transistor of a type is formed, and a manufacturing method thereof includes forming a gate on a substrate of a first conductive type and forming a source / drain of a second conductive type opposite to the first conductive type to form a MOS of a second conductive type. Forming a transistor, depositing an isolation film on an entire surface, and forming a drain contact hole of a second conductive MOS transistor, and selectively forming a conductor layer in the drain contact hole. Forming, planarizing, and etching back to the gate surface; forming a gate oxide film for forming a first transistor type MOS transistor on portions other than the conductive layer, and depositing polysilicon doped with a second conductive type. And defining a channel region in the deposited polysilicon to form a source drain of the first conductivity type to form a first transistor type MOS transistor.
Description
제1도는 종래의 CMOS 인버터 구조 단면도.1 is a cross-sectional view of a conventional CMOS inverter structure.
제2도는 종래의 NMOS 인버터 구조 단면도.2 is a cross-sectional view of a conventional NMOS inverter structure.
제3도는 인버터 회로 구성도.3 is a schematic diagram of an inverter circuit.
제4도는 본 발명의 CMOS인버터 제조공정 단면도.4 is a cross-sectional view of a manufacturing process of the CMOS inverter of the present invention.
제5도는 본 발명의 CMOS인버터 완성단면도.5 is a cross-sectional view of a CMOS inverter of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 필드산화막1: silicon substrate 2: field oxide film
5, 12 : 소오스/드레인 9 : 실리사이드5, 12: source / drain 9: silicide
10 : 도핑된 폴리실리콘 7, 13 : 산화막10: doped polysilicon 7, 13: oxide film
14 : 금속14: metal
본 발명은 반도체 소자에 관한 것으로 특히 엔모스(NMOS)와 피모스(PMOS)트랜지스터가 게이트를 공유한 구조의 CMOS 인버터 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a CMOS inverter structure and a manufacturing method having a structure in which a NMOS and a PMOS transistor share a gate.
종래의 CMOS 구조 및 제조방법을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.The conventional CMOS structure and manufacturing method will be described in detail with reference to the accompanying drawings.
제1도는 종래의 CMOS 인버터 구조 단면도로서, CMOS 인버터는 한 개의 엔모스 트랜지스터와 한 개의 피모스 트랜지스터를 금속으로 연결한 것으로, 실리콘기판(1)에 필드산화막(2)을 성장하여 액티브영역과 필드영역을 구분하고, 액티브영역중 피모스영역에 n형 웰(2)을 형성하고, 게이트산화막을 성장하여 폴리사이드(Polycide)를 증착식각하여 엔모스와 피모스 각각의 게이트(6)를 형성하고, n+이온주입으로 엔모스영역의 소오스/드레인과 P+이온주입으로 피모스 영역의 소오스/드레인을 형성하고, 워드라인의 격리를 위해 산화막(7)을 증착하고 베리드 콘택형성을 위해 산화막(7)을 선택식각하여 금속(8)을 증착하여 이루어진 구조이다.1 is a cross-sectional view of a conventional CMOS inverter structure, in which a CMOS inverter is formed by connecting one NMOS transistor and one PMOS transistor with a metal, and growing a field oxide film 2 on the silicon substrate 1 to form an active region and a field. N-type wells 2 are formed in the PMOS region of the active region, a gate oxide film is grown, and polycide is deposited and etched to form gates 6 of NMOS and PMOS, respectively. source / drain of the NMOS region by n + ion implantation and source / drain of the PMOS region by P + ion implantation, and an oxide film 7 is deposited for isolation of a word line, and an oxide layer is formed to form a buried contact. 7) is selectively etched to deposit a metal (8).
제2도는 제1도중 엔모스 영역을 나타낸 것으로, 하나의 엔모스 트랜지스터와 폴리저항(LOAD POLY) 및 금속라인으로 구성된 것이다.FIG. 2 shows the NMOS region in FIG. 1, which is composed of one NMOS transistor, a load resistor, and a metal line.
이와 같이 구성된 종래의 CMOS 인버터의 동작은 다음과 같다.The operation of the conventional CMOS inverter configured as described above is as follows.
제3도는 인버터회로 구성도로써, 제3도(a)는 엔모스 인버터 회로도이고, 제3도(b)는 CMOS 인버터회로도이다.3 is an inverter circuit configuration diagram. FIG. 3 (a) is an NMOS inverter circuit diagram and FIG. 3 (b) is a CMOS inverter circuit diagram.
즉 제3도(a)에서 입력신호가 하이레벨일때 엔모스가 "온"되어 출력신호는 로우레벨이 되고, 입력시호가 로우레벨일때 엔모스는 오프되어 출력신호는 하이레벨이 된다. 그리고 제3도(b)에서 입력신호가 하이레벨일 경우, 피모스는 "오프"되고 엔모스는 "온"되어 출력신호는 로우레벨이되고, 입력신호가 로우레벨일 경우 피모스는 "온"되고, 엔모스는 "오프"되어 출력신호는 하이레벨이 된다.That is, in FIG. 3A, when the input signal is high level, the NMOS is "on" and the output signal becomes low level. When the input signal is low level, the NMOS is turned off and the output signal becomes high level. In FIG. 3 (b), when the input signal is high level, the PMOS is "off" and the NMOS is "on" so that the output signal is low level, and when the input signal is low level, the PMOS is "on". And the NMOS are " off " so that the output signal becomes high level.
그러나, 종래의 CMOS 인버터에 있어서, 피모스 트랜지스터를 형성하기 위해서는 n형 웰을 형성하여야 했기 때문에 매우 큰 면적을 차지하여 집적화에 어려운 결점이 있다.However, in the conventional CMOS inverter, since an n-type well has to be formed in order to form a PMOS transistor, it takes up a very large area and has a disadvantage in that it is difficult to integrate.
본 발명은 이와 같은 결점을 해결하기 위해 안출한 것으로서, 박막의 엔모스와 피모스를 형성하고 게이트를 고유하도록 하는 CMOS를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such drawbacks, and an object thereof is to provide a CMOS for forming an NMOS and a PMOS of a thin film and making a gate unique.
이와 같은 목적을 달성하기위한 본 발명은 기판에 피모스를 박막트랜지스터(Thin Film Transisitor)를 형성하고, 이를 격리시킨 뒤 그 위에 게이트가 공유되도록 엔모스트랜지스터를 형성하는 구조 및 제조방법이다.The present invention for achieving the above object is a structure and manufacturing method for forming a PMOS in a thin film transistor (Thin Film Transisitor) on the substrate, isolating it and then forming an enmos transistor to share a gate thereon.
이와 같은 본 발명을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.When described in more detail with reference to the accompanying drawings, the present invention as follows.
제4도는 본 발명의 CMOS 인버터 제조공정 단면도를 낱낸 것으로, 제4도(a)와 같이 실리콘기판(1)에 필드산화막(2)을 성장하여 액티브영역과 필드영역을 구분하고, 게이트 산화막을 성장한 후 n형 불순물로 도핑된 폴리실리콘과 캡게이트 산화막을 차례로 증착하여 포토에치공정으로 게이트(6)를 형성하고, LDD(Lighly doped drain) 구조의 소오스/드레인을 형성하기위해 n-불순물 이온주입한 뒤 게이트(6)에 측벽산화막을 형성하여 n+불순물이온 주입을 한다.4 is a cross-sectional view of a manufacturing process of a CMOS inverter of the present invention. As shown in FIG. 4A, a field oxide film 2 is grown on a silicon substrate 1 to distinguish an active region from a field region, and a gate oxide film is grown. Next, polysilicon doped with n-type impurity and a capgate oxide layer are sequentially deposited to form a gate 6 by a photoetch process, and n - impurity ion implantation is performed to form a source / drain of LDD (Lighly doped drain) structure. After that, a sidewall oxide film is formed on the gate 6 to inject n + impurity ions.
제4도(b)와 같이 낮은 온도에서 전표면에 격리용 산화막(7)을 증착하고 포토에치공정으로 엔모스 트랜지스터의 드레인 콘택홀(Contact hole)을 형성하여 콘택홀내에 선택적인 화학증착법으로 실리사이드(Silicide)(9)를 증착한다.As shown in FIG. 4 (b), the isolation oxide film 7 is deposited on the entire surface at a low temperature, and a drain contact hole of the NMOS transistor is formed by a photoetch process. Silicide 9 is deposited.
제4도(C)와 같이 평탄화를 위하여 Chemical-Mechanical-Polishing으로 표면을 평탄화시킨후 게이트(6) 표면까지 에치백하고, 박막산화막을 성장시켜 피모스 트랜지스터의 게이트산화막을 형성한 다음 실리사이드(9)위의 산화막을 선택적 습식식각하고 n형 불순물로 도핑된 폴리실리콘(10)을 중착한다.As shown in FIG. 4 (C), the surface is planarized by chemical mechanical polishing to etch back to the surface of the gate 6, the thin film oxide is grown to form a gate oxide of the PMOS transistor, and the silicide (9). The wet oxide film is selectively wet etched and the polysilicon 10 doped with n-type impurities is deposited.
제4도(d)와 같이 , 포토레지스트(11)를 도포하여 피모스의 채널부분을 마스킹한 뒤 보론(Boron)을 고농도로 이온주입하고 제4도(e)와 같이 불필요한 부분을 제거하여 피모스의 트랜지스터의 소오스/드레인을 형성한다.As shown in FIG. 4 (d), the photoresist 11 is applied to mask the channel portion of the PMOS, and ion implanted at high concentration in boron, and unnecessary portions are removed as shown in FIG. The source / drain of the transistor of MOS is formed.
그 뒤, 산화막(13)을 두껍게 중착하고 콘택을 형성하여 금속전극(14)을 연결한다.Thereafter, the oxide film 13 is thickly thickened to form a contact to connect the metal electrode 14.
이와 같은 방법으로 제조하여 완성된 CMOS의 구조는 제5도와 같다.The structure of the CMOS fabricated and completed in this manner is shown in FIG.
즉, 기판(1)에 필드산화막(2)이 형성되고 액티브영역에 게이트(6)와 n형 소오스/드레인(5)이 형성되어 엔모스 트랜지스터가 형성되고, 그 위에 게이트 산화막을 사이에 두고 상기 게이트(6)를 공통으로하여 P형 소오스/드레인(12)이 형성되어 피모스 트랜지스터가 형성되고 피모스 트랜지스터와 엔모스 트랜지스터의 소오스/드레인 (5,12)은 실리사이드(9)로 연결되고 전극이 형성되어 있는 구조이다.That is, the field oxide film 2 is formed on the substrate 1, the gate 6 and the n-type source / drain 5 are formed in the active region to form an NMOS transistor, and the gate oxide film is interposed therebetween. P-type source / drain 12 is formed with the gate 6 in common to form a PMOS transistor, and the source / drain (5, 12) of the PMOS transistor and the NMOS transistor are connected by silicide 9 and the electrode This is a structure formed.
이상에서 설명한 바와 같이 본 발명의 CMOS 인버터 구조 및 제조방법에 있어서는 종래의 CMOS 구조에서 웰형성을 위해 넓은 면적이 필요했던 단점을 보완하고, 엔모스와 피모스 트랜지스터가 게이트를 고유하게하여 면적을 최소화하여 집적도를 향상시킬 수 있고, 소자표면의 평편도를 증가시킬 수 있는 효과등이 있다.As described above, the CMOS inverter structure and manufacturing method of the present invention compensate for the disadvantage that a large area was required for well formation in the conventional CMOS structure, and the NMOS and PMOS transistors make the gate unique to minimize the area. Therefore, the degree of integration can be improved, and the flatness of the device surface can be increased.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10593770B2 (en) | 2017-06-16 | 2020-03-17 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same |
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1991
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10593770B2 (en) | 2017-06-16 | 2020-03-17 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same |
| US10910477B2 (en) | 2017-06-16 | 2021-02-02 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same |
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| Publication number | Publication date |
|---|---|
| KR930011311A (en) | 1993-06-24 |
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