JPS583395B2 - Temperature-sensitive semiconductor device - Google Patents

Temperature-sensitive semiconductor device

Info

Publication number
JPS583395B2
JPS583395B2 JP51081195A JP8119576A JPS583395B2 JP S583395 B2 JPS583395 B2 JP S583395B2 JP 51081195 A JP51081195 A JP 51081195A JP 8119576 A JP8119576 A JP 8119576A JP S583395 B2 JPS583395 B2 JP S583395B2
Authority
JP
Japan
Prior art keywords
region
temperature
semiconductor device
junction
sensitive semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51081195A
Other languages
Japanese (ja)
Other versions
JPS536589A (en
Inventor
山中憲一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP51081195A priority Critical patent/JPS583395B2/en
Publication of JPS536589A publication Critical patent/JPS536589A/en
Publication of JPS583395B2 publication Critical patent/JPS583395B2/en
Expired legal-status Critical Current

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  • Thyristors (AREA)

Description

【発明の詳細な説明】 この発明は、感温半導体素子に係り、熱感度特性を向上
させた感温半導体素子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a temperature-sensitive semiconductor device, and more particularly to a temperature-sensitive semiconductor device with improved thermal sensitivity characteristics.

第1図a、bは、サイリスタ構造を有する従来の感温半
導体素子の模式的な縦断面図であり第2図aは縦形構造
のもの、第2図bは横形構造のものを表わす。
1A and 1B are schematic vertical cross-sectional views of a conventional temperature-sensitive semiconductor device having a thyristor structure, FIG. 2A shows a vertical structure, and FIG. 2B shows a horizontal structure.

図において、1はNエミツタ領域、2ぱPベース領域、
3はNベース領域、4はPエミツタ領域、5は上記の四
つの領域が形成されているシリコン基体、6はNエミツ
タ領域2との間の第1のPN接合、7はPベース領域2
とNべース領域3との間の第2のPN接合、8はシリコ
ン酸化膜などよりなる絶縁保護膜、9は蒸着金属膜など
よりなる電極である。
In the figure, 1 is an N emitter region, 2 is a P base region,
3 is an N base region, 4 is a P emitter region, 5 is a silicon substrate in which the above four regions are formed, 6 is a first PN junction with the N emitter region 2, and 7 is a P base region 2
8 is an insulating protective film made of a silicon oxide film or the like, and 9 is an electrode made of a vapor-deposited metal film or the like.

第1図a,bに示す構造を有する感温半導体素子は、N
エミツタ領域1,Pベース領域2およびNベース領域3
からなるNPNトランジスタのベース接地電流増幅率α
1、Pエミツタ領域4、Nベース領域3およびPベース
領域2からなるPNPトランジスタのベース接地電流増
幅率α2、ならびに第2のPN接合7の漏洩電流Ioの
熱による変化特性を利用して、ある温度でオフ状態から
オン状態にスイッチングさせている。
The temperature-sensitive semiconductor device having the structure shown in FIGS. 1a and 1b has an N
Emitter region 1, P base region 2 and N base region 3
The common base current amplification factor α of the NPN transistor consisting of
1. Utilizing the thermal change characteristics of the common base current amplification factor α2 of the PNP transistor consisting of the P emitter region 4, the N base region 3, and the P base region 2, and the leakage current Io of the second PN junction 7, It is switched from the off state to the on state depending on the temperature.

従って、感温半導体素子の熱感度特性を向上させるため
には、α1、α2およびIoの熱感度を大きくすればよ
い。
Therefore, in order to improve the thermal sensitivity characteristics of the temperature-sensitive semiconductor element, it is sufficient to increase the thermal sensitivities of α1, α2, and Io.

このうち、漏洩電流Ioの熱感度を大きくするには、P
ベース領域2およびNベース領域3の多数キャリア濃度
を下げるか、または第2のPN接合7の領域に深い準位
を作り、発生再結合(generation−reco
mbination)電流を生じさせるような方法が考
へられる。
Among these, in order to increase the thermal sensitivity of leakage current Io, P
By lowering the majority carrier concentration in the base region 2 and N base region 3 or by creating a deep level in the region of the second PN junction 7, generation-recombination
A method of generating a current (mbination) can be considered.

また、第1のPN接合6の面積と第2のPN接合7の面
積との比を大きくとって、第1のPN接合6の電流密度
を大きくすることによっても熱感度を大きくする効果が
期待できる。
Furthermore, increasing the current density of the first PN junction 6 by increasing the ratio of the area of the first PN junction 6 to the area of the second PN junction 7 is also expected to have the effect of increasing thermal sensitivity. can.

しかるに、拡散による従来の方法では、第2のPN接合
7の領域のみに深い準位を作るのは非常に困難であり、
まだ、第1のPN接合6の面積と第2のPN接合7との
比を大きくすれば、チップの大きさに対する感温半導体
素子に流せる許容電流の割合が小さくなる。
However, with the conventional method of diffusion, it is extremely difficult to create a deep level only in the second PN junction 7 region.
However, if the ratio of the area of the first PN junction 6 to the second PN junction 7 is increased, the ratio of the allowable current that can flow through the temperature-sensitive semiconductor element to the size of the chip becomes smaller.

この発明は、上記の点に鑑みてなされたもので、熱感度
特性を向上させた感温半導体素子を提供することを目的
としたものである。
The present invention has been made in view of the above points, and an object of the present invention is to provide a temperature-sensitive semiconductor element with improved thermal sensitivity characteristics.

以下、実施例によりこの発明を説明する。The present invention will be explained below with reference to Examples.

第2図a,bはこの発明の実施例である感温半導体素子
の模式的な縦断端面図であり、第2図aぱ縦形構造のも
の、第2図bは横形構造のものを表わす。
FIGS. 2a and 2b are schematic longitudinal sectional views of a temperature-sensitive semiconductor device according to an embodiment of the present invention, with FIG. 2a showing a vertical structure and FIG. 2B showing a horizontal structure.

図において、10は第2のPN接合7が半導体基体5の
表面に露出する部分の近傍に、イオン注入領域である。
In the figure, reference numeral 10 denotes an ion implantation region near the portion where the second PN junction 7 is exposed on the surface of the semiconductor substrate 5.

プロトンはシリコンウエハ中に高エネルギーで打ち込ま
れると、それが静止する附近に欠陥を生成する。
When protons are implanted with high energy into a silicon wafer, they create defects near where they come to rest.

この欠陥は通常、発生再結合中心として作用する。This defect normally acts as a generative recombination center.

プロトンを逆方向バイアスを加えた第2のPN接合7の
領域に注入することによって、漏洩電流Ioの熱感度を
増大させることができる。
By injecting protons into the reverse biased region of the second PN junction 7, the thermal sensitivity of the leakage current Io can be increased.

次に、上記の実施例の製造方法の概略を説明する。Next, the outline of the manufacturing method of the above embodiment will be explained.

通常のサイリスタの製造工程と同様の製造工程に従って
、シリコン基板にNエミッタ領域1、Pベース領域2、
Nベース領域3およびPエミッタ領域4を形成する。
According to a manufacturing process similar to that of a normal thyristor, an N emitter region 1, a P base region 2,
An N base region 3 and a P emitter region 4 are formed.

次に、上記の領域の形成時に形成されているシリコン基
板の表面の酸化膜のうち、第20PN接合7がシリコン
基板5の表面に露出する箇所を被覆している部分をエッ
チングにて数千Å程度にする〔この部分の酸化膜をすべ
て除去した後、改めて数千Åの酸化膜を形成してもよい
Next, out of the oxide film on the surface of the silicon substrate formed when forming the above region, a portion covering the part where the 20th PN junction 7 is exposed on the surface of the silicon substrate 5 is etched by several thousand Å. [After removing all the oxide film in this part, another oxide film with a thickness of several thousand Å may be formed.

〕。上記のエッチングにマスクとして使用したホトレジ
スト膜をプロトン遮蔽マスクとして用いて、プロトンを
イオン注入法により注入する。
]. Using the photoresist film used as a mask in the above etching as a proton shielding mask, protons are implanted by ion implantation.

その後、約480℃でリンガラス膜を作成し、その上に
シリコン酸化膜をCVD法で成長させて絶縁保護膜8を
形成する。
Thereafter, a phosphorus glass film is formed at about 480° C., and a silicon oxide film is grown thereon by the CVD method to form an insulating protective film 8.

つづいて、通常の方法で電極9を形成する。Subsequently, the electrode 9 is formed by a normal method.

プロトンは金などの重金属に比べて、イオン注入が容易
で、重金属のような高温での活性化が不必要である。
Compared to heavy metals such as gold, protons are easier to ion-implant, and unlike heavy metals, activation at high temperatures is unnecessary.

また、プロトンは静止領域においてのみ欠陥を作り出す
ので、ウエハの表面に欠陥が生じることが少ない。
Furthermore, since protons create defects only in the stationary region, defects are less likely to occur on the surface of the wafer.

以上詳述したように、この発明による感温半導体素子に
おいては、Pベース領域とNベース領域とにより形成さ
れるPN接合が半導体基体の表面に露出する部分にイオ
ン注入領域を設けたので、このイオン注入領域に深い準
位が形成され、上記PN接合の漏洩電流が増加するため
、熱感度特性を向上させることができる効果がある。
As detailed above, in the temperature-sensitive semiconductor device according to the present invention, the ion implantation region is provided in the part where the PN junction formed by the P base region and the N base region is exposed on the surface of the semiconductor substrate. Since a deep level is formed in the ion implantation region and the leakage current of the PN junction increases, the thermal sensitivity characteristics can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは従来の感温半導体素子の模式的な縦断端
面図、第2図a,bはこの発明の実施例である感温半導
体素子の模式的な縦断端面図である。 図において、1はエミッタ領域、2はPベース領域、3
ぱNベース領域、4はPエミッタ領域、5は半導体基体
、6は第1のPN接合、7は第2のPN接合、10はイ
オン注入領域である。 なお、図中同一符号はそれぞれ同一または相当部分を示
す。
1A and 1B are schematic longitudinal sectional views of a conventional temperature-sensitive semiconductor device, and FIGS. 2A and 2B are schematic longitudinal sectional views of a temperature-sensitive semiconductor device according to an embodiment of the present invention. In the figure, 1 is the emitter region, 2 is the P base region, and 3 is the emitter region.
4 is a P emitter region, 5 is a semiconductor substrate, 6 is a first PN junction, 7 is a second PN junction, and 10 is an ion implantation region. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 1 サイリスタ構造のNエミツタ領域、Pベース領域、
Nベース領域およびPエミツタ領域が形成されている半
導体基体、ならびに上記Pベース領域と上記Nベース領
域とにより形成されるPN接合が上記半導体基体の表面
に露出する部分の上記半導体基体に形成されたイオン注
入領域を備えた感温半導体素子。 2 イオン注入領域がプロトンをイオン注入することに
より形成されたことを特徴とする特許請求の範囲第1項
記載の感温半導体素子。
[Claims] 1. N emitter region, P base region of thyristor structure,
A semiconductor substrate in which an N base region and a P emitter region are formed, and a PN junction formed by the P base region and the N base region are formed in a portion of the semiconductor substrate exposed to the surface of the semiconductor substrate. A temperature-sensitive semiconductor device with an ion-implanted region. 2. The temperature-sensitive semiconductor device according to claim 1, wherein the ion-implanted region is formed by ion-implanting protons.
JP51081195A 1976-07-07 1976-07-07 Temperature-sensitive semiconductor device Expired JPS583395B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51081195A JPS583395B2 (en) 1976-07-07 1976-07-07 Temperature-sensitive semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51081195A JPS583395B2 (en) 1976-07-07 1976-07-07 Temperature-sensitive semiconductor device

Publications (2)

Publication Number Publication Date
JPS536589A JPS536589A (en) 1978-01-21
JPS583395B2 true JPS583395B2 (en) 1983-01-21

Family

ID=13739685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51081195A Expired JPS583395B2 (en) 1976-07-07 1976-07-07 Temperature-sensitive semiconductor device

Country Status (1)

Country Link
JP (1) JPS583395B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5365363U (en) * 1976-11-05 1978-06-01

Also Published As

Publication number Publication date
JPS536589A (en) 1978-01-21

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