DE102016124670B4 - Thyristor with a semiconductor body - Google Patents

Abstract

Thyristor with a semiconductor body (2) which has a first semiconductor body main side (3), a second semiconductor body main side (4) arranged opposite the first semiconductor body main side (3) and a first and second semiconductor body main side (3, 4) which runs around the semiconductor body (2). connecting semiconductor body edge (28), the semiconductor body (2) having a first semiconductor zone (5) of a first conductivity type, an area of an outer side (10) of the first semiconductor zone (5) having a first surface (11) of the first semiconductor body main side (3) The semiconductor body (2) has a second semiconductor zone which is in contact with an inner side (13) of the first semiconductor zone (5) which is arranged opposite the outside (10) of the first semiconductor zone (5) and extends to the edge of the semiconductor body (28) (6) of a second conductivity type, the semiconductor body (2) having a second semiconductor zone (6) has a third semiconductor zone (7) of the first conductivity type and a fourth semiconductor zone (8) of the second conductivity type in the third semiconductor zone (7), the semiconductor body (2) having a, in a semiconductor body edge region (25), on the second semiconductor zone (6 ) arranged fifth semiconductor zone (9) of the second conductivity type, the first outer surface (14) of which faces away from the first semiconductor body main side (3) forms a region of the second semiconductor body main side (4), the fifth semiconductor zone (9) running parallel to the semiconductor body edge (28) , wherein the doping concentrations of the fourth and fifth semiconductor zones (8,9) are higher than those of the second semiconductor zone (6), the semiconductor body (2) starting from a first surface (16) of the second semiconductor body main side (4) parallel to the Semiconductor body edge (28) extending and extending into the second semiconductor zone (6), first recess (15), the semiconductor body (2) in the area (26) of the first recess (15) having a first and a second step (20, 20 '), each of which has a concave bottom surface, the area (26 ) of the first recess (15) arranged first stage (20) does not run within the second semiconductor zone (6) and the second stage (20 ') arranged in the region (26) of the first recess (15) within the second and third semiconductor zones (6 , 7) runs.

Description

The invention relates to a thyristor with a semiconductor body.

In particular in the case of a MESA-shaped thyristor, there is often the need to protect an edge region of the semiconductor body which runs around the active region of the semiconductor body of the thyristor, since dirt particles arranged on the edge region of the semiconductor body have a negative effect on the electrical properties of the thyristor.

From the DE 100 44 960 A1 it is known to arrange a passivation layer on the surface of the edge region of a semiconductor body, which protects the edge region against contamination and mechanical influences. Due to the presence of electrical charges, an electrically conductive so-called inversion channel running along the edge of the semiconductor body can be formed, which leads to an electrically conductive connection between the doped semiconductor zones of the semiconductor body arranged on both main sides of the semiconductor body.

From the US 3,961,354 A is known a mesa thyristor with a silicon substrate of a first predetermined conductivity type, with two surface diffusion layers of opposite conductivity type, with further selected diffusion areas in these surface diffusion layers of the same conductivity type as the silicon substrate, with electrodes assigned to predetermined parts of these diffusion areas and with mesa-etched peripheral surfaces.

From the US 3,628,106 A is known a semiconductor body with a first zone adjoining a main surface of the semiconductor body, which has a central region and an edge region which extends to a further main surface of the semiconductor body.

Out EP 0 044 048 A1 A method for producing a semiconductor component provided with a glass passivation is known, in which trenches are formed in the semiconductor component which are provided with a coating made of glass.

From the US 3 197 681 A A transistor is known which has a semiconductor body with a flat base region arranged near a main surface of the semiconductor body.

From the US 4,298,881 A is known a semiconductor device with a semiconductor substrate, which has a first and a second main surface and at least first, second and third semiconductor layers, the conductivity types of which alternate between the first and second main surface.

From the DE 26 10 828 C2 A thyristor with at least four successive regions of alternately opposite conductivity types, which are arranged in a semiconductor body of the thyristor between a first and a second main surface of the semiconductor body, is known.

It is an object of the invention to provide a thyristor with a semiconductor body in which the formation of an electrically conductive inversion channel, which leads to an electrically conductive connection between the doped semiconductor zones of the semiconductor body arranged on both main sides of the semiconductor body, is prevented or at least reduced.

This object is achieved by a thyristor having a semiconductor body which has a first semiconductor body main side, a second semiconductor body main side arranged opposite the first semiconductor body main side and a semiconductor body edge which runs around the semiconductor body and connects the first and second semiconductor body main sides, the semiconductor body having a first semiconductor zone of a first conductivity type , wherein a region of an outside of the first semiconductor zone forms a first surface of the first semiconductor body main side, the semiconductor body forming a second semiconductor zone of a second conductivity type which is in contact with an inside of the first semiconductor zone which is arranged opposite the outside of the first semiconductor zone and extends to the edge of the semiconductor body The semiconductor body has a third semiconductor zone of the first conductivity type arranged on the second semiconductor zone s and has a fourth semiconductor zone of the second conductivity type arranged in the third semiconductor zone, the semiconductor body having a fifth semiconductor zone of the second conductivity type arranged in a semiconductor body edge region on the second semiconductor zone, the first outer surface of which faces away from the first semiconductor body main side forms an area of the second semiconductor body main side , wherein the fifth semiconductor zone runs parallel to the edge of the semiconductor body, the doping concentrations of the fourth and fifth semiconductor zones being higher than those of the second semiconductor zone, the semiconductor body extending from the first surface of the second semiconductor body main side, parallel to the edge of the semiconductor body and into the second semiconductor zone extending into the first recess, the semiconductor body having a first and a second step in the region of the first recess, each of which has a concave v have running floor area, the im The first stage arranged in the region of the first recess does not run within the second semiconductor zone and the second stage arranged in the region of the first recess runs within the second and third semiconductor zones.

Advantageous embodiments of the invention result from the dependent claims.

It proves to be advantageous if at least sections of the first recess are arranged between the fourth semiconductor zone and the fifth semiconductor zone, at least in these sections the first recess does not extend to the edge of the semiconductor body, since then the formation of an electrically conductive inversion channel is very reliably prevented or at least is reduced.

It also proves to be advantageous if the first recess is arranged between the fourth semiconductor zone and the fifth semiconductor zone, the first recess not running as far as the edge of the semiconductor body and the fifth semiconductor zone running parallel to the entire edge of the semiconductor body without interruption. In this case, the fifth semiconductor zone runs closed around an inner region of the second semiconductor body main side. As a result, the formation of an electrically conductive inversion channel is very reliably prevented or at least reduced.

It also proves to be advantageous if the first recess is designed in such a way that the fifth semiconductor zone has an outer surface delimiting the first recess, since the formation of an electrically conductive inversion channel is then particularly reliably prevented or at least reduced.

Furthermore, it proves to be advantageous if the semiconductor body has a second recess that extends from the first surface of the first semiconductor body main side to the edge of the semiconductor body, runs parallel to the edge of the semiconductor body, and extends at least on the edge of the semiconductor body into the second semiconductor zone. This delays the formation of an inversion channel, which leads to an electrically conductive connection between the doped semiconductor zones of the semiconductor chip arranged on both main sides of the semiconductor body, since the distance over which the inversion channel must form is lengthened by the second recess. Furthermore, electrical field strengths occurring at the edge region of the semiconductor body during operation of the thyristor are thereby reduced.

In this context, it proves to be advantageous if an inner edge of the first recess is arranged closer to the center of the semiconductor body in a direction perpendicular to the normal direction of the first surface of the first semiconductor body main side than an inner edge of the second recess. As a result, the mechanical stability of the edge region of the semiconductor body is increased.

Furthermore, it proves to be advantageous if a first recess edge line, at which a boundary of the second to third semiconductor zone adjoins the first recess, is arranged closer to the center of the semiconductor body in the direction perpendicular to the normal direction of the first surface of the first semiconductor body main side than a second recess edge line, at which a boundary from the first to the second semiconductor zone adjoins the second recess. As a result, the mechanical stability of the edge region of the semiconductor body is increased.

Furthermore, it proves to be advantageous if the semiconductor body has a first and a second step in the region of the second recess, each of which has a concave bottom surface, the first step arranged in the region of the second recess running exclusively within the first semiconductor zone and which in the The second stage arranged in the region of the second recess runs within the first and second semiconductor zones, since electrical field strengths occurring at the edge region of the semiconductor body are then greatly reduced during operation of the thyristor.

It also proves to be advantageous if the first recess extends to the edge of the semiconductor body, the first recess being designed such that the fifth semiconductor zone has an outer surface delimiting the first recess, the outer surface delimiting the first recess through the first outer surface of the fifth semiconductor zone is formed, since electrical field strengths occurring at the edge region of the semiconductor body are then reduced during operation of the thyristor. The fifth semiconductor zone preferably runs without interruption parallel to the entire edge of the semiconductor body. In this case, the fifth semiconductor zone runs closed around an inner region of the second semiconductor body main side.

In this context, it proves to be advantageous if the first and second recesses are mirror-symmetrical with respect to a plane running parallel to the first surface of the first semiconductor body main side in the second semiconductor zone, since then, during operation of the thyristor, electrical field strengths occurring at the edge region of the semiconductor body are reduced become.

In the area of the first recess, the semiconductor body has a first and a second step, each of which has a concave shape Have floor area, wherein the first stage arranged in the region of the first recess does not run within the second semiconductor zone and the second stage arranged in the region of the first recess runs within the second and third semiconductor zones. As a result, electrical field strengths occurring at the first recess of the semiconductor body are greatly reduced during operation of the thyristor.

It also proves to be advantageous if the first recess starts from an outer surface of the third or fourth semiconductor zone. The first recess can start both from an outer surface of the third semiconductor zone and from an outer surface of the fourth semiconductor zone.

It also proves to be advantageous if the semiconductor body edge runs parallel to the normal direction of the first surface of the first semiconductor body main side, since the semiconductor body edge is then particularly simple.

Furthermore, it proves to be advantageous if the semiconductor body has the outer recesses delimiting the first recess, at least part of the outer surfaces of the semiconductor body delimiting the first recess being designed as the outer surface of a silicon oxide layer of the respective semiconductor zone or on at least part of the outer surfaces delimiting the first recess a silicon oxide layer is arranged on the semiconductor body.

In this context, it proves to be advantageous if a polyimide layer is arranged on the silicon oxide layer.

Furthermore, it proves to be advantageous if the semiconductor body has the first recess delimiting outer surfaces, a polyimide layer being arranged at least on part of the outer surface delimiting the first recess.

Furthermore, it proves to be advantageous if the semiconductor body has the outer recesses delimiting the second recess, at least some of the outer surfaces of the semiconductor body delimiting the second recess being designed as outer surfaces of a silicon oxide layer of the respective semiconductor zone or on at least part of the outer surfaces delimiting the second recess a silicon oxide layer is arranged on the semiconductor body.

In this context, it proves to be advantageous if a polyimide layer is arranged on the silicon oxide layer.

It has also proven to be advantageous if the semiconductor body has the second recess-defining outer surfaces, a polyimide layer being arranged at least on part of the outer surface of the semiconductor body delimiting the second recess.

By using a polyimide layer, possibly in cooperation with a silicon oxide layer instead of the glass passivation customary in thyristors, the blocking of the formation of an electrically conductive inversion channel running from the first semiconductor zone along the edge of the semiconductor body to the third semiconductor zone can be reinforced.

It should be generally noted at this point that the semiconductor zones of the first conductivity type are preferably designed as p-doped semiconductor zones (p-conductivity type) and the semiconductor zones of the second conductivity type are designed as n-doped semiconductor zones (n-conductivity type). Alternatively, the semiconductor zones of the first conduction type can be designed as n-doped semiconductor zones (n-conduction type) and the semiconductor zones of the second conduction type can be designed as p-doped semiconductor zones (p-conduction type).

• 1 eine Schnittansicht einer Ausbildung eines erfindungsgemäßen Thyristors,
• 2 eine Draufsicht von oben auf den in 1 dargestellten Thyristor,
• 3 eine Schnittansicht eines Halbleiterkörpers eines zweiten Leitungstyps nach einem ersten Verfahrensschritt a) zur Herstellung eines erfindungsgemäßen Thyristors,
• 4 eine Schnittansicht des Halbleiterkörpers nach dem Erzeugen einer ersten, zweiten und dritten Halbleiterzone entsprechend einem zweiten Verfahrensschritt b) zur Herstellung eines erfindungsgemäßen Thyristors,
• 5 eine Schnittansicht des Halbleiterkörpers nach dem Erzeugen einer vierten und fünften Halbleiterzone entsprechend einem dritten Verfahrensschritt c) zur Herstellung eines erfindungsgemäßen Thyristors,
• 6 eine Schnittansicht des Halbleiterkörpers nach dem Erzeugen einer ersten und zweiten Ausnehmung entsprechend einem vierten Verfahrensschritt d) zur Herstellung eines erfindungsgemäßen Thyristors,
• 7 eine Schnittansicht des Halbleiterkörpers und von auf dem Halbleiterkörper aufgebrachten Metallisierungen nach einem weiteren Verfahrensschritt zur Herstellung eines erfindungsgemäßen Thyristors und
• 8 eine Schnittansicht einer weiteren Ausbildung eines erfindungsgemäßen Thyristors.

Exemplary embodiments of the invention are explained below with reference to the figures below. Show:

• 1 2 shows a sectional view of an embodiment of a thyristor according to the invention,
• 2 a top view of the in 1 shown thyristor,
• 3 2 shows a sectional view of a semiconductor body of a second conductivity type after a first method step a) for producing a thyristor according to the invention,
• 4 3 shows a sectional view of the semiconductor body after the production of a first, second and third semiconductor zone in accordance with a second method step b) for producing a thyristor according to the invention,
• 5 2 shows a sectional view of the semiconductor body after the generation of a fourth and fifth semiconductor zone in accordance with a third method step c) for producing a thyristor according to the invention,
• 6 3 shows a sectional view of the semiconductor body after the production of a first and a second recess in accordance with a fourth method step d) for producing a thyristor according to the invention,
• 7 a sectional view of the semiconductor body and of metallizations applied to the semiconductor body according to another Method step for producing a thyristor according to the invention and
• 8th a sectional view of a further embodiment of a thyristor according to the invention.

It should be noted that the figures are schematic representations. Identical elements are provided with the same reference symbols in the figures.

In 1 is a sectional view of an embodiment of a thyristor according to the invention 1 and in 2 a top view of the thyristor 1 shown with the thyristor 1 in 2 across from 1 is shown reduced and the polyimide layer is not shown.

The thyristor according to the invention 1 has a semiconductor body 2 on the first semiconductor body main side 3 , one of the first semiconductor body main side 3 oppositely arranged second semiconductor body main side 4 and one around the semiconductor body 2 circumferential, the first and second semiconductor body main side 3 and 4 connecting semiconductor body edge 28 having. The semiconductor material of the semiconductor body 2 consists preferably of silicon or silicon carbide.

The semiconductor body 2 has a first semiconductor zone 5 of a first conduction type, with an area of an outside 10 the first semiconductor zone 5 a, preferably planar, first surface 11 the first semiconductor body main side 3 formed. The first area 11 the first semiconductor body main side 3 is in an indoor area 50 the first semiconductor body main side 3 arranged. Furthermore, the semiconductor body 2 one, with the outside 10 the first semiconductor zone 5 oppositely arranged inside 13 the first semiconductor zone 5 in contact and up to the edge of the semiconductor body 28 extending second semiconductor zone 6 of a second line type. Furthermore, the semiconductor body 5 one on the second semiconductor zone 6 arranged third semiconductor zone 7 of the first conductivity type and one in the third semiconductor zone 7 arranged fourth semiconductor zone 8th of the second line type. The fourth semiconductor zone 8th forms one in the third semiconductor zone 7 arranged tub from. The semiconductor body 2 also has one in a semiconductor body edge region 25 of the semiconductor body 2 , on the second semiconductor zone 6 arranged fifth semiconductor zone 9 of the second conductivity type, whose from the first semiconductor body main side 3 facing away from the first outer surface 14 an area of the second semiconductor body main side 4 formed.

The semiconductor body 2 has one of a, preferably planar, first surface 16 the second semiconductor body main side 4 outgoing, parallel to the edge of the semiconductor body 28 extending and into the second semiconductor zone 6 reaching first recess 15 on. The first area 16 the second semiconductor body main side 4 is in an indoor area 51 the second semiconductor body main side 4 arranged. The first recess 15 runs, preferably closed, around the interior 51 the second semiconductor body main side 4 around. The fifth semiconductor zone 9 can what in 2 is not shown, also closed around the interior 51 the second semiconductor body main side 4 run around.

As exemplified in 2 shown, runs the fifth semiconductor zone 9 parallel to the edge of the semiconductor body 28 , The fifth semiconductor zone 9 preferably extends to the edge of the semiconductor body 28 so that the fifth semiconductor zone 9 preferably a second outer surface 18 having a region of the semiconductor body edge 28 formed. Alternatively, the fifth semiconductor zone can, however, not shown in the figures 9 also in front of the edge of the semiconductor body 28 end so that the second semiconductor zone 6 one on the edge of the semiconductor body 28 arranged outer surface, which is a region of the second semiconductor body main side 4 trains, has. The fifth semiconductor zone 9 need not necessarily be in the form of a coherent zone, but can, as exemplified in 2 represented, for example by the production of the recess 15 conditionally, in the form of several separate fifth semiconductor sub-zones 9 ' available. The first recess 15 is preferably produced in such a way that appropriately designed, parallel to the semiconductor body edge 28 in 2 in the vertical and horizontal direction through the entire second semiconductor body main side 4 trenches running out of the semiconductor body 2 be etched out, the fifth semiconductor zone 9 cut. The fifth semiconductor zone 9 can what in 2 is not shown, also run without interruption parallel to the entire edge of the semiconductor body and thus also closed around an inner region 51 the second semiconductor body main side 4 run around.

In the invention, the in the semiconductor body edge region 25 arranged fifth semiconductor zone 9 in cooperation with the first recess 15 which is the fifth semiconductor zone 9 from the third semiconductor zone 7 separates, forming one from the first semiconductor zone 1 along the edge of the semiconductor body 28 to the third semiconductor zone 7 running electrically conductive inversion channel prevented or at least reduced.

The thyristor 1 points to the electrical connection on the first surface 11 the first semiconductor body main side 3 arranged first metallization 12 , one on the fourth semiconductor zone 8th arranged second metallization 53 and one on the third semiconductor zone 7 arranged third metallization 24 on. The first metallization 12 preferably forms an anode metallization, the second metallization 53 preferably forms a cathode metallization and the third metallization 24 preferably forms a gate metallization. It should be noted that the third metallization 24 not necessarily near the edge of the semiconductor body as shown in the figures 28 must be arranged, but for example with an appropriate design of the fourth semiconductor zone 8th also in the area of the center M of the semiconductor body 2 can be arranged.

In the context of the embodiment according to 1 and 2 are at least sections 15 ' (please refer 2 ) of the first recess 15 between the fourth semiconductor zone 8th and the fifth semiconductor zone 9 arranged, at least in these sections 15 ' the first recess 15 the first recess 15 not to the edge of the semiconductor body 28 runs. The first recess 15 is preferably designed such that the fifth semiconductor zone 9 a the first recess 15 delimiting outer surface 19 having. The first recess 17 delimiting outer surface 19 the fifth semiconductor zone 9 is the fourth semiconductor zone 8th facing. The first recess 17 delimiting outer surface 19 the fifth semiconductor zone 9 is in the context of the embodiment of the second outer surface 18 the fifth semiconductor zone 9 covering an area of the semiconductor body edge 28 trained, arranged opposite. It should be noted that the second semiconductor zone 6 also one up to the second semiconductor body main side 4 reaching between the recess 15 and the fifth semiconductor zone 9 arranged, may have area (not shown in the figures), so that the fifth semiconductor zone 9 not necessarily the first recess 15 delimiting outer surface 19 must have.

The semiconductor body 2 preferably has one, starting from the first surface 11 the first semiconductor body main side 3 to the edge of the semiconductor body 28 running, parallel to, preferably the entire, semiconductor body edge 28 extending and at least on the edge of the semiconductor body 28 down to the second semiconductor zone 6 reaching, second recess 17 on. The second recess 17 runs around the interior 50 the first semiconductor body main side 3 around. Through the second recess 17 is that in operation of the thyristor at the edge of the semiconductor body 28 occurring electrical field strength is reduced.

The inside edge B1 the first recess 15 is, as exemplified in 1 shown, preferably in the direction perpendicular to the normal direction N of the first surface 11 the first semiconductor body main side 3 closer to the center M of the semiconductor body 2 arranged as the inner edge B2 the second recess 17 ,

A first recess margin line S1 at the border G1 from second to third semiconductor zone 6 and 7 to the first recess 15 is preferably as exemplified in 1 shown in the direction perpendicular to the normal direction N of the first surface 11 the first semiconductor body main side 3 closer to the center M of the semiconductor body 2 arranged like a second recess edge line S2 on the one border G2 from first to second semiconductor zone 5 and 6 to the second recess 17 borders. The first and second recess margin lines S1 and S2 run, spaced from the center M of the semiconductor body 2 to the center M of the semiconductor body 2 around.

The semiconductor body 2 preferably points in the area 27 the second recess 17 a first and a second stage 21 and 21 ' on, each having a concave bottom surface, the in the area 27 the second recess 17 arranged first stage 21 only within the first semiconductor zone 5 runs and that in the area 27 the second recess 17 arranged second stage 21 ' within the first and second semiconductor zones 5 and 6 runs.

Furthermore, the semiconductor body 2 in the area 26 the first recess 15 a first and a second stage 20 and 20 ' on, each having a concave bottom surface, the in the area 26 the first recess 15 arranged first stage 20 not within the second semiconductor zone 6 runs and that in the area 26 the first recess 15 arranged second stage 20 ' within the second and third semiconductor zones 6 and 7 runs. The one in the area 26 the first recess 15 arranged first stage 20 as in the exemplary embodiment, preferably runs exclusively in the third semiconductor zone 7 , The first recess 15 in this case it is from a preferably planar outer surface 31 the third semiconductor zone 7 off, ie the inner edge B1 the first recess 15 borders on the outer surface 31 the third semiconductor zone 7 on. The first stage 20 can not only in the third semiconductor zone 7 but also in the fourth semiconductor zone 7 run. The first recess 15 in this case it is from a preferably planar outer surface 32 the fourth semiconductor zone 8th off, ie the inner edge B1 the first recess 15 borders on the outer surface 32 the fourth semiconductor zone 8th on.

The semiconductor body edge 28 preferably runs from the first to the second semiconductor body main side 3 . 4 parallel to the normal direction N the first area 11 the first semiconductor body main side 3 , The semiconductor body edge 28 can, however also obliquely from the first semiconductor body main side 3 to the second semiconductor body main side 4 run.

At least part of the first recess 15 delimiting outer surfaces 33 . 34 and if necessary 19 (the outer surface 19 is for example in the embodiment 8th not available) of the semiconductor body 2 , ie at least part of the outer surfaces of the semiconductor body 2 having an interface with the first recess 15 can each have as the outer surface of a silicon oxide layer 22 the respective semiconductor zone 6 . 7 respectively. 9 be formed, being on the silicon oxide layer 22 a polyimide layer 23 can be arranged. Alternatively, the first recess can be formed on at least part of the 15 delimiting outer surfaces 33 . 34 and if necessary 19 of the semiconductor body 2 also a polyimide layer 23 be arranged without the silicon oxide layer 22 is available. The complete areas of the first recess 15 delimiting outer surfaces 33 . 34 and if necessary 19 can be used as outer surfaces of a silicon oxide layer 22 of the semiconductor zones that interface with the first recess 15 have, be formed, on the silicon oxide layer 22 a polyimide layer 23 can be arranged. Alternatively, the first recess can be made on the entire surface 15 delimiting outer surfaces 33 . 34 and if necessary 19 also a polyimide layer 23 be arranged without the silicon oxide layer 22 is available.

Preferably the first outer surface 14 the fifth semiconductor zone 9 that an area of the second semiconductor body main side 4 forms, not as the outer surface of a silicon oxide layer of the fifth semiconductor zone 9 formed or covered by a polyimide layer. The normal direction of the first outer surface 14 the fifth semiconductor zone 9 preferably agrees with the normal direction N the first area 11 the first semiconductor body main side 3 match. Of course, as exemplified only in 8th shown, the first outer surface in all embodiments 14 the fifth semiconductor zone 9 that an area of the second semiconductor body main side 4 forms, as the outer surface of a silicon oxide layer 22 the fifth semiconductor zone 9 be formed and / or a polyimide layer 23 be covered.

At least part of the second recess 17 delimiting outer surfaces 35 and 36 of the semiconductor body 2 , ie at least part of the outer surfaces of the semiconductor body 2 having an interface with the second recess 17 can each have as the outer surface of a silicon oxide layer 29 the respective semiconductor zone 5 respectively. 6 be formed, being on the silicon oxide layer 29 a polyimide layer 30 can be arranged. Alternatively, the second recess can be formed on at least part of the 17 delimiting outer surfaces 35 and 36 of the semiconductor body 2 also a polyimide layer 30 be arranged without the silicon oxide layer 29 is available. The complete areas of the second recess 17 delimiting outer surfaces 35 and 36 can be used as outer surfaces of a silicon oxide layer 29 the semiconductor zones that interface with the second recess 17 have, be formed, on the silicon oxide layer 29 a polyimide layer 30 can be arranged. Alternatively, the second recess can be made on the entire surface 17 delimiting outer surfaces 35 and 36 also a polyimide layer 30 be arranged without the silicon oxide layer 29 is available.

The respective recess 15 respectively. 17 delimiting outer surfaces 33 . 34 and optionally 19 (see 1 ) and possibly 14 (see 8th ) and 35, 36 each form an outer surface of a respective semiconductor zone.

The polyimide layer and the silicon oxide layer which may be present serve as passivation layers. By using a polyimide layer as described above, possibly in cooperation with a silicon oxide layer instead of the glass passivation which is customary in thyristors, it is possible to block the formation of one of the first semiconductor zones 1 along the edge of the semiconductor body 28 to the third semiconductor zone 7 extending electrically conductive inversion channel.

The respective silicon oxide layer 22 respectively. 29 if the semiconductor material of the semiconductor body 2 consists of silicon or silicon carbide, in the exemplary embodiments by oxidation of the corresponding outer surface area of the semiconductor body 2 generated so that the respective silicon oxide layer in the exemplary embodiments 22 respectively. 29 Part of the semiconductor body 2 or the respective semiconductor zone, the outer surface of which was oxidized to produce the silicon oxide layer. It should be noted that, in the sense of the invention, a surface area of a semiconductor zone of the semiconductor body 2 layer produced by chemical reaction (eg oxidation) with the semiconductor zone, in particular electrically non-conductive layer, is part of the semiconductor zone in question. The silicon oxide of the respective silicon oxide layer can be present, for example, in the form of silicon monoxide or silicon dioxide or in the form of a mixture of silicon monoxide and silicon dioxide. If the semiconductor material of the semiconductor body 2 consists of silicon carbide, the respective silicon oxide layer can also have carbon.

The respective silicon oxide layer can also be produced by a coating process (e.g. Plasma coating) are generated by coating the respective semiconductor zone with a corresponding silicon oxide layer. In this case, the first recess is preferably on at least part of the 15 delimiting outer surfaces of the semiconductor body 2 and preferably on at least part of the second recess 17 delimiting outer surfaces of the semiconductor body 2 each arranged a silicon oxide layer, which is not shown in the figures. A respective polyimide layer can be arranged on the respective silicon oxide layer.

If a polyimide layer is arranged on the silicon oxide layer, then the polyimide layer has mechanical contact with the silicon oxide layer.

The first recess 15 delimiting outer surfaces 33 . 34 and optionally 19 (the outer surface 19 is for example in the embodiment 8th not available) of the semiconductor body 2 , ie the outer surfaces of the semiconductor body 2 having an interface with the first recess 15 are preferably not each formed as the outer surface of an electrically non-conductive layer, such as a silicon oxide layer. The outer surfaces of the semiconductor body 2 having an interface with the first recess 15 have in this case are electrically conductive. The second recess 17 delimiting outer surfaces 35 and 36 of the semiconductor body 2 , ie the outer surfaces of the semiconductor body 2 having an interface with the second recess 17 are preferably not each formed as the outer surface of an electrically non-conductive layer, such as a silicon oxide layer. The outer surfaces of the semiconductor body 2 having an interface with the second recess 17 have in this case are electrically conductive.

In all embodiments, the range 26 the first recess 15 the polyimide layer 23 also on no electrically non-conductive layer, in particular on no silicon oxide layer. In all embodiments, the range 27 the second recess 17 the polyimide layer 30 also on no electrically non-conductive layer, in particular on no silicon oxide layer.

The first and third semiconductor zone 5 and 7 can in the normal direction N of the first surface 11 the first semiconductor body main side 3 each have, for example, a thickness of 80 μm to 120 μm, in particular of 90 μm to 110 μm, the first and third semiconductor zones 5 and 7 can have a different thickness. The first and third semiconductor zones 5 and 7 are p-doped within the scope of the exemplary embodiments, the p-doping, for example, by diffusion of boron aluminum and / or gallium into the semiconductor material (for example silicon or silicon carbide) of the semiconductor body 2 may have arisen. The first and third semiconductor zones 5 and 7 can, for example, each have a doping concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ cm ^-3 , the first and third semiconductor zones 5 and 7 can have a different doping concentration. The second semiconductor zone 6 can be in the normal direction N of the first surface 11 the first semiconductor body main side 3 For example, have a thickness of 240 µm to 300 µm, in particular from 260 µm to 280 µm, and a doping concentration of 1 × 10 ¹³ cm ^-3 to 1 × 10 ¹⁴ cm ^-3 . The fourth and fifth semiconductor zones 8th and 9 can in the normal direction N of the first surface 11 the first semiconductor body main side 3 each have, for example, a thickness of 5 μm to 40 μm, in particular of 10 μm to 20 μm, the fourth and fifth semiconductor zones 8th and 9 can have a different thickness, but preferably have an identical thickness. The fourth and fifth semiconductor zones 8th and 9 can, for example, each have a doping concentration of 1 × 10 ²⁰ cm ^-3 to 1 × 10 ²¹ cm ^-3 , the fourth and fifth semiconductor zones 8th and 9 can have a different doping concentration, but preferably have an identical doping concentration. The doping concentrations of the fourth and fifth semiconductor zones 8th and 9 are higher than that of the second semiconductor zone 6 , so that in the figures or exemplary embodiments in which the fourth and fifth semiconductor zone 8th and 9 have an n-doping, the doping of the fourth and fifth semiconductor zones 8th and 9 with n + and the doping of the second semiconductor zone 6 are designated with n-. The second, fourth and fifth semiconductor zones n-doped within the scope of the exemplary embodiments 6 . 8th and 9 can, for example, by diffusion of phosphorus into the semiconductor material (eg silicon or silicon carbide) of the semiconductor body 2 have arisen. The depth T of the first recess 15 , with respect to the, preferably planar, first surface 16 the second semiconductor body main side 4 , is greater than the thickness of the third semiconductor zone 7 and can be, for example, 121 µm to 150 µm, in particular, for example, 135 µm. It should also be generally noted that the values or value ranges given above are exemplary values or value ranges that strongly depend, for example, on the desired blocking voltage and the desired properties of the thyristor 1 depend, so that considerable deviations from the above values or ranges of values are possible. The thyristor 1 can have a reverse voltage of 1600V, for example.

In 8th is a sectional view of another embodiment of a thyristor according to the invention 1 , including possible advantageous designs, variants, dimensions and doping concentrations with the design of the thyristor 1 according to the 1 and 2 except for the differences described below.

In the thyristor according to the invention 1 according to 8th runs the first recess 15 to the edge of the semiconductor body 28 , the first recess 15 is formed such that the fifth semiconductor zone 9 a the first recess 15 has an outer surface, the first recess 15 delimiting outer surface of the fifth semiconductor zone 9 through the first outer surface 14 the fifth semiconductor zone 9 is formed. Furthermore, the first and second recesses are preferred 15 and 17 with respect to one parallel to the first surface 11 the first semiconductor body main side 3 in the second semiconductor zone 6 extending plane E mirror-symmetrical. The plane E preferably faces the outer surface 32 the fourth semiconductor zone 8th and to the first surface 11 the first semiconductor body main side 3 in the normal direction N of the first surface 11 an identical distance.

The fifth semiconductor zone 9 preferably runs without interruption parallel to the entire semiconductor body edge 28 , The fifth semiconductor zone 9 in this case runs closed around an interior area 51 the second semiconductor body main side 4 around.

The following is a method for producing a thyristor designed according to the exemplary embodiments 1 indicated with the following process steps.

In a first method step a), as exemplified in 3 shown, providing a semiconductor body 2 of a second conduction type (n-conduction type or p-conduction type), which has a first semiconductor body main side 3 , one of the first semiconductor body main side 3 oppositely arranged second semiconductor body main side 4 and one around the semiconductor body 2 circumferential, the first and second semiconductor body main side 3 and 4 connecting semiconductor body edge 28 having. The semiconductor body 3 has an n-doping as the basic doping within the scope of the exemplary embodiments.

In a subsequent method step b), the result thereof is exemplarily shown in 4 is shown, a generation takes place in the semiconductor body 2 reaching in, over the entire first semiconductor body main side 3 extending first semiconductor zone 5 of a first conductivity type and generating one in the semiconductor body 2 into the third semiconductor zone 7 of the first conductivity type over a not to the edge of the semiconductor body 28 extend center area MB of the second semiconductor body main side 4 , The first semiconductor zone 5 and the third semiconductor zone 7 are p-doped within the scope of the exemplary embodiments, the p-doping, for example, by diffusion of boron aluminum and / or gallium into the semiconductor material (for example silicon or silicon carbide) of the semiconductor body 2 can be generated. As a result of creating the first semiconductor zone 5 and the third semiconductor zone 7 forms one, with an outside 10 the first semiconductor zone 5 oppositely arranged inside 13 the first semiconductor zone 5 in contact and up to the edge of the semiconductor body 28 extending second semiconductor zone 6 of the second line type.

In a subsequent method step c), the result thereof is exemplarily shown in 5 is shown, a generation takes place in the third semiconductor zone 7 reaching in, over a partial area TB of the central area MB of the second semiconductor body main side 4 extending fourth semiconductor zone 7 of the second conductivity type and generating one in the second semiconductor zone 6 reaching over an edge area 25 ' the second semiconductor body main side 4 extending parallel to the edge of the semiconductor body 28 trending, fifth semiconductor zone. of the second line type. The fourth semiconductor zone 8th is considered to be in the third semiconductor zone 7 arranged tub trained. The fourth and fifth semiconductor zones n-doped within the scope of the exemplary embodiments 8th and 9 can, for example, by diffusion of phosphorus into the semiconductor material (eg silicon or silicon carbide) of the semiconductor body 2 be generated. Due to the additional doping of the semiconductor material of the semiconductor body 2 , have the fourth and fifth semiconductor zones 8th and 9 a higher doping concentration than the second semiconductor zone 6 ,

In a subsequent method step d), the result thereof is shown, for example, in 6 is shown, a first, preferably planar, surface is generated 16 the second semiconductor body main side 4 outgoing, parallel to the semiconductor body edge 28 extending and into the second semiconductor zone 6 into the first recess 15 , causing the semiconductor body 2 the first recess 15 delimiting outer surfaces 33 and 34 has, wherein the first recess 15 is designed such that at least sections 15 ' the first recess 15 between the fourth semiconductor zone 8th and the fifth semiconductor zone 9 are arranged and at least in these sections 15 ' the first recess 15 the first recess 15 not to the edge of the semiconductor body 28 runs. Preferably the first recess 15 formed such that the fifth semiconductor zone 9 a the first recess 15 delimiting outer surface 19 having. The first recess 15 delimiting outer surface 19 is the fourth semiconductor zone 8th facing. Preferably, in the method step, a starting from a first surface is also generated 11 the first semiconductor body main side 3 to the edge of the semiconductor body 28 running, parallel to, preferably the entire, semiconductor body edge 28 extending and at least at the edge of the semiconductor body 28 down to the second semiconductor zone 6 reaching, second recess 17 , causing the semiconductor body 2 the second recess 17 delimiting outer surfaces 35 and 36 comprises creating the first and second recesses 15 and 17 can be done simultaneously or in any order in time. The creation of the respective recess 15 respectively. 17 can be done, for example, by etching, sawing and / or grinding.

To produce the according 8th trained thyristor 1 deviates from the above-mentioned method, the first recess in method step d) 15 generated such that the first recess 15 is designed such that the first recess 15 to the edge of the semiconductor body 28 runs and the fifth semiconductor zone 9 a the first recess 15 has an outer surface, the first recess 15 delimiting outer surface of the fifth semiconductor zone 9 through the first outer surface 14 the fifth semiconductor zone 9 is formed, the first outer surface 14 the fifth semiconductor zone 9 an area of the second semiconductor body main side 4 formed.

In a subsequent method step e), which is preferably to be carried out, the result thereof is shown, for example, in 1 and 8th is shown, a silicon oxide layer is produced 22 at least in part of the first recess 15 delimiting outer surfaces 33 and 34 and if available 19 of the semiconductor body 2 , wherein the semiconductor material of the semiconductor body 2 preferably consists of silicon or silicon carbide. A silicon oxide layer is preferably also produced in the method step 29 at least in part of the second recess 17 delimiting outer surfaces 35 and 36 of the semiconductor body 2 , The generation of the silicon oxide layers 22 and 29 takes place by oxidation or by coating the corresponding outer surface areas of the semiconductor body 2 , The generation of the silicon oxide layers 22 and 29 can be done simultaneously or in any order in time.

In a subsequent method step f), which is preferably to be carried out, the result thereof is shown, for example, in 1 and 8th a polyimide layer is arranged 23 on the silicon oxide layer 22 and preferably placing a polyimide layer 30 on the silicon oxide layer 29 , Arranging the polyimide layers 23 and 30 can be done simultaneously or in any order in time.

In a method step f) which is preferably to be carried out after method step d), the result of which is shown, for example, in 1 and 8th a polyimide layer is arranged 23 at least on part of the first recess 15 delimiting outer surfaces 14 . 19 . 33 . 34 of the semiconductor body 2 and preferably placing a polyimide layer 30 at least on part of the second recess 17 delimiting outer surfaces 35 . 36 of the semiconductor body 2 , Arranging the polyimide layers 23 and 30 can be done simultaneously or in any order in time.

In a further process step, which can take place between process steps c) and d), or between process steps d) and e), or after process step f) or after process step g), one is arranged on the first surface 11 the first semiconductor body main side 3 arranged first metallization 12 , one on the fourth semiconductor zone 8th arranged second metallization 53 and one on the third semiconductor zone 7 arranged third metallization 24 , The first metallization 12 preferably forms an anode metallization, the second metallization 53 preferably forms a cathode metallization and the third metallization 24 preferably forms a gate metallization. The respective metallization, which generally consists of several metal layers, can be applied, for example, by sputtering. In the exemplary embodiment, this method step is carried out between method steps d) and e). The result of this process step is exemplified in 7 shown.

It should be noted at this point that features of different exemplary embodiments of the invention can of course be combined with one another as desired, provided the features are not mutually exclusive.

Claims (15)

Thyristor with a semiconductor body (2) which has a first semiconductor body main side (3), a second semiconductor body main side (4) arranged opposite the first semiconductor body main side (3) and a first and second semiconductor body main side (3, 4) which runs around the semiconductor body (2). connecting semiconductor body edge (28), the semiconductor body (2) having a first semiconductor zone (5) of a first conductivity type, an area of an outer side (10) of the first semiconductor zone (5) having a first surface (11) of the first semiconductor body main side (3) The semiconductor body (2) forms a second semiconductor zone which is in contact with an inner side (13) of the first semiconductor zone (5) which is arranged opposite the outer side (10) of the first semiconductor zone (5) and extends to the edge of the semiconductor body (28) (6) of a second conductivity type, the semiconductor body (2) being on the second semiconductor zone (6) arranged third semiconductor zone (7) of the first conductivity type and a fourth semiconductor zone (8) arranged in the third semiconductor zone (7) of the second conductivity type, the semiconductor body (2), in a semiconductor body edge region (25), on the second Has a semiconductor zone (6) arranged fifth semiconductor zone (9) of the second conductivity type, the first outer surface (14) of which faces away from the first semiconductor body main side (3) forms a region of the second semiconductor body main side (4), the fifth semiconductor zone (9) parallel to the semiconductor body edge ( 28), the doping concentrations of the fourth and fifth semiconductor zones (8, 9) being higher than those of the second semiconductor zone (6), the semiconductor body (2) starting from a first surface (16) of the second semiconductor body main side (4) , First recess running parallel to the edge of the semiconductor body (28) and reaching into the second semiconductor zone (6) ng (15), the semiconductor body (2) in the area (26) of the first recess (15) having a first and a second step (20, 20 '), each of which has a concave bottom surface, the area ( 26) of the first recess (15) arranged first stage (20) does not run within the second semiconductor zone (6) and the second stage (20 ') arranged in the region (26) of the first recess (15) within the second and third semiconductor zone ( 6.7) runs. Thyristor after Claim 1 , characterized in that at least sections (15 ') of the first recess (15) are arranged between the fourth semiconductor zone (8) and the fifth semiconductor zone (9), the first recess (15) not at least in these sections (15') extends to the edge of the semiconductor body (28). Thyristor after Claim 2 , characterized in that the first recess (15) is formed such that the fifth semiconductor zone (9) has an outer surface (19) delimiting the first recess (15). Thyristor according to one of the preceding claims, characterized in that the semiconductor body (2), extending from the first surface (11) of the first semiconductor body main side (3) to the semiconductor body edge (28), running parallel to the semiconductor body edge (28) and at least on Has semiconductor body edge (28) extending into the second semiconductor zone (6), second recess (17). Thyristor after Claim 4 , characterized in that an inner edge (B1) of the first recess (15) in the direction perpendicular (S) to the normal direction (N) of the first surface (11) of the first semiconductor body main side (3) closer to the center (M) of the semiconductor body (2) is arranged like an inner edge (B2) of the second recess (17). Thyristor after Claim 4 or 5 , characterized in that a first recess edge line (S1), at which a boundary from the second to the third semiconductor zone (6, 7) adjoins the first recess (15), in a direction perpendicular to the normal direction (N) of the first surface (11) of the the first semiconductor body main side (3) is arranged closer to the center (M) of the semiconductor body (2) than a second recess edge line (S2), on which a boundary from the first to the second semiconductor zone (5, 6) adjoins the second recess (17). Thyristor after Claim 1 , characterized in that the first recess (15) extends to the edge of the semiconductor body (28), the first recess (15) being designed such that the fifth semiconductor zone (9) has an outer surface delimiting the first recess (15), the the first recess (15) delimiting outer surface of the fifth semiconductor zone (9) is formed by the first outer surface (14) of the fifth semiconductor zone (9). Thyristor after Claim 7 , characterized in that the semiconductor body (2), starting from the first surface (11) of the first semiconductor body main side (3) up to the semiconductor body edge (28), running parallel to the semiconductor body edge (28) and at least on the semiconductor body edge (28) up to the second semiconductor zone (6) has a second recess (17). Thyristor after Claim 8 , characterized in that the first and second recesses (15, 17) are mirror-symmetrical in relation to a plane (E) running parallel to the first surface (11) of the first semiconductor body main side (3) in the second semiconductor zone (6). Thyristor after Claim 8 or 9 or according to one of the Claims 4 to 6 , characterized in that the semiconductor body (2) in the area (27) of the second recess (17) has a first and a second step (21, 21 '), each of which has a concave bottom surface, the area (27) the second recess (17) arranged first stage (21) runs exclusively within the first semiconductor zone (5) and the second stage (21 ') arranged in the region (27) of the second recess (17) within the first and second semiconductor zones (5, 6) runs. Thyristor according to one of the preceding claims, characterized in that the first recess (15) extends from an outer surface (31, 32) of the third or fourth semiconductor zone (7, 8). Thyristor according to one of the preceding claims, characterized in that the semiconductor body edge (28) runs from the first to the second semiconductor body main side (3, 4) parallel to the normal direction (N) of the first surface (11) of the first semiconductor body main side (3). Thyristor according to one of the preceding claims, characterized in that the semiconductor body (2) has outer surfaces (14, 19, 33, 34) delimiting the first recess (15), at least part of the outer surfaces (14 delimiting the first recess (15) , 19, 33, 34) of the semiconductor body (2) is designed in each case as an outer surface of a silicon oxide layer (22) of the respective semiconductor zone (6, 7, 9) or on at least a part of the outer surfaces (14, 19) delimiting the first recess (15) , 33, 34) of the semiconductor body (2), a silicon oxide layer is arranged. Thyristor after Claim 13 , characterized in that a polyimide layer (23) is arranged on the silicon oxide layer. Thyristor according to one of the Claims 1 to 12 characterized in that the semiconductor body (2) has outer surfaces (14, 19, 33, 34) delimiting the first recess (15), with at least part of the outer surfaces (14, 19, 33, delimiting the first recess (15)) 34) of the semiconductor body (2), a polyimide layer (23) is arranged.

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