JPH03188636A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device wherein high speed operation and microminiaturization are realized, by using a two layer polysilicon self- alignment technique, and forming an outer base layer of high concentration distantly from an emitter region by using a link base layer sufficiently overlapping with an intrinsic base layer and the outer base layer. CONSTITUTION:Through an oxide film 19, first impurities B is ion-impland in a region of an outer peripheral part, of an intrinsic base region, surrounded by an element isolation LOCOS film 18. A link base layer 24 is formed by diffusing said impurities by heat treatment. The oxide film 19 is selectively wet-etched and eliminated by using a stuck 23 left on the intrinsic base region 22 as a mask, and the surface of the film 24 is exposed. The layer 24 of, e.g. 0.3mum in thickness whose impurity concentration is lower than a P-type outer base layer 28 can be formed. Said layer 24 sufficiently overlaps with a P-type outer base layer 28 whose junction depth is, e.g. about 0.2mum and a P-type intrinsic base layer 31 whose junction depth is 0.2mum or less in this case.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which bipolar transistors are made faster and smaller.

Conventional technology In recent years, bipolar transistors have been miniaturized beyond the limits of photolithography using various self-alignment techniques.
It has achieved extremely high speed and high performance characteristics.

The mainstream of these self-aligned transistors is a two-layer polysilicon self-aligned structure in which polysilicon is used for the base and emitter electrodes. Figure 2 shows a conventional semiconductor device and its manufacturing method (NP from al to Tdl).
An example of a method for manufacturing an N transistor will be shown.

First, as shown in FIG. 2, an N-type buried collector layer 2 is formed on the surface of a P-type silicon substrate 1, and then an N-type epitaaxial layer 3 is grown. Next, element isolation LOCO3
A film 4 is formed on the surface of the N-type epitaxial layer 3. Next, the N-type epitaxial layer 3 and the element isolation LOGO 5 film 4
A P° polyrecon film 5 and a CVD oxide film 6, which will serve as a base extraction electrode, are grown on the entire surface of the substrate. Next, the CV-D oxide film 6 and then the P° polysilicon film 5 are removed by etching using a photolithography resist as a mask to expose the intrinsic base region 7 on the surface of the N-type epitaquin layer 3.

Next, as shown in FIG. 2 tb+, after growing a nitride film 8 over the entire surface, P-type impurities are introduced into the N-type epitaxial layer 3 from the P polysilicon film 5 by heat treatment, and the P-type external base layer 9 is heated. form.

Next, as shown in FIG. 2fc), the nitride film 8 is anisotropically etched to form a nitride film sidewall 10. Polysilicon-based extraction electrode 5. An emitter extraction hole 11 is formed.

Finally, as shown in FIG. Impurity ions are implanted, and P-type impurities are introduced into the intrinsic base region 7 from the polysilicon emitter electrode 12 through the emitter lead-out opening 11 by heat treatment to form a P-type concrete base layer 13. Furthermore, polysilicon emitter electrode 1
2, an N-type impurity is introduced into the intrinsic base layer 13 from the polysilicon emitter electrode 12 through the emitter lead-out opening 11 by heat treatment, and the N-type impurity is introduced into the intrinsic base layer 13 through the emitter extraction hole 11.
A mold emitter layer 14 is formed.

According to the method for manufacturing a semiconductor device as described above, the external base region, emitter region, base electrode extension part, and emitter electrode extension part of a bipolar transistor can all be formed in a self-aligned manner, making it possible to dramatically increase the speed and miniaturize the bipolar transistor. You can aim for it.

Problems to be Solved by the Invention In the conventional two-layer polysilicon self-alignment technique described above, the external base layer and the intrinsic base layer are sufficiently overlapped under the nitride film sidewall of the sidewall of the base extraction electrode.
The thickness of the nitride sidewall and the junction depth of the external base layer and intrinsic base layer are optimized to avoid collector-emitter punch-through leakage and increases in base resistance in the overlap region. For example, when the depth of the external base layer is about 0.3 μm and the depth of the intrinsic base layer is about 0.2 μm, the optimal thickness of the nitride film sidewall is 0.2 to 0.25 μm. However, in such cases, the highly doped external base layer is very close to the emitter region, leading to a decrease in hFE and cutoff frequency, and an increase in the pace-emitter capacitance due to the overlap between the external base layer and the emitter layer. This leads to a decrease in reliability due to hot carrier effects.

The above-mentioned problem caused by the close proximity of the highly doped extrinsic base layer and the emitter region can be solved by forming a link base layer that sufficiently overlaps the extrinsic base layer and the intrinsic base layer to distance the highly doped extrinsic base layer from the emitter region. However, the formation of the link base layer in two-layer polysilicon technology self-aligned transistors is very difficult.

The present invention solves the above-mentioned conventional problems and provides a method and method for manufacturing a semiconductor device having a link base layer that sufficiently overlaps both an extrinsic base layer and an intrinsic base layer using two-layer polysilicon self-alignment technology. The purpose is to

Means for Solving the Problems In order to achieve this object, the method for manufacturing a semiconductor device of the present invention provides a method for manufacturing a semiconductor device in which a first insulating film is formed on the entire surface of a base region on a surface portion of a semiconductor substrate and a first insulating film formed around the base region. a second insulating film, a first semiconductor film, and then a third insulating film; selectively etching away the third insulating film and then the first semiconductor film; forming a stack consisting of the first semiconductor film and the third insulating film on the intrinsic base region in the region; forming a link base layer by adding a first impurity to a region surrounding the first insulating film at the outer edge of the base region; and selectively adding the second semiconductor film using the stack as a mask. a step of etching away the surface of the link base layer to expose the surface of the link base layer, a step of forming a sidewall made of a fourth insulating film on the sidewalls of the stack and the second insulating film, and a step of forming a second semiconductor film on the entire surface. a step of etching away the second semiconductor film on the stack and the sidewall to form a base extraction electrode of the second semiconductor film;
a step of adding a second impurity to the base extraction electrode; a step of introducing a second impurity from the base extraction electrode to the surface portion of the semiconductor substrate to form an external base layer;
and a step of etching and removing the stack and the second insulating film to form an emitter lead-out opening.

Effect: According to the method of manufacturing a semiconductor device of the present invention, a link base layer that sufficiently overlaps both the intrinsic base layer and the extrinsic base layer can be formed using a two-layer polysilicon self-alignment technique, thereby reducing collector-emitter punch-through leakage and base resistance. The highly doped external base layer can be moved away from the emitter region while avoiding large increases.

Embodiment FIG. 1 (al to (f)) shows an embodiment of the present invention using NPN +
- This is a sectional view showing the steps of the transistor.

First, as shown in FIG. 1(a), a P-type silicon substrate 15
After forming an N-type buried collector layer 16 on the surface, an N-type epitaxial layer 17 that will become a semiconductor substrate is grown.

Next, the element isolation LOCO3 film 18, which becomes the first insulating film, is
After forming on the surface of the type epitaxial layer 17, an oxide film 19, which will become the second insulating film, is formed on the entire surface with a thickness of about 50 to 1100 nm, and then a polysilicon film 20, which will become the first semiconductor film, is formed with a thickness of about 20 nm.
After growing a nitride film 21 of about 0 to 300 nm and then about 50 to 1100 nm, which will become the third insulating film, the nitride film 21 and then the polysilicon film 20 are selectively etched using a photolithographic resist as a mask. The intrinsic base region 2 on the surface of the N-type epitaxial layer 17 is removed.
A stack 23 consisting of a nitride film 21 and a polysilicon film 20 is formed on the nitride film 21 and the polysilicon film 20.

Next, as shown in FIG. 1 fb), 1 to 2×10 ” of boron, which becomes the first impurity, is added to the outer edge of the intrinsic base region 22 and the region surrounded by the element isolation LOGO3 film 18 through the oxide film 19. The link base layer 24 is formed by implanting ions of about an-2 and then diffusing them by heat treatment at 900° C. for about 30 minutes.Next, using the stack 23 remaining on the intrinsic base region 22 as a mask, the oxide film 19 is selectively formed. Wet etching is performed to expose the surface of the link base layer 24.

Next, as shown in FIG. 1 (C1), a nitride film to be a fourth insulating film is grown to a thickness of about 200 to 300 nm over the entire surface, and then anisotropically etched to form a nitride film sidewall 25.

Next, as shown in FIG. 1 (dl), after growing a polysilicon film that will become the second semiconductor to a thickness of about 400 to 500 nm over the entire surface, a resist is applied to the entire surface. Next, the resist and stack 23 and the nitride film sidewall 25 are formed. At the same time, the upper polysilicon film is removed by etching to flatten the surface, and a polysilicon base lead electrode 26 is formed.

Next, as shown in FIG. 2, the surface of the polysilicon base lead electrode 26 is oxidized to form an oxide film 27.

Next, a second impurity of boron is added to the polysilicon base extraction electrode 26 through the oxide film 27 at a rate of 5×101S to 1×
After ion implantation of about 1016all-2, 900℃,
By heat treatment for 30 to 60 minutes, boron is introduced from the polysilicon base lead-out electrode 26 into the N-type epitaxial layer 17 to form an external base layer 28 having a higher impurity concentration than the link base layer 24.

Next, as shown in FIG. 2 (fl), the nitride film 21 left on the intrinsic base region 22 and the polysilicon film 20 are etched and removed using a photolithographic resist as a mask, and then the oxide film 19 is wet-etched. This is removed to form an emitter lead-out opening 29.

Finally, as shown in FIG. 2+g+, a polysilicon film is grown on the entire surface, and then the polysilicon film is selectively etched away using a photolithographic resist as a mask to form an emitter extraction electrode 30. Furthermore, ions of boron as a third impurity are implanted into the polysilicon emitter extraction electrode 30 at a depth of about 1 to 5 x 10"cm-2.
Emitter drawer hole 2 is formed by heat treatment at ℃ for about 30 minutes.
9 into the intrinsic base region 22 from the polysilicon emitter extraction electrode 30 to form the intrinsic base layer 31.
form. Furthermore, polysilicon emitter extraction electrode 3
Arsenic, which will become the fourth impurity, is ion-implanted into the polysilicon emitter lead electrode 30 through the emitter lead-out opening 29 and introduced into the intrinsic base layer 31 by heat treatment at 900°C for about 30 minutes. ,
An emitter layer 32 is formed.

According to the method for manufacturing a semiconductor device as described above, the P-type external base layer 28 with a junction depth of about 0.2 μm and the P-type concrete base layer 31 with a junction depth of 0.2 μm or less are sufficiently overlapped. A link base layer 24 having a thickness of about 0.3 μm and having an impurity concentration lower than that of the P-type external base layer 28 can be formed.

Therefore, while avoiding punch-through between the collector and emitter and a significant increase in base resistance, a highly doped external base layer is formed from the emitter region to about the width of the nitride film sidewall (0.2 to 0.0
．． 25 μm).

Note that in the example, the third insulating film was a nitride film, but
The third insulating film may be an oxide film.

In addition, in the example, the fourth insulating film was a nitride film, but
The fourth insulating film may be an oxide film.

Further, in the embodiment, the surface of the polysilicon-based lead electrode was oxidized to form an insulating film between it and the emitter lead electrode, but this insulating film may be a CVD insulating film.

As described in detail, according to the method of manufacturing a semiconductor device of the present invention, punch-through leakage between the collector and emitter is prevented by using a two-layer polysilicon self-alignment technique to form a link base layer that sufficiently overlaps both the intrinsic base layer and the extrinsic base layer. The highly doped external base layer can be moved away from the emitter region while avoiding a large increase in base resistance.

For this reason, the current amplification factor (hFE) and cutoff frequency decrease due to the proximity of the highly doped external base layer to the emitter region, and the overlap between the external base layer and emitter layer increases the pace emitter capacitance and increases hot carriers. It is possible to suppress a decrease in reliability due to effectiveness.

[Brief explanation of drawings]

FIG. 1(al~(fl) is a step-by-step cross-sectional view of an NPN bipolar transistor according to an embodiment of the present invention, FIG. 2(al~(d)
) are process-order sectional views of a conventional example. 5... P+ polysilicon film (base extraction electrode), 6... CVD oxide film, 7... Intrinsic base region, 8... Nitride film, 10・・・・・・
Nitride film side wall, 11...Emitter extraction portion opening, 17...N type epitaxial layer, 1
8... Element isolation LOGO3 film, 19...
・Oxide film, 20...Polysilicon film, 21...
...Nitride film, 22...Intrinsic base region, 2
3...Stack, 24...Link base layer, 25...Nitride film side wall, 26...
...Polysilicon base extraction electrode, 28...
. . . External base layer, 29 . . . Emitter draw-out portion opening.

Claims (1)

[Claims] A step of growing a second insulating film, then the first semiconductor film, and then a third insulating film on the entire surface of the base region on the surface of the semiconductor substrate and the first insulating film formed around the base region. Then, the third insulating film and then the first semiconductor film are selectively etched away, and a stack consisting of the first semiconductor film and the third insulating film is formed on the intrinsic base region in the base region. and applying a first impurity through the second insulating film using the stack as a mask to a region on the surface of the semiconductor substrate at the outer edge of the intrinsic base region and surrounded by the first insulating film. a step of selectively etching away the second semiconductor film using the stack as a mask to expose the surface of the link base layer; a step of forming a sidewall made of a fourth insulating film on the sidewall of the film, a step of growing a second semiconductor film on the entire surface, and etching away the second semiconductor film on the stack and the sidewall. forming a base extraction electrode of the second semiconductor film, adding a second impurity to the base extraction electrode, and introducing a second impurity from the base extraction electrode into the surface portion of the semiconductor substrate. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming an external base layer by etching the stack and the second insulating film to form an emitter lead-out opening.