JPH11176837A - Semiconductor integrated circuit device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a higher speed for a semiconductor integrated circuit having a bipolar transistor by locating the maximum value of the concentration of impurities of a lightly doped collector region to an area where the maximum value is shallower than coupling portion between the true base region and the lightly doped collector region. SOLUTION: p-type impurities such as B are introduced to an epitaxial layer by ion-implantation, in succession, n-type impurities such as P is introduced to the epitaxial layer by ion-implantation. Next, by giving the first thermal treatment to the semiconductor substrate, a true base region constituted with p-type impurities and a lightly doped collector region constitute with n-type impurities are formed. Here, the conditions for p-ion implantation for forming the lightly doped collector region are set in such a manner that, in the lightly doped collector region after a second heat treatment to be given later to the semiconductor substrate, the region obtaining the maximum impurities concentration becomes shallower than the collector base coupling portion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a bipolar device.

[0002]

2. Description of the Related Art A structure in the depth direction including an intrinsic base region of an npn-type bipolar transistor studied by the present inventors will be described with reference to an impurity concentration distribution shown in FIG.

The emitter region contains 3 × 10 ²⁰ n-type impurities.
This is a high-concentration impurity region introduced at about cm ⁻³ . Below this, a p-type intrinsic base region having a thickness of about 0.05 μm and a maximum impurity concentration of about 10 ¹⁹ cm ⁻³ is provided. Under the intrinsic base region, the impurity concentration is 5 × 10 ¹⁵
Although an n-type epitaxial layer of about cm ⁻³ is about 0.2 μm, the impurity concentration in this region is 5 × 10 ¹⁶ to 10 ^17.
An n-type low concentration collector region of about cm ⁻³ is formed. The maximum value of the impurity concentration of this low concentration collector region is
It is located approximately in the center of the epitaxial layer below the intrinsic base region. In addition, below the epitaxial layer,
An n-type high concentration collector buried layer exists as a lead-out region to the collector electrode.

Meanwhile, the low-concentration collector region is to reduce the parasitic capacitance of the collector-base junction, also to improve the cutoff frequency f _T, it is provided to speed up the bipolar transistor, for example, an epitaxial A method of uniformly introducing impurities during layer growth, or 150
It is formed by implanting impurity ions below the intrinsic base region at an acceleration voltage of keV.

A method of forming a low concentration collector region by ion implantation is described in, for example, IEEE Transactions on Electron Devices.
-ps Si Bipolar IC Using Advanced Super Self-Aligne
d Process Technology with Collector Ion Implantati
on "Vol. 36, PP. 1370-1375, 1989).

[0006]

However, the present inventor has set forth a method for forming a low concentration collector region,
The following problems were found.

In other words, if impurities are introduced during the growth of the epitaxial layer, unnecessary parasitic capacitance is added since impurities are introduced in areas other than below the intrinsic base region. In addition, when impurities are introduced below the intrinsic base region by ion implantation, the low concentration collector region is easily affected by the tail due to channeling of the intrinsic base region, causing a decrease in the withstand voltage of the collector-base junction.

An object of the present invention is to provide a technique capable of realizing a high-speed semiconductor integrated circuit device having a bipolar transistor.

Another object of the present invention is to provide a technique capable of realizing a high operating speed in a semiconductor integrated circuit device having a bipolar transistor without lowering the withstand voltage of a collector-base junction. Is to do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device according to the present invention comprises an emitter region, an intrinsic base region and a low concentration collector region, and the intrinsic base region is connected to a base electrode via an external base diffusion layer and a base extraction electrode. In the bipolar transistor thus manufactured, the maximum value of the impurity concentration of the low concentration collector region is located in a region shallower than the junction between the intrinsic base region and the low concentration collector region.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises an emitter region, an intrinsic base region, and a low-concentration collector region, and the intrinsic base region is formed via an external base diffusion layer and a base extraction electrode. When forming a bipolar transistor connected to the base electrode by first forming a base extraction electrode, then,
The ion implantation of the impurity forming the low concentration collector region and the ion implantation of the impurity forming the intrinsic base region are continuously performed. The ion implantation of the impurity forming the low concentration collector region is performed by an acceleration voltage of about 100 keV. Done.

According to the above-mentioned means, in the impurity concentration distribution of the low concentration collector region, the region where the maximum value of the impurity concentration is located is set shallower than the collector-base junction, so that the parasitic concentration of the collector-base junction is reduced. Capacitance can be reduced by about 10% compared to the case of the technique studied by the present inventors, and furthermore, it is possible to reduce the influence of channeling of the intrinsic base region. Without making f _T about 10 to 2 times higher than in the case of the technique studied by the inventor.
0% can be improved.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 is a distribution diagram of impurity concentration showing a structure in a depth direction including an intrinsic base region of an npn-type bipolar transistor according to an embodiment of the present invention formed on a semiconductor substrate. It is.

The emitter region is an n-type high-concentration impurity region having a thickness of about 0.03 μm into which an n-type impurity, for example, arsenic (As) is introduced, for example, about 3 × 10 ²⁰ cm ⁻³ .

Underneath the layer, a p-type impurity, for example, boron (B) is formed by ion implantation to form a layer having a maximum impurity concentration of about 10 ¹⁹ cm ^{-3 and} a thickness of about ^0.1 cm. A 05 μm p-type intrinsic base region is provided. The intrinsic base region is formed by a difference between the concentration of the p-type impurity and the concentration of the n-type impurity forming the emitter region. For this reason, the maximum value of the impurity concentration of the intrinsic base region and the thickness of the intrinsic base region are sensitive to heat treatment and the like in the manufacturing process of the bipolar transistor.

Under the intrinsic base region, an n-type epitaxial layer having an impurity concentration of, for example, about 5 × 10 ¹⁵ cm ⁻³ is about 0.2 μm. In this region, an n-type impurity, for example, phosphorus ( For example, an n-type low-concentration collector region having an impurity concentration of about 5 × 10 ¹⁶ to 10 ¹⁷ cm ⁻³ is formed by introducing P) by ion implantation. However, the maximum impurity concentration of this low concentration collector region is
It is located in a region shallower than the collector-base junction.

Further, under the epitaxial layer, a high-concentration n-type collector buried layer exists as a region for leading to the collector electrode.

Next, a method of manufacturing the npn-type bipolar transistor according to the first embodiment having the impurity concentration distribution shown in FIG. 1 will be described with reference to FIGS.

First, as shown in FIG. 2, an n-type collector buried layer 2 and an n-type epitaxial layer 3 having a thickness of, for example, about 0.03 μm are sequentially formed on a p-type semiconductor substrate 1. Next, as shown in FIG. 3, after forming a channel stopper layer 4, an isolation oxide film 5 is formed by a selective oxidation method.
Is formed, and then an n-type impurity, for example, P is introduced into a part of the epitaxial layer 3 to form the collector extraction diffusion layer 6.

Next, as shown in FIG. 4, after removing the silicon oxide film on the surface of the epitaxial layer 3 in the region where the intrinsic base region is to be formed later, a p-type impurity such as B is left on the semiconductor substrate 1. The added polycrystalline silicon film 7 and silicon oxide film 8 are sequentially deposited.

Next, as shown in FIG. 5, using the photoresist pattern as a mask, the silicon oxide film 8 and the polycrystalline silicon film 7 are sequentially etched to remove the silicon oxide film 8 and the polycrystalline silicon film 7 other than the base extraction region. Remove. The processed polycrystalline silicon film 7 forms a base extraction electrode.

Thereafter, a p-type impurity such as B is introduced into the epitaxial layer 3 by ion implantation.
An n-type impurity, for example, P is introduced into the epitaxial layer 3 by ion implantation. Next, the first heat treatment is performed on the semiconductor substrate 1 to form an intrinsic base region 9a composed of the p-type impurity and a low concentration collector region 10a composed of the n-type impurity. However, the impurity concentration distributions of the intrinsic base region 9a and the low-concentration collector region 10a do not show the impurity concentration distribution shown in FIG. 1, and are shown in FIG. 1 by the second and subsequent heat treatments performed on the semiconductor substrate 1 later. Thus, an intrinsic base region 9b and a low concentration collector region 10b having an impurity concentration distribution are obtained.

Here, the low-concentration collector region 10a has, for example, an acceleration voltage of about 100 keV and a dose of about 5 × 10 ¹² to
It is formed by implanting P ions into the epitaxial layer 3 under the condition of 10 ¹³ cm ^-2 . The conditions for this ion implantation are set so that, in the low-concentration collector region 10b after the second and subsequent heat treatments to be performed on the semiconductor substrate 1, the region where the impurity concentration becomes maximum is shallower than the collector-base junction. Is done.

When P ions are introduced into the epitaxial layer 3 under the polycrystalline silicon film 7 by ion implantation when the low concentration collector region 10a is formed,
Before depositing the polycrystalline silicon film 7 on the semiconductor substrate 1,
The ion implantation may be performed using a photoresist pattern as a mask.

Next, as shown in FIG. 6, after depositing a silicon oxide film 11 on the semiconductor substrate 1, the silicon oxide film 11 is etched by, for example, RIE (Reactive Ion Etching) to form a silicon oxide film. 8 and a sidewall spacer made of the silicon oxide film 11 is formed on the side wall of the polycrystalline silicon film 7.

Here, in order to prevent the surface of the intrinsic base region 9a from being abraded and not to damage the intrinsic base region 9a, a thin silicon oxide film is previously formed on the surface of the intrinsic base region 9a as the etching stop film. It may be formed.

Next, as shown in FIG. 7, after exposing the surface of the intrinsic base region 9a, a polycrystalline silicon film 12 to which an n-type impurity, for example, P is added, is deposited on the semiconductor substrate 1; Then, the polysilicon film 12 is etched using the photoresist pattern as a mask.

Next, as shown in FIG. 8, a passivation film 13 is deposited on the semiconductor substrate 1. Next, by performing a second heat treatment on the semiconductor substrate 1, the impurity (P) added to the polycrystalline silicon film 12 is diffused into the epitaxial layer 3, and the n-type having the impurity concentration distribution shown in FIG. Is formed. Further, impurity (B) added to polycrystalline silicon film 7 diffuses into epitaxial layer 3 to form p-type external base diffusion layer 15.

At the same time, the impurity (B) forming the intrinsic base region 9a diffuses again to form the p-type intrinsic base region 9b having the impurity concentration distribution shown in FIG.
Further, the impurity (P) forming the low concentration collector region 10a diffuses again to form the n-type low concentration collector region 10b having the impurity concentration distribution shown in FIG. The impurity concentration distribution of the low concentration collector region 10b subjected to the second heat treatment and the low concentration
There is no significant change from the impurity concentration distribution of 0a.

Next, by etching the passivation film 13 using the photoresist pattern as a mask, the contact hole 1 is formed on the collector leading diffusion layer 6.
6a, and a contact hole 16b is formed on the polycrystalline silicon film 12. At the same time, passivation film 1
3 and silicon oxide film 8 are sequentially etched to form contact holes 16c on polycrystalline silicon film 7.
To form

Thereafter, a metal film is deposited on the semiconductor substrate 1 and then the metal film is etched using the photoresist pattern as a mask, so that the collector electrode 17 in contact with the collector lead diffusion layer 6 through the contact hole 16a, An emitter electrode 18 in contact with the polycrystalline silicon film 12 on the emitter region 14 through the hole 16b and a base electrode 19 in contact with a base extraction electrode (polycrystalline silicon film 7) connected to the intrinsic base region 9b through the contact hole 16c are formed. ,
The npn-type bipolar transistor of the present embodiment is completed.

As described above, according to the first embodiment, the region of the low-concentration collector region 10b where the impurity concentration distribution is maximum is made shallower than the collector-base junction, so that the collector-base junction is formed. The parasitic capacitance can be reduced by about 10% as compared with the conventional case, and the intrinsic base region 9b
It is possible to reduce the influence of the channeling, the f _T without decreasing the breakdown voltage of the collector-base junction can be improved approximately 10-20% than before.

Next, the first embodiment is referred to as ECL (Emitter
Coupled Logic-CMOS (Complementary Metal Ox)
The case where the present invention is applied to an (ide Semiconductor) type BiCMOS memory will be described.

FIG. 9 shows an ECL-CMOS type BiCMOS.
FIG. 2 is a plan view illustrating a configuration of a memory. The memory cell 20 is C
The peripheral circuit 21 constituted by a MOS FET (Field Effect Transistor) and arranged around the memory cell 20 is constituted by the bipolar transistor of the first embodiment using the ECL circuit.

In this BiCMOS memory, the writing speed and the reading speed of the memory are increased, and the access time of the memory is shortened by about 20% as compared with the case where a conventional bipolar transistor is used.

In the first embodiment, after the impurity ion implantation for forming the intrinsic base region 9a and the impurity ion implantation for forming the low-concentration collector region 10a are performed successively, The substrate 1 was subjected to the first heat treatment, but after ion implantation of impurities for forming the low concentration collector region 10a, the impurities for forming the intrinsic base region 9a were thermally diffused into the surface of the semiconductor substrate 1. May be introduced from

(Embodiment 2) A method of manufacturing another npn-type bipolar transistor having the impurity concentration distribution shown in FIG. 1 will be described with reference to FIGS.

First, as shown in FIG. 10, an n-type collector buried layer 2 and an n-type epitaxial layer 3 are sequentially formed on a p-type semiconductor substrate 1.

Next, after forming a shallow trench isolation 22 and a deep trench isolation 23 as an element isolation insulating film, a collector lead diffusion layer 6 is formed. Next, after removing the silicon oxide film on the surface of the epitaxial layer 3 in the region where the intrinsic base region 9a is to be formed later, the p-type impurity, for example, the polycrystalline silicon film 24 to which B is added and the impurity Is sequentially deposited.

Next, as shown in FIG.
Metal film above, for example, titanium (Ti) film or a tungsten (W) film or a silicide film, for example, titanium silicide _{(TiSi X, 0 <x ≦} 2) film or a tungsten silicide _{(WSi x, 0 <x ≦} 2) film, Is deposited, the polycrystalline silicon film 25 is reacted with the metal film or the silicide film to form a silicide layer 26.
Next, a silicon oxide film 27 is deposited on the semiconductor substrate 1.

Thereafter, similarly to the manufacturing method described in the first embodiment, the npn-type bipolar transistor according to the second embodiment is formed.

That is, as shown in FIG. 12, after forming a base extraction electrode constituted by the polycrystalline silicon film 24 and the silicide layer 26, the intrinsic base region 9 is formed.
Then, ion implantation of a p-type impurity for forming a is performed and ion implantation of an n-type impurity for forming a low concentration collector region 10a are performed successively.
Is subjected to a first heat treatment.

Next, sidewall spacers made of the silicon oxide film 11 are formed on the side walls of the silicon oxide film 27, the silicide layer 26, and the polycrystalline silicon film 24.

Next, as shown in FIG. 13, after forming a polycrystalline silicon film 12 to which an n-type impurity is added on the intrinsic base region 9a, a passivation film 13 is deposited on the semiconductor substrate 1; By performing a second heat treatment on semiconductor substrate 1, n-type impurities added to polycrystalline silicon film 12 diffuse into epitaxial layer 3, and furthermore, intrinsic base region 9 a and low concentration collector region 10.
The p-type impurity and the n-type impurity constituting each of a are diffused to form emitter region 14, intrinsic base region 9b and low concentration collector region 10b having the impurity concentration distribution shown in FIG.

Thereafter, contact holes 16a to 16c
Is formed, and then a collector electrode 17, an emitter electrode 18, and a base electrode 19 are formed, thereby completing the npn-type bipolar transistor of the second embodiment.

As described above, according to the second embodiment, the trench isolation is used for the element isolation insulating film, and the low-resistance silicide layer is formed on the surface of the base extraction electrode. High integration and high speed of a semiconductor integrated circuit device having a bipolar transistor can be realized.

(Embodiment 3) An SOI (Silicon On Insulato) having the impurity concentration distribution shown in FIG. 1 and having a silicon layer provided on a supporting substrate via a buried oxide film.
r) A method for manufacturing an npn-type bipolar transistor formed on a substrate will be described with reference to FIGS.

First, as shown in FIG.
An n-type collector buried layer 2 and an n-type epitaxial layer are sequentially formed on a p-type silicon layer 30 provided thereon with a buried oxide film 29 interposed therebetween.

Next, after forming a shallow trench isolation 22 and a deep trench isolation 23 as element isolation insulating films, a collector lead diffusion layer 6 is formed. Next, after removing the silicon oxide film on the surface of the epitaxial layer 3 in the region where the intrinsic base region 9a is to be formed later,
A polycrystalline silicon film 24 to which a p-type impurity, for example, B is added, a polycrystalline silicon film 25 to which no impurity is added, and a silicon oxide film 27 are sequentially deposited on the OI substrate. As a method of introducing impurities into the polycrystalline silicon film 25, for example, when the polycrystalline silicon film 25 is grown by the CVD method, an impurity-added CVD is performed while adding impurities.
Method or ion implantation method. In the case of the ion implantation method, impurity ions are implanted after the polycrystalline silicon films 24 and 25 are formed by the CVD method without introducing impurities. In this case, the polycrystalline silicon films 24 and 25 can be formed at one time.

Next, as shown in FIG. 15, using the photoresist pattern as a mask, the silicon oxide film 27, the polycrystalline silicon film 25 and the polycrystalline silicon film 24 are sequentially etched, and the polycrystalline silicon films 25 and 24 are used. After forming the configured base extraction electrode, ion implantation of a p-type impurity for forming the intrinsic base region 9a and ion implantation of an n-type impurity for forming the low concentration collector region 10a are performed successively. , A first heat treatment is performed on the SOI substrate.

Next, a silicon oxide film 11 is formed on the SOI substrate.
Then, the silicon oxide film 11 is processed by anisotropic etching such as RIE, so that the silicon oxide film 11 is formed on the side walls of the silicon oxide film 27, the polycrystalline silicon film 25, and the polycrystalline silicon film 24 from the silicon oxide film 11. Is formed.

Next, as shown in FIG. 16, after a polycrystalline silicon film 12 to which an n-type impurity is added is deposited on an SOI substrate, the polycrystalline silicon film 12 is etched using a photoresist pattern as a mask. . At this time, the silicon oxide film 27 on the base lead electrode made of the polycrystalline silicon films 25 and 24 is also removed.

Next, after depositing a metal film or a silicide film on the SOI substrate, the polycrystalline silicon film 25 reacts with the metal film or the silicide film to form a silicide layer 26 on the surface of the polycrystalline silicon film 25. Form. At the same time, the polycrystalline silicon film 12 reacts with the metal film to form a silicide layer 26 on the surface of the polycrystalline silicon film 12.

Thereafter, similarly to the manufacturing method described in the first embodiment, the npn-type bipolar transistor according to the third embodiment is formed.

That is, as shown in FIG. 17, after the passivation film 13 is deposited on the SOI substrate, the SOI substrate is subjected to the next (second or third) heat treatment to be added to the polycrystalline silicon film 12. The n-type impurities diffuse into the epitaxial layer 3, and the p-type impurities and the n-type impurities constituting the intrinsic base region 9a and the low-concentration collector region 10a, respectively, diffuse to form the impurities shown in FIG. An emitter region 14 having a concentration distribution,
An intrinsic base region 9b and a low concentration collector region 10b are formed.

Thereafter, contact holes 16a to 16c
Is formed, and then a collector electrode 17, an emitter electrode 18, and a base electrode 19 are formed, whereby the npn-type bipolar transistor of the third embodiment is completed.

As described above, according to the third embodiment, the parasitic capacitance is reduced by forming the low-resistance silicide layer on the surface of the base extraction electrode and forming the bipolar transistor on the SOI substrate. Thus, the speed of a semiconductor integrated circuit device having a bipolar transistor can be increased.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, a case where the present invention is applied to a method of manufacturing an npn-type bipolar transistor has been described. However, the present invention is also applicable to a method of manufacturing a pnp-type bipolar transistor.

[0064]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the impurity concentration distribution of each of the emitter region, the intrinsic base region and the low-concentration collector region can be optimized. Therefore, the present inventors examined the parasitic capacitance of the collector-base junction. load is reduced by about 10% than the case of the technique of Figure 18 becomes lighter, also, f _T
Is about 10 to 20% lower than the case of the technology studied by the inventor.
Since the switching speed is improved and the switching speed is increased, the operation speed of the semiconductor integrated circuit device having the bipolar transistor is increased by about 10 to 20%.

Further, since the impurity concentration of each of the emitter region, the intrinsic base region and the low concentration collector region can be optimized, the influence of channeling of the intrinsic base region can be reduced, and the withstand voltage of the collector-base junction can be reduced. Without this, the operation speed of the semiconductor integrated circuit device having the bipolar transistor can be increased.

[Brief description of the drawings]

FIG. 1 is an impurity concentration distribution diagram in a depth direction of a semiconductor substrate including an intrinsic base region of a bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing an npn-type bipolar transistor according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the npn-type bipolar transistor according to one embodiment of the present invention;

FIG. 18 is an impurity concentration distribution diagram in a depth direction of a semiconductor substrate including an intrinsic base region of a bipolar transistor studied by the present inventors.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Collector buried layer 3 Epitaxial layer 4 Channel stopper layer 5 Isolation oxide film 6 Collector extraction diffusion layer 7 Polycrystalline silicon layer 8 Silicon oxide film 9a Intrinsic base region 9b Intrinsic base region 10a Low concentration collector region 10b Low concentration collector region Reference Signs List 11 silicon oxide film 12 polycrystalline silicon film 13 passivation film 14 emitter region 15 external base diffusion layer 16a contact hole 16b contact hole 16c contact hole 17 collector electrode 18 emitter electrode 19 base electrode 20 memory cell 21 peripheral circuit 22 shallow groove isolation 23 Deep trench isolation 24 Polycrystalline silicon film 25 Polycrystalline silicon film 26 Silicide film 27 Silicon oxide film 28 Support substrate 29 Buried oxide film 30 Silicon layer

Claims (8)

[Claims] 1. A semiconductor integrated circuit comprising an emitter region, an intrinsic base region and a low concentration collector region, wherein the intrinsic base region has a bipolar transistor connected to a base electrode via an external base diffusion layer and a base lead electrode. A semiconductor integrated circuit device, wherein a maximum value of an impurity concentration of the low concentration collector region is located in a region shallower than a junction between the intrinsic base region and the low concentration collector region. 2. A semiconductor integrated circuit comprising an emitter region, an intrinsic base region, and a low concentration collector region, wherein the intrinsic base region has a bipolar transistor connected to a base electrode via an external base diffusion layer and a base extraction electrode. A semiconductor integrated device, wherein near the junction between the intrinsic base region and the low-concentration collector region, the concentration of the impurity constituting the low-concentration collector region decreases as the depth increases from the surface of the substrate. Circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein said base lead electrode is made of a polycrystalline silicon film, and a silicide layer is formed on a surface of said polycrystalline silicon film. Semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein an element isolation region for electrically isolating adjacent semiconductor elements is formed by a trench isolation. A semiconductor integrated circuit device characterized by the above-mentioned. 5. The semiconductor integrated circuit device according to claim 1, wherein said bipolar transistor is formed on an SOI substrate having a silicon layer provided on a supporting substrate via a buried oxide film. A semiconductor integrated circuit device characterized in that: 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein after the base extraction electrode is formed, ion implantation of impurities forming the low concentration collector region is performed. And a method of manufacturing a semiconductor integrated circuit device, wherein ion implantation of impurities constituting the intrinsic base region is performed continuously. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein after forming said base lead-out electrode, ion implantation of impurities forming said low-concentration collector region is performed. And then introducing an impurity constituting the intrinsic base region by thermal diffusion. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the ion implantation of the impurity forming the low concentration collector region is performed by an acceleration voltage of about 100 keV. A method for manufacturing a circuit device.