JPH0794521A - Bipolar transistor - Google Patents

Abstract

PURPOSE:To provide a bipolar transistor whose operation speed is higher than a conventional one. CONSTITUTION:The title bipolar transistor has an n-type emitter diffusion layer 3 formed on the purface of a p-type silicon substrate 1, an emitter leading electrode 4 formed on the p-type silicon substrate 1 so as to surround this n-type emitter diffusion layer 3 touching the n-type emitter diffusion layer 3 and having a cut line, a p-type base layer 7 formed self-matchingly on the n-type emitter diffusion layer 3 in a region surounded by this emitter leading electrode 4, and an n-type collector layer 9 formed self-matchingly on this p-type base layer 7.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to bipolar transistors.

[0002]

2. Description of the Related Art In recent years, a large-scale integrated circuit formed by integrating a large number of transistors, resistors, etc., on one chip in an important part of a computer or communication equipment so as to achieve an electric circuit ( LSI) is frequently used. Therefore, the performance of the entire device is largely linked to the performance of the LSI alone. The performance improvement of the LSI alone can be realized by increasing the speed of the device.

FIG. 5 is a sectional view of an element showing the structure of a conventional high speed bipolar transistor. This will be described according to the manufacturing process. First, the n ⁺ type buried layer 71 and the n ⁻ type collector epitaxial layer 72 are formed on the silicon substrate 70, and then the collector epitaxial layer 72 is isolated by the oxide insulating film 73. .

Next, a base lead electrode 74 made of polycrystalline silicon containing impurities is formed, and then a p-type external base region 75b is formed by impurity diffusion from the base lead electrode 74.

Next, the side wall of the base lead-out electrode 74,
After oxidizing the substrate surface in the region surrounded by the side wall to form an oxide film (not shown), impurity ions are implanted through this oxide film to form the p-type intrinsic base region 75a.

Next, after forming a side wall spacer 77 on the side wall of the base lead electrode 74, the oxide film formed on the substrate surface in the region surrounded by the side wall spacer 77 is removed.

Next, an emitter extraction electrode 79 made of a polycrystalline silicon layer containing n-type impurities is formed, and then an n-type emitter diffusion layer 78 is formed by impurity diffusion from the emitter extraction electrode 79. As a result, the base region and the emitter region can be formed in a self-aligned manner, and a mask for forming the emitter becomes unnecessary. Therefore, the element size can be reduced by the margin of mask alignment, and the integration degree and operation speed of the LSI can be improved.

Finally, the emitter electrode 80 and the base electrode 8
1, the collector electrode 82 is formed and completed.

By the way, in this type of bipolar transistor, the collector region (n-type intrinsic base region 75
The n-type collector epitaxial layer 72 under a is n ^−.
It is connected to the collector electrode 82 via the mold embedding layer 71 and the collector epitaxial layer 72.

That is, the conventional bipolar transistor has a structure in which a lateral portion 83 of the n ^-- type buried layer 71 (a simple current path which does not perform active operation) which does not directly contribute to device operation exists. .

However, this lateral portion 83 cannot be eliminated structurally, and it is difficult to miniaturize the lateral portion 83. Therefore, it is difficult to further increase the speed with the conventional structure. .

[0012]

As described above, in the conventional bipolar transistor, the lateral portion of the buried layer, which does not directly contribute to the device operation, cannot be eliminated structurally, and the speed is further increased. There was a problem that it was difficult.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a bipolar transistor which has an improved element structure and operates at a higher speed than ever before.

[0014]

In order to achieve the above object, a bipolar transistor of the present invention is formed on an emitter layer formed on the surface of a semiconductor substrate and on the semiconductor substrate so as to surround the emitter layer. An emitter extraction electrode that is in contact with the emitter layer and has a recess on the emitter layer; a base layer that is at least partially formed on the emitter layer in a recess region of the emitter extraction electrode; And a collector layer formed on the base layer in the region.

[0015]

According to the present invention, since the collector layer is not formed in the semiconductor substrate as in the prior art but is formed on the base layer on the semiconductor substrate, the buried layer serving as a current path for the collector current is formed. The layer becomes unnecessary and the collector current can be taken out without going through the buried layer. Therefore, the embedded layer can be miniaturized as compared with the conventional one as much as it is unnecessary, and the speed can be increased.

Further, since the base layer and the collector layer can be formed in a self-aligned manner, the emitter / base junction area and the base / collector junction area can be reduced. Therefore, both the capacitance between the emitter and the base and the capacitance between the base and the collector can be reduced, and the speed can be increased.

Here, the base layer can be formed in a self-aligned manner, for example, by an epitaxial method using the emitter layer in the region surrounded by the emitter extraction electrode as a base.

The collector layer can be formed in a self-aligned manner by, for example, forming a base layer and then burying a conductive film in a region surrounded by the emitter extraction electrode.

[0019]

Embodiments will be described below with reference to the drawings.

1 and 2 show an n according to an embodiment of the present invention.
FIG. 6 is a process drawing showing the manufacturing method of the pn-type bipolar transistor.

First, as shown in FIG. 1A, a high-concentration n ⁺ -type diffusion layer to be the n-type emitter diffusion layer 3 is formed on the p-type silicon substrate 1 by using a well-known diffusion technique. Next, the n ⁺ type diffusion layer is insulated and separated by the oxide insulator 2 to form the n type emitter diffusion layer 3.

Next, after depositing a polycrystalline silicon film containing an n-type impurity to be the emitter extraction electrode 4 on the entire surface, an oxide film 5 is deposited on this polycrystalline silicon film. Next, the oxide film 5 and the polycrystalline silicon film are patterned into a predetermined shape by using a photolithography technique to form an emitter extraction electrode 4.

As shown in the plan view of FIG. 1A, the emitter extraction electrode 4 is formed so as to surround the n-type emitter diffusion layer 3. However, the emitter extraction electrode 4 has a cut line and n The type emitter diffusion layer 3 is not completely surrounded.

Next, as shown in FIG. 1B, after depositing a nitride film to be the sidewall spacers 6 on the entire surface, this nitride film is anisotropically etched to form a nitride film on the sidewall of the emitter extraction electrode 4. Are left, and the side wall spacers 6 are formed. Depending on the lateral dimension of the side wall spacer 6, the emitter-base junction area, the base
The size of the collector junction area is determined.

Then, by epitaxial growth, a p-type base layer 7 made of a p-type silicon crystal layer is formed on the exposed surface of the n-type emitter diffusion layer 3 in the region surrounded by the emitter extraction electrode 4 and the sidewall spacer 6. Selectively formed. Here, in order to form the p-type silicon crystal layer, for example, diborane (B ₂ H ₆ ) may be mixed at a predetermined pressure, temperature, and gas flow rate during epitaxial growth.

Next, as shown in FIG. 2A, an interlayer insulating film 8 is deposited on the entire surface, a contact hole is opened in the region of the p-type base layer 7, and then an n-type collector layer is formed in this contact hole. A polycrystalline silicon layer to be 9 is embedded. Then, after implanting arsenic or phosphorus ions into this polycrystalline silicon layer, heat treatment is performed to form an n-type collector layer 9.

Here, instead of the polycrystalline silicon layer ion-implanted with arsenic or phosphorus, a polycrystalline silicon layer already doped with arsenic or phosphorus may be used. Further, instead of polycrystalline silicon, an epitaxial silicon layer doped with arsenic or phosphorus may be used.

Finally, as shown in FIG. 2B, the emitter extraction electrode 4, the p-type base layer 7, and the n-type collector layer 9 are formed.
After the interlayer insulating film 8 on the region of is etched to open a contact hole, the collector electrode 10 and the emitter electrode 1 are formed.
1, the base electrode 12 is formed and completed.

According to the manufacturing method described above, FIG.
In this step, the p-type base layer 7 is formed in a self-aligned manner and the emitter-base junction area is reduced, so that the emitter-base capacitance can be reduced as in the conventional case.

Further, in the step of FIG. 2A, unlike the conventional case, the n-type collector layer is formed in a self-aligned manner, and the base-collector junction area becomes small, so that the base-collector capacitance is also small. it can.

Therefore, according to the manufacturing method of this embodiment, the capacitance between the base and the collector can be reduced as compared with the conventional method, so that the bipolar transistor can be manufactured at a higher speed than the conventional method.

In addition, the bipolar transistor manufactured according to the manufacturing method of the present embodiment has the n-type collector layer 10
However, it is formed on the p-type base layer 7 on the p-type silicon substrate 1 instead of being formed in the semiconductor substrate as in the conventional case.

Therefore, the buried layer serving as a current path for the collector current is not required, and the collector current can be directly taken out from the collector electrode 10 without passing through the buried layer. Therefore, the embedded layer can be miniaturized as compared with the conventional one, and the speed can be increased.

Thus, according to this embodiment, the base-collector capacitance is reduced, the cutoff frequency is increased, and the collector current can be directly taken out from the collector electrode without the buried layer. , The operating speed can be greatly increased.

FIG. 3 shows ECL (Emitter Coupled Logic).
Is known as a logic circuit, in which an emitter-coupled bipolar transistor is used.

FIG. 4A is a sectional view showing the structure of the emitter coupling portion when the bipolar transistor of the above embodiment is used in this circuit. When the bipolar transistor of the above embodiment is used, the emitters can be easily coupled to each other, and the emitters can be coupled in one element isolation region, and the area of the entire circuit can be reduced.

On the other hand, FIG. 4B is a sectional view showing the structure of the emitter coupling portion when the conventional bipolar transistor shown in FIG. 5 is used. When the conventional bipolar transistor is used, the emitter cannot be coupled unless two element isolation regions are used, so that the circuit area is significantly increased.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the p-type silicon layer was used as the p-type base layer 7, but instead of this,
You may use a SiGe layer. The SiGe layer is formed, for example, by monogermane (GeH ₄ ) at the time of forming the silicon layer.
Should be introduced.

In addition, various modifications can be made without departing from the scope of the present invention.

[0040]

As described above in detail, according to the present invention, the collector current can be taken out without passing through the buried layer, and further, the emitter-base capacitance and the base-collector capacitance can be reduced. It is possible to realize a bipolar transistor that operates at higher speed.

[Brief description of drawings]

FIG. 1 is a process diagram of a first half showing a method for manufacturing an npn-type bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a second half process chart showing a method for manufacturing an npn-type bipolar transistor according to an embodiment of the present invention.

FIG. 3 is an equivalent circuit showing the configuration of ECL.

FIG. 4 is a diagram showing a comparison between an emitter-coupled portion of an ECL using a bipolar transistor according to the present invention and that used in a conventional bipolar transistor.

FIG. 5 is an element cross-sectional view showing the structure of a conventional bipolar transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate 2 ... Oxide insulator 3 ... N-type emitter diffusion layer 4 ... Emitter extraction electrode 5 ... Oxide film 6 ... Sidewall spacer 7 ... P-type base layer 8 ... Interlayer insulation film 9 ... N-type collector layer 10 ... Collector electrode 11 ... Emitter electrode 12 ... Base electrode

Claims (1)

[Claims] 1. An emitter layer formed on a surface of a semiconductor substrate, and an emitter lead formed on the semiconductor substrate so as to surround the emitter layer, contacting the emitter layer, and having a recess on the emitter layer. An electrode; a base layer at least partially formed on the emitter layer in the recessed region of the emitter extraction electrode; and a collector layer formed on the base layer in the recessed region. Characteristic bipolar transistor.