JPH03126229A - Transistor - Google Patents
TransistorInfo
- Publication number
- JPH03126229A JPH03126229A JP26584089A JP26584089A JPH03126229A JP H03126229 A JPH03126229 A JP H03126229A JP 26584089 A JP26584089 A JP 26584089A JP 26584089 A JP26584089 A JP 26584089A JP H03126229 A JPH03126229 A JP H03126229A
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter
- base
- resistor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000087 stabilizing effect Effects 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005299 abrasion Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、エミッタに直列のエミッタバラスト抵抗を有
し、またベース・エミッタ間に安定化抵抗を存するトラ
ンジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transistor having an emitter ballast resistor in series with the emitter and a stabilizing resistor between the base and emitter.
パワートランジスタにおいて、半導体基板全面に分散し
て配置されるエミッタ電極に流れるｉｔ流の局所集中を
防ぎ安全動作領域を広げるため、エミッタに直列にエミ
ッタバラスト抵抗を接続される。エミッタバラスト抵抗
を形成する方法には、例えば書籍「半導体ハンドブック
」 （オーム社。In a power transistor, an emitter ballast resistor is connected in series to the emitter in order to prevent local concentration of the IT current flowing to the emitter electrode, which is distributed over the entire surface of the semiconductor substrate, and to widen the safe operation area. For example, the book "Semiconductor Handbook" (Ohmsha) describes how to form an emitter ballast resistor.
昭和５２年発行）に記載されているような次の方法があ
る。第２図（４）、 （ｂ）に示すのは、コレクタ層ｌ
に接するベース領域ｚ内に形成されたエミッタ拡散層３
内の抵抗３１を利用するものである。ベース層２にはベ
ース電極４が、エミツタ層３にはエミッタ電極５がそれ
ぞれ酸化膜６の開口部で接触するが、エミツタ層３の上
にさらに補助電極５１が設けられのるで、電極５．５１
の間の拡散層３の抵抗３１がエミッタバラスト抵抗とな
る。第３図に示すものは、エミツタ層３の表面に接触す
るアルミニウム蒸着膜５との接触抵抗３２を利用したも
のである。There is the following method as described in ``Published in 1972''. What is shown in FIG. 2 (4) and (b) is the collector layer l.
An emitter diffusion layer 3 formed in the base region z in contact with
This utilizes the resistor 31 inside. A base electrode 4 contacts the base layer 2 and an emitter electrode 5 contacts the emitter layer 3 through the opening of the oxide film 6. However, since an auxiliary electrode 51 is further provided on the emitter layer 3, the electrode 5 .51
The resistance 31 of the diffusion layer 3 between the two becomes an emitter ballast resistance. The one shown in FIG. 3 utilizes the contact resistance 32 between the aluminum vapor deposited film 5 and the surface of the emitter layer 3.
第４図に示すものは、エミッタ電極５はエミツタ層３と
直接接触せず、酸化膜６の上に形成されたニクロムなど
の蒸着抵抗７を介して接触するものである、そのほか、
第５図に示すようにエミッタ拡散層３と同一導電型であ
るがそれより浅い不純物拡散層３３からなる抵抗３４を
利用し、これを介してエミッタ電極５と接続する特開昭
６３−２８８０６３号公報で公知の方法もある。In the case shown in FIG. 4, the emitter electrode 5 does not come into direct contact with the emitter layer 3, but rather through a vapor deposited resistor 7 made of nichrome or the like formed on the oxide film 6.
As shown in FIG. 5, a resistor 34 made of an impurity diffused layer 33 having the same conductivity type as the emitter diffused layer 3 but shallower than that is used, and is connected to the emitter electrode 5 through this. There are also methods known in publications.
一方、第６図に示すように、トランジスタ２１にはエミ
ッタバラスト抵抗２２のほかに、コレクタ・エミッタ間
耐圧の安定化のためにベース・エミッタ間に抵抗２３が
接続される。この抵抗２３は、第７図にｎｐｎ）ランジ
スタを例として示すように、ベース領域２の表面部にエ
ミツタ層３と同一導電型のｎ型領域８をそれぞれハンチ
ングしたように形成し、その−＠８１を酸化ＷＸ６を貫
通してベース電極４と接触させ、他端８２を酸化膜６を
貫通してエミッタ電極５と接触させることにより形成す
る。On the other hand, as shown in FIG. 6, in addition to the emitter ballast resistor 22, a resistor 23 is connected between the base and emitter of the transistor 21 in order to stabilize the breakdown voltage between the collector and emitter. This resistor 23 is formed by hunting n-type regions 8 of the same conductivity type as the emitter layer 3 on the surface of the base region 2, as shown in FIG. 7 using an npn transistor as an example. 81 is formed by penetrating the oxide WX 6 and contacting the base electrode 4 , and the other end 82 is formed by penetrating the oxide film 6 and contacting the emitter electrode 5 .
しかしながら、第７図に示すようにｎ型抵抗領域８を設
けると、この領域５とその直下のベース領域２．コレク
タ領域１とでｎｐｎ ）ランジスタ構造が形成され、特
にそのエミッタを極５への引出し側に近い領域、すなわ
ち＃Ａ３２に近い領域はエミッタとして強く働いてしま
うことになる。他端３１のベース電極４への引出し側に
近い領域は、エミッタ電流が領域３５の抵抗を介してエ
ミッタに流れるためエミッタ動作は弱い、このため、端
３７に近いｆＩＩｌ域で形成されるトランジスタは、第
３図で示した方法によりエミッタバラスト抵抗が備えら
れない限りエミッタバラスト抵抗で保護されないので、
安全動作領域が最も低くなり、この部分で破壊し、半導
体装置の所望の安全動作領域が得られないという欠点が
あった。However, if an n-type resistance region 8 is provided as shown in FIG. 7, this region 5 and the base region 2. An npn) transistor structure is formed with the collector region 1, and in particular, the region close to the side where the emitter is drawn out to the pole 5, that is, the region close to #A32, functions strongly as an emitter. In the region near the extraction side of the other end 31 to the base electrode 4, the emitter operation is weak because the emitter current flows to the emitter via the resistance of the region 35. Therefore, the transistor formed in the fIIl region near the end 37 is , unless an emitter ballast resistor is provided by the method shown in Figure 3, it will not be protected by an emitter ballast resistor, so
There is a drawback that the safe operating area is the lowest and the semiconductor device is destroyed at this portion, making it impossible to obtain the desired safe operating area of the semiconductor device.
本発明の目的は、ベース・エミッタ間安定抵抗としてベ
ース饋域内に設けられる他導電形の抵抗領域に基づく破
壊を防止し、エミッタバラスト抵抗により高められた安
全動作領域を狭めることのないトランジスタを提供する
ことにある。An object of the present invention is to provide a transistor that prevents destruction due to a resistance region of another conductivity type provided in the base region as a stable resistance between the base and emitter, and does not narrow the safe operation area increased by the emitter ballast resistance. It's about doing.
（！１１Ｎを解決するための手段〕
上記の目的を達成するために、本発明は、第−導電形の
ベース領域とその表面部に選択的に形成された第二導電
形のエミッタ領域を備え、ベース電極がベース領域に、
エミッタ電極がエミッタ領域に連結されたエミッタ領域
より浅いエミッタバラスト抵抗領域に接続され、またベ
ース電極およびエミッタ電極がベース領域の表面部に選
択的に形成された第二導電形の安定化抵抗領域の両端に
もそれぞれ接続されるトランジスタにおいて、安定化抵
抗領域の少なくともエミッタ電極に接続される端に近い
部分がエミッタバラスト抵抗領域と同じ深さであるもの
とする。(Means for solving !11N) In order to achieve the above object, the present invention includes a base region of a first conductivity type and an emitter region of a second conductivity type selectively formed on the surface thereof. , the base electrode is in the base region,
The emitter electrode is connected to an emitter ballast resistor region shallower than the emitter region connected to the emitter region, and the base electrode and the emitter electrode are selectively formed on the surface of the base region. In the transistors connected to both ends, at least a portion of the stabilizing resistance region close to the end connected to the emitter electrode is assumed to have the same depth as the emitter ballast resistance region.
安定化抵抗領域のエミッタ電極に接続される端に近い部
分が、エミッタバラスト抵抗と同じ浅い拡散領域となっ
て高砥抗となるため、安定化抵抗領域、ベース領域およ
びコレクタ領域からなるトランジスタへのエミッタバラ
スト抵抗の機能が付加され、このトランジスタにおける
破壊による安全動作領域が狭くなるのを防ぐ。The part of the stabilizing resistor region near the end connected to the emitter electrode becomes a shallow diffusion region similar to the emitter ballast resistor and has high abrasion resistance. The function of an emitter ballast resistor is added to prevent the safe operation area from narrowing due to breakdown in this transistor.
（実施例〕
第１図は本発明の一実施例を示し、第５図、第７図と共
通の部分には同一の符号が付されている。(Embodiment) FIG. 1 shows an embodiment of the present invention, and parts common to FIGS. 5 and 7 are given the same reference numerals.
この場合、ｎ型の安定化抵抗ｎ域８は、エミッタ拡散領
域３と同じ深さの領域８３とエミッタバラスト抵抗領域
となる浅い拡散層３３と同じ深さの領域８４とからなる
。このようなトランジスタは、ｎ型シリコン基板に不純
物を拡散してｐ型のベース領域を形成したのち、その表
面部に深い不純物拡散によってｎ型のエミッタ領域３お
よび安定化抵抗領域８の深いｇ域８３を形成する０次い
で、再びベース領域の表面部に浅い不純物拡散を行い、
エミッタ領域３を連結するエミッタバラスト抵抗領域３
３と安定化抵抗領域８の浅い領域８４を形成する。In this case, the n-type stabilizing resistance n region 8 consists of a region 83 having the same depth as the emitter diffusion region 3 and a region 84 having the same depth as the shallow diffusion layer 33 serving as the emitter ballast resistance region. In such a transistor, impurities are diffused into an n-type silicon substrate to form a p-type base region, and then impurities are deeply diffused into the surface of the base region to form an n-type emitter region 3 and a deep g region of the stabilizing resistance region 8. 83 is formed. Next, shallow impurity diffusion is performed again on the surface of the base region.
Emitter ballast resistance region 3 connecting emitter regions 3
3 and a shallow region 84 of the stabilizing resistance region 8 is formed.
このあと、表面を覆う酸化膜６にコンタクトホール４１
，４２，５１．５２を開け、ベース電極４をコンタクト
ホール４１でベース領域２と、またコンタクトホール４
２で抵抗６１ 埴８３の端８工と接触させ、エミッタ電
極５をコンタクトホール５１でエミッタバラスト抵抗領
域３３の中央に接触させ、またコンタクトホール５２で
抵抗領域８４の端８２と接触させる。これにより、安定
化抵抗領域８は、その両＄８１．８２ テベースを極４
およびエミッタ電極と接続されることになる、これによ
ってエミッタ電極５に近い抵抗領域８のトランジスタ動
作が抑制される。After this, a contact hole 41 is formed in the oxide film 6 covering the surface.
, 42, 51, and 52 are opened, and the base electrode 4 is connected to the base region 2 through the contact hole 41, and also through the contact hole 4.
2, the emitter electrode 5 is brought into contact with the center of the emitter ballast resistance region 33 through the contact hole 51, and is brought into contact with the end 82 of the resistance region 84 through the contact hole 52. This allows the stabilizing resistor region 8 to connect its two bases to pole 4.
and the emitter electrode, thereby suppressing the transistor operation of the resistive region 8 near the emitter electrode 5.
第８図は別の実施例を示し、安全動作領域８をすべてエ
ミッタバラスト抵抗領域となる拡散層３３と同時に形成
できる浅いｎ型拡散層としてトランジスタ動作を抑制し
たものである。FIG. 8 shows another embodiment in which the transistor operation is suppressed by forming the entire safe operation region 8 as a shallow n-type diffusion layer that can be formed simultaneously with the diffusion layer 33 which becomes the emitter ballast resistance region.
本発明によれば、ベース・エミッタ間の基板内に内蔵さ
れた安定化抵抗の領域にさらにより高い抵抗を挿入する
ことにより、この抵抗に安定化領域とその直下のベース
領域、コレクタ領域によって形成される寄生トランジス
タのエミッタバラスト抵抗の機能を持たせる。これによ
って安全動作領域が広がって破壊を防止することができ
る。しかも、この抵抗は本来のエミッタバラスト抵抗と
同時に形成できるため、製造工程の複雑化を招くことが
ない。According to the present invention, by inserting an even higher resistance into the region of the stabilizing resistor built into the substrate between the base and emitter, the resistor is formed by the stabilizing region, the base region immediately below it, and the collector region. It has the function of an emitter ballast resistor for the parasitic transistor. This expands the safe operation area and prevents damage. Furthermore, since this resistor can be formed at the same time as the original emitter ballast resistor, the manufacturing process does not become complicated.
第１図は本発明の一実施例のトランジスタの断面図、第
２図、第３図、第４図、第５図はそれぞれトランジスタ
のエミッタバラスト抵抗の異なる例を示し、第２図、第
４図のうち（ａｌは平面図、（ｂ）は断面図、第３図は
斜視図、第５図は断面図、第６図は本発明の実施される
トランジスタの等価回路図、第７図は安定化抵抗を有す
るトランジスタを示し、そのうち（ａｌは平面図、山）
は断面図、第８図は本発明の別の実施例のトランジスタ
の断面図である。
１：コレクタ領域、２：ベース領域、３：エミッタ領域
、３３：エミッタバラスト抵抗領域、４：ベース電極、
５：エミッタ電極、８：安定化抵抗第２図
第１図
第４図
第５図FIG. 1 is a cross-sectional view of a transistor according to an embodiment of the present invention, and FIGS. Among the figures, (al is a plan view, (b) is a sectional view, FIG. 3 is a perspective view, FIG. 5 is a sectional view, FIG. 6 is an equivalent circuit diagram of a transistor in which the present invention is implemented, and FIG. 7 is a Shows a transistor with a stabilizing resistor, of which (al is a plan view, a mountain)
is a cross-sectional view, and FIG. 8 is a cross-sectional view of a transistor according to another embodiment of the present invention. 1: Collector region, 2: Base region, 3: Emitter region, 33: Emitter ballast resistance region, 4: Base electrode,
5: Emitter electrode, 8: Stabilizing resistor Figure 2 Figure 1 Figure 4 Figure 5
Claims (1)
成された第二導電形のエミッタ領域を備え、ベース電極
がベース領域に、エミッタ電極がエミッタ領域に連結さ
れたエミッタ領域より浅いエミッタバラスト抵抗領域に
接続され、またベース電極およびエミッタ電極がベース
領域の表面部に選択的に形成された安定化抵抗領域の両
端にもそれぞれ接続されるものにおいて、安定化抵抗領
域の少なくともエミッタ電極に接続される端に近い部分
がエミッタバラスト抵抗領域と同じ深さであることを特
徴とするトランジスタ。1) A base region of a first conductivity type and an emitter region of a second conductivity type selectively formed on its surface, shallower than the emitter region in which the base electrode is connected to the base region and the emitter electrode is connected to the emitter region. At least the emitter electrode of the stabilizing resistor region is connected to the emitter ballast resistor region, and the base electrode and the emitter electrode are respectively connected to both ends of the stabilizing resistor region selectively formed on the surface of the base region. A transistor characterized in that the part near the end connected to the emitter ballast has the same depth as the resistor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26584089A JPH03126229A (en) | 1989-10-12 | 1989-10-12 | Transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26584089A JPH03126229A (en) | 1989-10-12 | 1989-10-12 | Transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03126229A true JPH03126229A (en) | 1991-05-29 |
Family
ID=17422797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26584089A Pending JPH03126229A (en) | 1989-10-12 | 1989-10-12 | Transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03126229A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5374844A (en) * | 1993-03-25 | 1994-12-20 | Micrel, Inc. | Bipolar transistor structure using ballast resistor |
-
1989
- 1989-10-12 JP JP26584089A patent/JPH03126229A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5374844A (en) * | 1993-03-25 | 1994-12-20 | Micrel, Inc. | Bipolar transistor structure using ballast resistor |
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