JPS60196970A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain high hFE easily by forming another conduction type emitter region and collector region shaped in a semiconductor region while being isolated in the lateral direction and another conduction type low concentration region shaped to the base of the emitter region. CONSTITUTION:A P type region 5 formed in concentration lower than an emitter region 6-1 and size deeper than the region 6-1 is added to the inside of the emitter region 6-1 in order to reduce the injection of charges from the base of the emitter region 6-1. The P type region 5 is formed previously before shaping the emitter region 6-1 and a collector region 6-2. Charges are hardly injected to a base region from the base of the emitter region 6-1, and high hFE is obtained by the reduction of base currents and reactive currents flowing through a P type silicon substrate 1. A lateral type PNP transistor having high hFE is acquired, and the method is available for improving characteristics such as the low distortion factor of a power IC, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to lateral transistors, and more particularly to lateral transistors with high current amplification factors (referred to as HPG).

Generally, NpN in bipolar integrated circuits (ICs)
The mixed use of ) transistors and PNP) transistors not only facilitates level shifting and phase inversion, increases the degree of freedom in design, and simplifies the circuit configuration, but also allows PNP) transistors to be used as loads for NPN) transistors. It can be used as a consumable cylinder.

It offers many advantages such as reduced force and increased stacking density. There is a horizontal PNP) transistor that can be easily introduced.

(Prior Art) Horizontal PNP transistors are usually fabricated by simultaneously forming an emitter and a collector using the base diffusion of a vertical PNP transistor, as shown in a schematic cross-sectional view in Figure 1. There is. After forming an N-type high concentration buried layer 2 on a 2M silicon substrate 1, an N-type evixial layer 3 is grown. This epitaxial layer 3 is separated into island-like regions by a P-type isolation layer 4, and becomes the base region of a lateral PNP transistor. P-type impurities are diffused into the island region of the epitaxial layer 3 to form an emitter Ig region 6-1 and a collector region 6-2.
and are formed at the same time. This impurity diffusion is vertical NpN)
It is formed at the same time as the base diffusion of the transistor. Further, an N-type impurity is diffused into the island-like region of the epitaxial layer 3 to form a base extraction region 7. This N-type impurity diffusion is formed using emitter diffusion of a vertical NPN transistor. The surface of the epitaxial layer 3 is covered with a silicon dioxide film 8, and an emitter electrode 9, a collector electrode 10, and a base electrode 11 are formed through the openings in the silicon dioxide film 8. These electrodes 9, 10.11 are
After photoetching the silicon dioxide film 8, aluminum or the like is deposited to form the silicon dioxide film 8.

The emitter electrode IE includes a lateral component IEL injected into the base from the side of the emitter region 6-1, and an emitter chain acid 6-1.
In the structure shown in FIG. 1, part of the vertical component Igv of the emitter current flows into the P-type silicon substrate 1 and becomes a reactive current. The rest becomes base current due to hole recombination in the base region. Therefore, in such a structure, there is a large amount of reactive current, and high hyg cannot be expected.

In recent years, requirements have become stricter regarding the characteristics of PNP transistors. Particularly in power ICs, etc., one of the requirements for improving characteristics such as lower distortion and simplifying the circuit configuration is to use a PNP transistor with a high hpz equivalent to an NpN transistor, at least in the output stage. has been done. Conventional horizontal PNP as shown in Figure 1)
For transistors, the manufacturing process is set to be optimal for NpN transistors.
The requirements for a PNP transistor cannot be fully satisfied.

(Object of the Invention) An object of the present invention is to provide a lateral transistor which can easily obtain high hrg by eliminating such drawbacks.

(Structure of the Invention) According to the present invention, a semiconductor region of one conductivity type, an emitter region and a collector region of another conductivity type formed laterally separated in this semiconductor region, and a semiconductor region formed on the bottom surface of the emitter region. A semiconductor device having a low concentration region of another conductivity type is obtained.

(Embodiments of the Invention) The present invention will be described in detail below with reference to the drawings. Figure 2 is a schematic cross-sectional view of an embodiment of a horizontal PNP transistor according to the present invention.

The same parts as in the conventional example shown in FIG. 1 are given the same numbers and their explanation will be omitted. In order to reduce charge injection from the bottom of the emitter region 6-1, an emitter region 6-11 is formed before forming the collector region 6-2 inside the conventional emitter region 6-1.

(Effects of the Invention) According to this structure, the bottom surface of the emitter region 6-1 has a low concentration and is formed deeply.
Injection of charge from the bottom surface of the silicon substrate 1 into the base region is almost eliminated, the base current and the reactive current flowing through the P-type silicon substrate 1 are reduced, and a high hrE can be obtained.

The present invention has been described above with reference to typical embodiments.According to the present invention, a high hrE lateral PNP transistor can be obtained, which is useful for improving characteristics such as lowering the distortion rate of power ICs and the like.

It should be noted that the present invention is not limited to the above embodiments, and even if the polarity is changed, it does not depart from the scope of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing an example of a conventional semiconductor device;
FIG. 2 is a schematic sectional view showing an embodiment according to the present invention. 1...P-type silicon substrate, 2...N-type high concentration buried layer, 3...N-type epitaxial layer,
4...Pff1 separation layer, 5...P type low concentration emitter region, 6-1...P type emitter region, 6-2...P type Collector area, 7...
... N-type base electrode extraction region, 8 ... silicon oxide film, 9 ... emitter electrode, 10 ...
... Collector electrode, 11 ... Base electrode.

Claims (1)

[Claims] a semiconductor region of one conductivity type; a first region of opposite conductivity type formed in the semiconductor region; 2 region and the part of the semiconductor region in contact with the bottom surface of the flute 1 region at a lower concentration than the first @ region.
11. A semiconductor device comprising a third region of a mold.