JPS60144962A - Monolithic integrated circuit - Google Patents

Abstract

PURPOSE:To make both N-P-N and P-N-P transistors having high performance coexist by gradually increasing impurity concentration on the collector side in the vicinity of a collector-base junction in the N-P-N transistor toward the direction of a substrate surface. CONSTITUTION:An N-P-N transistor (TR) is constituted by an N type collector region 304 formed to a P type substrate 301, a P type base region 305 and an N type collector region 306. A high-concentration N type region 309 is shaped with the object of reducing resistance parasitized to a collector electrode and a high-concentration P type region 311 with the object of reducing resistance parasitized to a base electrode respectively. On the other hand, a P-N-P TR is constituted by a collector region formed to the substrate 301, an N type base region 307 and a P type emitter region. A high-concentration P type region 312 is shaped to a collector electrode section and a high-concenstration N type region 310 to a base electrode section respectively with the object of reducing parasitic resistance. Accordingly, performance is improved in each TR, and both N-P-N and P-N-P TRs having high performance can be formed on the same substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a monolithic integrated circuit in which two types of bipolar transistors, PNP type and NPN type, coexist.

[Prior art]

The electrical mobility of minority carriers in the base region of an NPN transistor is much higher than that of a PNP transistor (approximately 2.5 times at an impurity level of 10/cr/l), which makes it possible to improve the performance of an NPN transistor. teeth,
PNP) is said to be easier than a transistor. Therefore, the development of processes and structures for bipolar type monolithic integrated circuits (hereinafter referred to as IC) has focused on improving the performance of NPN (NPN) transistors. On the other hand, PNP transistors were not used at all, or even if they were actively used, they were often ones that were naturally produced along with the formation of high-performance NPN transistors.

Figure 1 shows high-performance NPs made using the oxide isolation method.
1 is a cross-sectional view of a conventional IC having an N transistor and a PNP transistor formed at the same time as the N transistor. In FIG. 1, the NPN transistor has a p-type substrate 1
01, and an n-type epitaxial region 104 whose periphery is surrounded by a silicon oxide layer 103. Collector area and IC
The basic configuration is a p-type base region 105 and an n-type emitter region 106, which are sequentially formed from the surface by a diffusion method or an ion implantation method. On the other hand, the PNP transistor has a p-type substrate 101e collector,
N-type epitaxial region 107't-base, p-type region 1 formed simultaneously with base region of NPN transistor
08 as an emitter. Furthermore, in order to reduce the resistance value parasitic to the electrodes, high concentration n-type regions 109 and 110 are provided directly under each electrode of the collector of the NPN transistor and the base of the PNP transistor. Highly doped p-type regions 111 and 112 are formed directly under each electrode. As each electrode of the NPN transistor and the PNP transistor, a conductor 114 such as metal or polysilicon is attached through an opening formed in an insulating film 113 extending over the IC surface. In the structure shown in FIG.
The diffusion profile of the n-type region 106, the diffusion profile of the n-type region 106, etc. are all set to optimize the hFE rfT+ breakdown voltage, etc. of the NPN transistor. For example, in order to obtain a high ft, the base length should be shortened, and the diffusion flow profile in the base region should be changed to collector base junction (hereinafter referred to as CB junction).
The impurity concentration is made to increase from the EB junction toward the emitter base junction (hereinafter referred to as EB junction), and the impurity concentration gradient of the emitter is also made to increase steeply from the EB junction toward the surface. On the other hand, for the PNP transistor, the n-type epitaxial region 107 becomes the base region.

Therefore, it is difficult to stably shorten the base length, and it is also impossible to create a concentration gradient in the base region, so it is not possible to obtain a high 7T.

For example, the thickness of the n-type epitaxial layer is 1 μm, NPN
In the IC structure shown in Figure 1, where the depth of the CB junction of the transistor is 0.2 μm and the depth of the emitter of the PNP transistor is about <0.2 μm, it is possible to obtain an fT of several GHz for the NPN transistor. Yes, but PN
P) For transistors, at most several tens of MH2L can be obtained.

In recent years, there has been a growing demand for both digital ICs and linear ICs to incorporate high-performance NPN) transistors and high-performance PNP) transistors together. FIG. 2 shows a circuit diagram as an example where it would be advantageous to incorporate a high performance PNP transistor with a high performance NPN transistor in the digital circuit presented in the 1980 Patent Application No. 141901. In Figure 2, the collector load resistance 1.几2 and signal (IN in the figure) input NPN)
The transistor Q1, the reference (Vf'L in the figure) input transistor Q1 and the constant current source 1 are the power supply Vl (!:
3 to 5 cm is added between V* to form a CML type gate. Transistor Q3, diode Dl, resistor s,
PNP transistor Q4 is an output buffer that drives external load Cs. Usually, a large-scale digital LSI is constructed by connecting together a large number of circuit blocks made using the circuit shown in FIG. 2 as a basic gate. At this time, Cs shown in FIG. 2 is the sum of the input capacitance of the next stage circuit block and the parasitic capacitance of the inter-block wiring. In large-scale digital LSIs, the capacitance Cs is smaller than the parasitic capacitance of transistors, resistors, etc.
becomes large, and the speed of charging and discharging this capacitance Cs almost determines the speed of the circuit.

The circuit has a characteristic that makes it possible to significantly shorten the discharge time of the capacitance Os when compared to a normal emitter 7 lowerer when a PNP transistor has a performance comparable to an NPN transistor. [Object of the Invention] An object of the present invention is to provide a monolithic integrated circuit that makes it possible to coexist high-performance PNP transistors and high-performance NPN transistors on the same IC.

[Structure of the invention]

The monolithic integrated circuit of the present invention is a monolithic integrated circuit in which a plurality of vertical PNP transistors and a plurality of vertical NPN transistors are formed on the surface of the same semiconductor substrate, in which at least one of the PNP transistor and the NPN transistor is formed. The impurity concentration on the collector side near the collector paste junction gradually increases toward the surface of the semiconductor substrate.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a sectional view of one embodiment of the present invention. FIG. 3 shows a case where a p-type substrate is used as a collector of a PNP transistor.

As shown in FIG. 3, the NPN transistor has a p-type substrate 3
n-type collector region 3041 and p-type collector region 305.01 sequentially formed by diffusion method or ion implantation method. The n-type emitter region 306 has a multilayer structure. Furthermore, a highly doped n-type region 309 is formed for the purpose of reducing the parasitic resistance of the collector electrode, and a highly doped p-type region 311 is formed for the purpose of reducing the parasitic resistance of the pace electrode by a diffusion method or an ion implantation method.

On the other hand, a PNP transistor has a p-type substrate as a collector region,
N-type space region 307°p-type emitter region 3 sequentially formed by diffusion method or ion implantation method
08. Further, a high concentration ml region 312 is provided in the collector electrode portion, and a high concentration n-type region 31 is provided in the pace electrode portion.
0 is formed for the purpose of reducing parasitic resistance. P.N.
The insulation isolation of the P and NPN transistors is performed by the silicon oxide layer 30.3, and the electrodes of each transistor are made of metal or polyester through the openings provided in the insulating film 313 extending over the IC surface. The fact that a conductor 314 such as silicon is attached is the same as in the conventional example shown in FIG.

In this embodiment, since the impurity concentration on the collector side near the collector paste junction of the NPN transistor is configured to gradually increase toward the surface of the semiconductor substrate, the NPN transistor
Formation of n-type collector region 304+p-type space region 3051 and n-type emitter region 306 of N transistor and i'N
P) The n-type space region 307+p-type emitter region 308 of the transistor can be formed by diffusion from the substrate surface, making it possible to optimize each transistor to achieve high performance. For example, the junction between the collector and the substrate in an NPN transistor.

The CB junction and EB junction are 4 μm and 1 μm from the surface, respectively.

If fT of about 1.5 GHz is possible at 0.6 μm, the CB junction in a PNP transistor.

Approximately 500 MHz can be obtained by setting the HB junction to a depth equal to or less than that of the NPN.

FIG. 4 shows a second embodiment of the present invention in which ni is deposited on a p-type substrate.
High performance NPN and PNP by stacking 1 epitaxial layer
A cross-sectional view of an IC when a transistor is created is shown. As shown in FIG. 4, the NPN transistor has a p-type substrate 40
a collector region consisting of a heavily doped n-type buried region 402 and an n-type epitaxial region 404 formed on I;
It is composed of a p-type base region 405 and an n-type emitter region 406, which are sequentially formed from the C surface by a diffusion method or an ion implantation method.

On the other hand, the PNP) transistor has a structure in which the impurity concentration on the collector side near the collector paste junction gradually increases toward the substrate surface, so it can be formed sequentially from the IC surface by a diffusion method or an ion implantation method. The type pace region 407 and the p-type emitter region 408 can now be optimized for higher performance. Furthermore, as in the first embodiment shown in FIG.
The collector electrode of the transistor and the base electrode of the PNP transistor have high concentration n-type regions 409 and 410 st7.
'cNPN) The base electrode of the transistor and the collector electrode of the PNP) transistor have high concentration diffusion regions 411.41
2 is formed. PNP.

Insulation isolation of NPN transistor is silicon oxide layer 403
What is being done is that the electrodes of each transistor are the insulating film extending over the IC surface.
This is similar to the embodiment. In this embodiment shown in FIG.
P? An n-type buried region 416 is placed directly under the p-type collector region of the transistor to lower the collector parasitic resistance. If the collector parasitic resistance can be high to some extent, this p
In this case, the same as the template may be used, but in the case of operating at a different potential, a structure can be adopted in which an n-type buried region is placed below the n-type buried region 416 so as to include the n-type buried region. Therefore, by adopting the structure of this embodiment, the widths of the base regions of both NPN and PNP transistors can be reduced similarly to the first embodiment.

It is possible to appropriately control the impurity concentration gradient, etc., and it is also possible to improve performance by lowering the collector parasitic resistance.

As shown in the above two embodiments, the IC according to the present invention has a vertical PNP transistor and a vertical NP transistor on the same semiconductor substrate.
A plurality of N transistors are formed respectively, and the PN
At least one of the P transistor and the NPN transistor has a structure in which the impurity concentration on the collector side near the collector base junction gradually increases in the direction of the surface of the semiconductor substrate.
The collector region of the transistor can be formed from the IC surface by diffusion or ion implantation. Therefore, it is possible to use a part of the p-type region having a uniform impurity concentration distribution as the collector of the PNP transistor, and to use an n-type region created in the part of the p-type region by diffusion or ion implantation as the collector of the NPN transistor. can.

Conversely, a part of the n-type region with a uniform concentration of impurity 1 is
The p-type region formed in the n-type region can be used as the collector of a PNP transistor. As a result, in both PNP and NPN transistors, the base region and emitter region are
It can be formed by diffusion from the surface or ion implantation, and is designed to improve performance and increase pace length.

Base region impurities etc. can be controlled.

Although the above embodiments have been described with reference to the case where the present invention is applied to a bipolar type IC, it is clear that the present invention can also be sufficiently applied to an IC in which bipolar transistors and MOS transistors are mixed.

〔Effect of the invention〕

As explained above, according to the present invention, a high-performance PNP) gingister and a high-performance NPN can be formed on the same semiconductor substrate.
) It is possible to coexist with transistors, and it can be effective in forming high-performance, large-scale digital L8 construction, etc., which are currently in demand.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional IC in which NPN) transistors and PNP l-
FIGS. 3 and 4 are cross-sectional views of embodiments of the present invention. 101.301.401...P-type substrate, 102
゜402...High concentration buried region, 103,30
3゜403...Silicon oxide layer, 104,40
4...N-type epitaxial region, 304°°°
-n Fil collector area, 105.305.405.
...p-type base region, 106,306,406.
""'n-type emitter region, 107.407=°=...n
Type epitaxial/diameter region, 307...N-type base region, 108,308 degrees 408...P-type emitter region, 109,110 degrees 309.310.409.4
10.--High concentration n-type region, 1111112,3
11.411.412...“high concentration p-genus region, 11
3,313,413°゛. °°°Insulating film, 1141314, 4i4...Conductor, 415..."p-type collector region, 416...
...P-type buried region s"1 + Vll...
・・Power supply, IN・・・・Input voltage, ■几・・・・
・Reference voltage, R, 3.几、・・・Resistance、QI、C2、C3・・・NPN) Transistor、Q、・・・PNP）Transistor %D1...
...Diode, C5...Load capacity. Congee f diagram 2 diagram 4

Claims (3)

[Claims] (1) In a monolithic integrated circuit in which a plurality of vertical PNP transistors and a plurality of vertical NPN transistors are formed on the same semiconductor substrate surface, a collector base junction of at least one of the PNP transistor and the NPN transistor A monolithic integrated circuit characterized in that the impurity concentration on the collector side in the vicinity gradually increases toward the surface of the semiconductor substrate. (2) The monolithic integrated circuit according to claim (1), wherein the transistor in which the impurity concentration on the collector side near the collector-base junction gradually increases toward the surface of the semiconductor substrate is an NPN transistor. (3) The monolithic integrated circuit according to claim (1), wherein the transistor in which the impurity concentration on the collector side near the collector-base junction gradually increases toward the surface of the semiconductor substrate is a PNP transistor.