JPH0222857A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a high-frequency characteristic by a method wherein an N-type base region is formed newly inside an N<-> type epitaxial layer and N-type source and drain regions whose concentration is lower than that of N<+> type source and drain regions are formed simultaneously so as to include the N<+> source and drain regions at their inside. CONSTITUTION:In a Bi-MOS integrated circuit device, a high-concentration N-type base region 8a is formed in a T-PNP transistor Q2. During the same process as this, first N-type source and drain regions 8b whose concentration is lower than that of N<+> type source and drain regions of an N-ch transistor Q3 and which are deeper than these regions are formed at their outside so as to include the regions at their inside. When a P-channel transistor Qa exists, its N-type well region is formed simulta neously in the same manner by utilizing a formation process of the N-type base region 8a; accordingly; it is possible to relax a concentration gradient at a junction face between a well region and source and drain regions in a MOS transistor. Accordingly, it is possible to realize the high breakdown strength of an N-channel transistor and a P-channel transistor. At the same time, it is possible to improve the punchthrough breakdown strength, a current characteristic of a grounded-emitter current amplification factor (hFE) and a frequency characteristic of the T-PNP transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a B1-MO3 integrated circuit device in which a bipolar transistor and a MOS transistor are formed on the same substrate. Regarding.

[Conventional technology]

The triple diffusion type PNP transistor (hereinafter referred to as T-PNP transistor) was developed as a high-performance vertical PNP transistor.
Since it has good complementarity with N transistor), it is analog
A digital coexistence type Bi-MO8$i'ifi circuit device has been developed and put into practical use.

FIG. 3 is a cross-sectional view showing an example of the structure of a conventional analog-digital coexisting B1-MO3 integrated circuit device including a triple-diffused PNP transistor. Here, Ql, Q2, and Ql are an NPN transistor, a T-PNP transistor, and an N-channel MOS transistor (hereinafter simply referred to as an Nch transistor), respectively, and a digital section is constituted by the Nch transistor Q1. The structure of this integrated circuit device is manufactured by the following method. First, N1 type buried layers 2a and 2b are selectively formed on a P- type silicon substrate 1, then P+ type buried layers 3a and 3b are selectively formed, respectively, and then an N- type epitaxial layer 4 is formed on the entire surface of the substrate. to grow. At this time, the P+ type buried layer 3a is made into a floating region by increasing outward diffusion into the N- type epitaxial waste 4. Next, T-PNP transistor Q2
P+ type collector region 5a and P+ type insulation isolation region 5
b are formed so as to be continuous with the P+ type buried layers 3a and 3b, respectively. Next, after forming the N+ type collector region 6 of the NPN transistor Q1 so as to be continuous with the N+ type buried layer 2a, the P type well region 7 of the Nch transistor Q3 is formed.
form. Next, after forming the P type base region 9 of the NPN transistor Qt, this NPN transistor Q1
P+ type base contact region 10a and T-PN
P” type emitter region 10b of P transistor Q2.

A p+ type collector contact region 10c is simultaneously formed in one diffusion process. Next, the NPN transistor Q1
N+ type emitter region 11a, N'' type collector contact region 1lb, N of T-PNP transistor Q2
After forming the + type base contact region 11c and the N+ type source and drain regions lid of the Nch transistor Q at the same time, the gate oxide film 12 of the Nch transistor Q3 is formed, and the insulating oxide film 13 is opened to form an aluminum electrode. The process is completed by providing wiring to each transistor.

[Problem to be solved by the invention]

In this manner, the conventional manufacturing method described above converts the N+ type source and drain regions 11d of the Nch transistor Q3 into NP
N+ type emitter region 11a of N transistor Q, N+
type collector contact region 11b and N+ type base contact region 11c of T-PNP transistor Q2
Since the source and drain regions 11d and the drain regions 11d are formed at high concentration and shallowly at the same time through a common diffusion process, the concentration gradient at the junction surface with the P-type well region 7 becomes steep, and the electric field strength near the drain is strengthened. However, it has the disadvantage of lowering the drain breakdown voltage.

In addition, since the base region of the T-PNP transistor Q3 is formed of low concentration N-type epitaxial M4, the bunch-through breakdown voltage of the formed T-PNP transistor Q3 is low, and the emitter common current amplification factor (hpE) is low. The disadvantage is that the current characteristics are also poor. In other words, in the low current region, the common emitter current amplification factor (hpE)
This causes an undesirable problem in that the linearity of The device has various drawbacks such as a small cutoff frequency (f↑) and poor high frequency characteristics.

In view of the above circumstances, an object of the present invention is to improve high frequency characteristics such as the source and drain breakdown voltage of a MOS transistor in a Bi-MO3 structure, the punch-through breakdown voltage of a triple diffused PNP transistor, the common emitter current amplification factor, and the cutoff frequency. It is an object of the present invention to provide a method for manufacturing a semiconductor device that allows the manufacturing of a semiconductor device.

[Means to solve the problem]

According to the present invention, there is provided a method for manufacturing a semiconductor device in which a triple diffusion type PNP transistor including a buried layer and an MO8 type transistor including a well region are formed adjacent to each other in an N-type epitaxial layer Jω on a P-type silicon substrate. , an N-type base region is newly formed in the N-type epitaxial layer forming the base of the triple-diffusion type PNP transistor, and an N-type well region of the MO3 type transistor or The structure includes simultaneously forming an N+ type source on the P type well region, an N type source surrounding the drain region, an N type source having a lower concentration than the drain region, and a train region.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIGS. 1(a) to 1(e) are manufacturing process diagrams of a Bi-MO3 integrated circuit device including a triple diffusion type PNP transistor showing one embodiment of the present invention. According to this embodiment, first, as shown in FIG. 1(a), a P-type silicon substrate 1 having a specific resistance of 1 to 100 Ω·1 is doped with, for example, arsenic (^S) or antimony (sb) to After selectively forming N+ type buried layers 2a and 2b of 40Ω/hole, for example, by doping with boron (B), P+ type buried layers 3a and 3b of 200 to 500Ω/hole are respectively formed, and then specific resistance A low concentration N″′ type epitaxial layer 4 of 0.5 to 2Ω·Ω is grown on the entire surface of the substrate. Here, the P+ type buried layer 3a is formed in the N1 type buried layer 2b, and the N− type epitaxial layer 4 is formed in the N1 type buried layer 2b. The outward diffusion into the layer 4 is increased to form a floating region.Next, as shown in FIG. 1(b), for example, boron ( B) respectively doped with T of 5-50Ω/mouth.
- The P+ type collector region 5a and the P+ type insulating isolation region 5b of the PNP transistor Q2 are respectively connected to the P+ type buried layer 3.
a and 3b, followed by NPN
The N+ type collector region 6 of the transistor Q1 is formed to be continuous with the N+ type buried layer 2a by doping, for example, with phosphorus (P) to a resistance of 5 to 50 Ω/hole, and the P type well region 7 of the Nch transistor Q3 is For example, it is formed with boron (B) doping to 3 to 5 Ω/hole.

Here, as shown in FIG. 1(C), the P-type well region 7
N-type first source and drain regions 8b of the N-channel transistor Q are formed therein at the same time as the N-type base region 8a of the T-PNP transistor Q2. This area 8a, 8
b is formed, for example, by phosphorus (P) doping to 1 to 3 Ω/gate. Then, the P-type base region 9 of the NPN transistor Ql is formed, for example, by doping with boron (B) to a resistance of 1 to 3 Ω/gate. Next, as shown in FIG. 1(d), the N type base region 8a of the T-PNP transistor Q2, the P+ type emitter region 10b in the P+ type collector region 5a, and the P+ type collector/contact region 10.
c and P in the P type base region 9 of the NPN transistor Q+.
+ type base contact regions 10a are formed at the same time, for example, by boron (B) doping with a resistance of 3 to 7 Ω/gate, and then N+ type emitters in the P type base region 9 and the N+ type collector region 6 of the NPN transistor Q1 are formed simultaneously. Region 11a and N+ type collector contact region 11b, N type base region 8a of T-PNP transistor Q2, N+ type base contact region 11c and N+ type second source and drain region 8b of Nch transistor Q3. For example, the source and drain regions 11d are
They are simultaneously formed at 3 to 7 Ω/port by doping with phosphorus (P). The rest is Nch transistor Q, gate oxide film 1
2 is formed to a thickness of 500 to 800 layers, and an insulating oxide film 13 is formed.
If the electrode wiring is provided by opening the
) as shown in NPN transistor Q1. An integrated circuit device having a Bi-MO3 structure including a T-PNP transistor Q2 and an Nch transistor Qq is obtained.

According to this embodiment, the source and drain regions of the NCh transistor have a two-layer structure with two different concentrations, and an N-type layer with a relatively low concentration is interposed at the interface with the P-type well. The concentration gradient at the junction between the region and the source and drain regions is more relaxed than that of the conventional structure.

FIG. 2 shows a Bi-
FIG. 2 is a cross-sectional view of an MO3 integrated circuit device. According to this embodiment, the Pch transistor Q4 is the T-PNP transistor Q
2 and Nch transistor Q3, the N-type well region 18c and the N-type first source and drain regions 8b of the Nch transistor Q3 are formed in the step of forming the N-type base region 8a of the T-PNP transistor Q2, respectively. are formed at the same time. That is, according to this embodiment, the Pch provided with the relatively high concentration N-type well region 8c
Transistor Q4 can be formed. Therefore, P
The + type source and drain regions 10d are connected to the P+ type emitter region 10b of the T-PNP transistor Q2, the P+ type collector/contact region 10c, and the NPN transistor Qt.
P+ type base contact region 10a (not shown)
Even if they are formed at the same time, the concentration gradient at the junction between the N-type well region 8C and the P+-type source/drain region 10d in the Pch transistor Q4 is more relaxed than in the conventional structure. According to this embodiment, a CMOS integrated circuit device can be obtained very easily since a Pch transistor can be formed without increasing the number of steps.
The -type epitaxial layer has an N-type well region with small concentration variations formed by ion implantation of, for example, phosphorus (P), so the advantage is that the threshold voltage can be easily controlled. has.

〔Effect of the invention〕

As explained in detail above, according to the present invention, B 1-
The MO3% product circuit device has a step of forming a relatively highly doped N-type base region in a T-PNP transistor, and also includes an N+-type source and drain region of an Nch transistor in the same step. An N-type first source and drain region with a lower concentration and deeper depth is formed on the outside of the N-type well region. Since they are formed simultaneously using the region formation process, the concentration gradient at the junction surface between the well region and the source and train regions in the MOS transistor can be alleviated. Therefore,
It is possible to increase the withstand voltage of each Nch and Pch transistor, and at the same time, it has achieved remarkable effects such as improving the punch-through withstand voltage of the T-PNP transistor, the current characteristics of the common emitter current amplification factor (hPE), and the frequency characteristics. It can be effective.

First, in MOS transistors, the concentration gradient at the junction between the source/drain region and the well region is gentler than before, and the electric field strength near the train is relaxed, so the source/drain breakdown voltage can be increased. It becomes possible to do so.

Next, in the T-PNP transistor, the base
The expansion of the depletion layer toward the base side at the collector junction is suppressed, increasing punch-through voltage. Also, the depletion layer at the emitter-base junction is smaller than before, reducing rejunction current in the depletion layer. Therefore, the linearity of the common emitter current amplification factor (hpt) increases. Furthermore, the base region immediately below the emitter region becomes highly concentrated and the influence of the Webster effect is alleviated, so that the maximum collector current (I c ---) increases. Furthermore,
The newly provided N-type base region has an impurity concentration gradient,
This acts as an accelerating electric field for the holes injected from the emitter, and if the same punch-through breakdown voltage is to be guaranteed, the epitaxial layer can be made thinner and the base width becomes smaller, so the cutoff frequency (1
ding) becomes larger. In other words, the high frequency characteristics are significantly improved.

[Brief explanation of the drawing]

1(a) to (e) are manufacturing process diagrams of a Bi-MO3 integrated circuit device including a triple diffusion type PNP transistor showing one embodiment of the present invention, and FIG. 2 is a manufacturing process diagram of a Bi-MO3 integrated circuit device according to another embodiment of the present invention. FIG. 3 is a cross-sectional view of a conventional Bi-MO9O9 integrated circuit device of a conventional analog-digital coexistence type including triple diffused PNP transistors. 1... P- type silicon substrate, 2a, 2b... N+ type buried layer, 3a, 3b... P+ type buried layer, 4... N-
type epitaxial layer, 5a...P+ type collector region,
5b... P+ type insulation isolation region, 6... N+ type collector region, 7... P type well region, 8a... N type base region, 8b... N type first source and drain region, 8
c...N type well region, 9...P type base region, 1
0a...P+ type base contact region, 10b...
・P+ type emitter region, 10c...P+ type collector・
Contact region, 10d...P+ type source, drain region, lla...N+ type emitter region, 111)...
・N+ type collector contact region, llc...N+
Type base contact area, lld...N''' type second
Source, train region, 12...gate oxide film, 13
...Insulating oxide film, Ql...NPN)-transistor,
Q2...T-PNP transistor, Q3...Nch
Transistor, Q4...Pch transistor.

Claims (1)

[Claims] A method for manufacturing a semiconductor device in which a triple diffusion type PNP transistor including a buried layer and a MOS type transistor including a well region are formed adjacent to each other in an N^- type epitaxial layer on a P type silicon substrate. PNP
Newly forming an N type base region in the N^- type epitaxial layer forming the base of the transistor,
N^+ on the N-type well region or P-type well region of the MOS transistor in the same process as the N-type base region.
1. A method of manufacturing a semiconductor device, comprising simultaneously forming the N-type source and drain regions each having a lower concentration than the N^+-type source and drain regions, which respectively surround the N-type source and drain regions.