JPH0369180B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a semiconductor device in which a bipolar transistor and a CMOS coexist on one semiconductor substrate.

[Prior art and its problems]

When a bipolar transistor and CMOS coexist on one semiconductor substrate, conventionally, as shown in the flowchart of Fig. 2, an n-buried layer 2 is provided on a part of the p-type Si substrate 1 (A), and then An n ^- layer 3 is epitaxially grown on a substrate 1, a p-isolation diffusion layer 4 is provided that reaches the p-substrate 1 from the surface of the n ^- layer 3, and each bipolar transistor is electrically isolated by a pn junction. In the n-channel MOSFET section, a p ^- well layer 5 is provided by ion implantation.
(B) Furthermore, in the bipolar part, in order to reduce the collector series resistance, an n ⁺ color diffusion layer 6 that reaches the n ⁺ buried layer 2 is provided, a p ⁺ base diffusion layer 7,
While an n ⁺ emitter diffusion layer 8 is provided, in the CMOS section, an n ⁺ source/drain diffusion layer 9 is provided in the region of the p ^- well layer 5, and a p ⁺ source/drain diffusion layer 10 is provided in other parts (C). Next, an emitter electrode 11, a base electrode 12, and a collector electrode 13 are provided on the n ⁺ emitter layer 8, p ⁺ base layer 7, and n ⁺ color layer 6, respectively, and an insulating film 15 is provided on the surface between the source and drain of the CMOS section. The bipolar transistor 21 and the n-channel
A bipolar CMOS semiconductor device is constituted by a MOSFET 22 and a p-channel MOSFET 23. However, in such a structure, in the n-channel MOSFET section 22, the p ^- well layer 5-
n ^- epitaxial layer 3 - p substrate 1, and in p channel MOSFET section 23, p ⁺ source/drain layer 10 - n ^- epitaxial layer 3 -
The p-substrate 1 constitutes a parasitic pnp transistor, and since the n ^- epitaxial layer 3 corresponding to the base has a low impurity concentration to maintain breakdown voltage, the h _FE of the parasitic pnp transistor
It had the disadvantage that it was large and latch-up occurred.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bipolar CMOS semiconductor device which can prevent latch-up due to a parasitic bipolar transistor in a CMOS section, while eliminating the above-mentioned drawbacks, and which eliminates the need to increase the number of manufacturing steps.

[Key points of the invention]

The present invention provides a bipolar transistor that coexists with CMOS, on a semiconductor substrate of a first conductivity type, a buried diffusion layer between an epitaxial layer of a second conductivity type and the substrate, and a buried diffusion layer between the buried diffusion layer and the epitaxial layer. A semiconductor device comprising a collector made of a collar layer connected to a surface, a base of a first conductivity type formed in an epitaxial layer, and an emitter of a second conductivity type formed in the base layer. Each of the P-channel transistor and N-channel transistor of the CMOS is provided with a second buried diffusion layer of a second conductivity type formed in the same process as the buried diffusion layer of the bipolar transistor;
The channel transistor includes a channel stopper layer of a second conductivity type that is formed in the same process as the collar layer of the bipolar transistor and connects the second buried diffusion layer and the surface of the epitaxial layer. The n-channel transistor is formed near the outside of the well layer of the first conductivity type in the same process as the collar layer, and the second buried diffusion layer connects the second buried diffusion layer and the surface of the epitaxial layer. The above object is achieved by each having a conductive type channel stopper layer.

[Embodiments of the invention]

The manufacturing process of an embodiment of a bipolar CMOS semiconductor device according to the present invention is shown in a flowchart in FIG.
Components common to those in FIG. 2 are given the same reference numerals. Figure 1A shows a bipolar transistor section and a CMOS p channel on a part of the p-type Si substrate 1.
The step of providing three n ⁺ buried layers 2 in each of the MOSFET part and the n ^{- channel} MOSFET part is shown in FIG.
Separated from CMOS section and further N-channel
In the MOSFET section, a step of forming a p ^- well layer 5 by ion implantation is shown. Figure 1C shows that the same process is performed when an n ⁺ color diffusion layer 6 is provided in the bipolar part.
An n ⁺ channel stopper diffusion layer 17 is provided to reach the n ⁺ buried layer 2 of the CMOS section, and at this time, the n channel MOSFET section is provided near the outside of the p ^- well layer 5 ^.
A channel stopper diffusion layer is provided.
Next, a step is shown in which an n ⁺ source/drain diffusion layer 9 is formed in the p ^- well layer 5 in the n-channel MOSFET section, and a p ⁺ source/drain diffusion layer 10 is formed in the epitaxial layer 3 in the p-channel MOSFET section. Furthermore, in the same way as in Figure 1D
An emitter electrode 11, a base electrode 12, and a collector electrode 13 are provided on the n ⁺ emitter layer 8, p ⁺ base layer 7, and n ⁺ color layer 6 of the npn transistor 21, respectively, and on the insulating film 15 between each source and drain of the CMOS section. A bipolar
A CMOS semiconductor device is constructed. This manufacturing process is similar to the conventional bipolar film shown in Figure 2.
It can be carried out using the same number of steps as the manufacturing process of CMOS semiconductor devices.

【Effect of the invention】

According to the present invention, in a bipolar/CMOS semiconductor device, by providing a buried layer and a channel stopper layer in a CMOS part in the same process as a buried layer and a collar layer in a bipolar part, the base region of a parasitic bipolar transistor in a CMOS part is By increasing the impurity concentration in the region surrounding the parasitic transistor, the h _FE of the parasitic transistor can be lowered, and as a result, latch-up can be prevented without increasing the number of steps, so the effect obtained is extremely large.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view sequentially showing the manufacturing process of an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the manufacturing process of a conventional example. 1: p-type Si substrate, 2: n ⁺ buried layer, 3: n ^- epitaxial layer, 4: p isolation layer, 5:
p ^- well layer, 6: n ⁺ color layer, 7: p ⁺ base layer,
8: n ⁺ emitter layer, 9: n ⁺ source/drain layer,
10: p ⁺ source/drain layer, 17: n ⁺ channel stopper layer.

Claims (1)

[Claims] 1 A bipolar transistor that coexists with CMOS has a buried diffusion layer between a second conductivity type epitaxial layer and the substrate on a first conductivity type semiconductor substrate, and a buried diffusion layer between the buried diffusion layer and the surface of the epitaxial layer. A bipolar transistor consisting of a collector made of a collar layer connecting the two, a base of a first conductivity type formed in an epitaxial layer, and an emitter of a second conductivity type formed in the base layer. The p-channel transistor and n-channel transistor of the CMOS are each provided with a second buried diffusion layer of a second conductivity type formed in the same process as the buried diffusion layer, and the p-channel transistor is a bipolar transistor. A channel stopper layer of a second conductivity type is formed in the same process as the collar layer and connects the second buried diffusion layer and the surface of the epitaxial layer, and the n-channel transistor includes a channel stopper layer of a first conductivity type. a channel stopper layer of the second conductivity type that is formed near the outside of the well layer of the mold in the same process as the collar layer and connects the second buried diffusion layer and the surface of the epitaxial layer; Bipolar and
CMOS semiconductor device.