JPS58216455A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To perform the microminiaturization of a C-MOS element and the increase in the breakdown strength of a linear bipolar element by forming a p<+> type buried region and a p<+> type region under a well region forming part of an n type semiconductor layer on a p type semiconductor substrate and in the vicinity of a boundary between the substrate to afford an element isolating region forming part and the semiconductor layer in the same step to reduce the resistance of the p type well region, thereby preventing a latchup phenomenon enabling to form an element isolating region. CONSTITUTION:When a p<+> type buried region 109 of high density which makes contact with a region 115 is formed on the bottom of a p type well region 115, a latchup phenomenon can be prevented, and the well region 115 which has an impurity profile with multiplex ion implantation for deciding the performance of an n-channel MOS transistor can be formed from the surface side. When a p<+> type region 108 is formed simultaneously with the step of forming the region 109 and a p type region 113 is formed simultaneously with the step of forming the region 115, an ultrafine p type isolation region 114 which can be effectively electrically isolated from an n-p-n type bipolar transistor and a C-MOS can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device with a composite structure in which a bipolar element and an 0MO8 element are coexisted on the same chip.

[Technical background of the invention]

BACKGROUND ART In recent years, integrated circuit technology has made remarkable progress, and composite devices that process analog and digital quantities simultaneously have become important, especially from the viewpoint of multifunctionality. For example, I”
L (Integrated Injection Lo
gic), etc., it has been made to coexist with a high-voltage linear transistor, and high performance has been achieved. There is still another possibility, MO8
The coexistence technology of devices, especially 0MO8 devices and bipolar devices, is attracting attention.

By the way, as a composite device in which a bipolar element and an 0MO8 element coexist, conventionally, Oki Electric Research & Development No. 114, Vo14B+No.2. shown in FIG. P39-P4
4 is known. That is, 1 in the figure is a p-type semiconductor substrate, and an n-type semiconductor layer 2 is provided on this substrate 1. This semiconductor layer 2 has island regions 4 separated by p-type isolation regions 3 that reach the surface of the substrate 1. ．． 42 is formed. An n-type buried region 51 is provided near the interface between the substrate 1 and the semiconductor layer 2 under the - side island region 41, and an n-type buried region 52 is provided near the interface between the substrate 1 and the semiconductor layer 2 under the other island region 420. is selectively provided, and a p-well region 6 is provided in a portion of the semiconductor layer 2 above the n+ type buried region 53.

One of the island regions 41 is provided with a p-type base region 7, an n+-type emitter region 8 located within the space region 7, and an n+-type collector extraction region 9.
An npn bipolar transistor is formed. Further, on the surface of the other island region 48 other than the well region 6, there are p-type source and drain regions 1 electrically isolated from each other.
0° 11 is provided, and the source and drain regions 10
．． An annular n-type channel region 12 is provided so as to surround the region 11 . On the surface of the p-well region 6, there are n+ type source and drain regions 1 electrically isolated from each other.
3.14 are provided, and an annular p+ type channel cut region 16 is provided so as to surround these regions 13.14. Further, the entire surface of the semiconductor layer 2 is covered with an oxide film 16. However, the above-mentioned p raw type source.

A thin dirt oxide film "'1*162" is formed on the region including between the drain regions 10 and 11 and on the region including between the n-type source and drain regions 13 and 14.Furthermore,
Island region 41 where npn pie era transistor is formed
The base region 7. is formed on the upper oxide film 16 through a contact hole. Emitter region 8 and collector extraction region 9
AI electrodes 17 to 19 are provided which are respectively connected to.

Also, the dirt oxide film 16sr16! Above is Alr-
) are provided with electrodes 20, 21, and an oxide film 16.
The p-type source is provided above through a contact hole,
Kl electrodes 22 to 25 connected to the drain region 10° 11 and the n-type source and drain regions 13 and 14 are provided.

In the manufacturing process of the composite device shown in FIG. 12, the p-type isolation region 3 and the p-well region 6 are formed in the same step.

[Problems with background technology]

However, the method for manufacturing the composite device shown in FIG. 1 has the following drawbacks.

That is, the layer resistance of the p-well region 6 is the same as that of the n-type buried region 5.
The parasitic npn based on the p-well region 6 in the pnpn thyristor structure causes the so-called Latchia, Zo phenomenon because it tends to increase due to the upward diffusion of
) Increase the current amplification factor of the transistor.

Furthermore, the p-well region 6 is a p-type isolation region 3.
Since it is formed in the same process as that of the semiconductor layer 2, it is necessary to form it by diffusion deeper than the thickness of the semiconductor layer 2. As a result, for example, if the depth of the p-well region 6 is reduced from the current 10 μm to 5 μm to 3 μm for the purpose of miniaturizing 0MO8, the thickness of the semiconductor layer 2 must be reduced accordingly. First, the collector-base junction breakdown voltage of the npn bipolar transistor formed at the same time decreases, as well as the emitter-base junction breakdown voltage, etc., making it difficult to coexist with high-voltage linear transistors.

On the other hand, if the thickness of the semiconductor layer 2 is increased to more than 10 μm for the purpose of coexistence with a high breakdown voltage linear transistor, it becomes necessary to separate each island region 'l+41 in the same process as the p-well region 6. It was difficult to form the p-type isolation region 3.

[Purpose of the invention]

The present invention is a bipolar element and an 0MO8 transistor that prevents latch and zero, improves element isolation, and makes it possible to form a vertical pnp (pnp) transistor as a piezoelectric element.
The present invention aims to provide a method for manufacturing a semiconductor device having a composite structure in which elements coexist.

[Summary of the invention]

The first invention of the present application is, for example, to form a p-type buried region under a planned well region of an n-type semiconductor layer on a p-type semiconductor substrate and near the interface between the substrate and the semiconductor layer, which will become a planned element isolation region, in the same process. , p- by forming a p-type region.
By reducing the resistance of the well region, it is possible to prevent the chipping phenomenon, and also to make it possible to form an element isolation region without depending on the thickness of the semiconductor layer or the formation of the p-well region.
The main points are to realize miniaturization of MO8 elements and higher voltage resistance of linear and 9-dimensional elements.

The second invention of the present application is, for example, a portion of the n-type semiconductor layer on the p-type semiconductor substrate under the planned well region, and a portion of the semiconductor layer on the n-type buried region under the planned I-ra element in the same process. By forming p-type buried regions respectively at K, p
- In addition to reducing the resistance of the well region to prevent latch and lag phenomena, the p-type buried region is used as a collector region, and the vertical pnp-type with high switching speed is floating with respect to the substrate due to the p-type buried region. The main point is to form an I-La transistor.

[Embodiments of the invention]

Embodiment 1 Embodiment 1 is applied to the manufacture of a composite anisotropic device in which an npn non-polar transistor and OMO8 coexist as shown in the steps of FIGS. 2(a) to 2(g).

First, the surface of the p-type silicon substrate 101 is selectively doped with an n-type impurity having a small diffusion coefficient, such as sb, to form n-type diffusion layers 1021, 102. was formed. Subsequently, a thermal oxide film 103 is grown on the surface of the substrate 101, and the thermal oxide film 103 is grown on the surface of the substrate 101.
03, a resist pattern 104 in which a planned p-type buried region and a planned p-type region are opened by photolithography.
After forming, using the resist pattern 104 as a mask, a p-type impurity such as zolon is applied to an accelerating voltage of 150@V,
)'−! Amount l x 10'% deviation" ~ 4 x 10"/c
Ions are implanted under the conditions of m' to form the substrate 101 and the n-type diffusion layer xo2*VcN ion-implanted layer 1051. 105
1+105 was selectively formed (as shown in FIG. 2 (!1)).

Subsequently, the resist layer 104 and the thermal oxide film 10 are formed.
After removing 3, for example, an n-type 7937 layer 106 having a thickness of about 6 μm was epitaxially grown. At this time, the n-type diffusion layer 10.21, IO! .

＼ due to heat during epitaxial growth υ" type silicon layer 10
The substrate 10 oozes out by causing an autodosing phenomenon in 6.
An n-type buried region 10 is formed near the interface between 1 and the silicon layer 106.
7. ．． 107. was selectively formed. at the same time,? Ron ion implantation layer 1051. 1051 similarly causes autodoping, and type 1 regions JO8, 108 are formed near the interface between the substrate 10 and the silicon layer 106, and
Since the solon ion implantation layer 105 in the n+ type diffusion layer 102s has a larger diffusion coefficient than the sb of the diffusion layer 102, the silicon layer 10 on the n+ type buried region 107m
A p-type buried region 109 was formed in 6 portions (as shown in FIG. 2(b)).

(11) Next, a thermal oxide film 110 is grown on the surface of the n-type silicon layer 106, and a portion corresponding to the needle-shaped region 108, 108 and the p-type buried region are formed on the thermal oxide film 110 by photolithography. After forming a resist pattern 111 with openings corresponding to 109, using this resist pattern 11 as a mask, a p-type impurity, for example, Ron, is applied at an accelerating voltage of 100.
A zolon ion implantation layer 1121.
12 (as shown in FIG. 2(, )). Subsequently, after removing the resist layer 111, heat treatment was performed. At this time,? Ron ion implantation layer 112, . 112. is activated and diffused to form p-type regions 113 and 113 connected to the p-type regions ios and ion, thereby forming p-type isolation regions 114 and 114 that electrically isolate the n-type 7937 layer 106. It was done. In addition, the solon ion implantation layer 112 is also activated and diffused into the p-well region 11 whose bottom is in contact with the p-type buried region 109.
5 was formed. The p-type isolation region 114
, 114, and an n-type buried region 1071 at the bottom.
The island region 1161 where ! is present becomes the pi-4-ra element forming region, and the island region 116 where the n-type buried region 102 and the heron are present below! is the CMO8 element formation area (Fig. 2(d)
). The impurity profiles of the p-type buried region 109 and the n-type buried region 1073 in the well region 115, which are formed in the depth direction from the surface of the p-well region 115, are as shown in FIG.

(11) Next, a p-type impurity, for example, zero, is passed through the thermal oxide film 110 to the island region 1161. Island area 116 and the area 116. The p-well region 116'VC in the p-well region 116'VC is selectively implanted and diffused to form a p-type space region 117 in the silicon layer 106 of the island region 1161.
1-type source and drain regions 118 and 119 electrically isolated from each other in the silicon layer 106, and p-type channel cut regions 120 in the p-well region 115 were formed at the same time (see Fig. 2). ).

QNext, the thermal oxide film 110 is removed and the thick oxide film 1 is formed again.
After growing 21 on the entire surface, an oxide film is formed in the planned emitter region formation area, the collector extraction area formation area, the n-type channel cut area area, and the n+ type source and drain area area using a chemical coating technique. 121 was selectively machined and removed by etching to form openings 122... Next, using the oxide film 121 as a mask, for example, arsenic ions are implanted through the openings 122 and diffused to form an n-type emitter in the base region 117 of the island region 1161.
3, an n-type collector extraction region 124 in the silicon layer 106 of the island region 1161, a meter-shaped channel cut region 125 in the silicon layer 106 of the island region 1163, an n-type source in the p-well region 115, drain region 126
゜127 were formed at the same time (as shown in Fig. 2(f)).
.

0 Next, after removing the oxide film 121 and forming a thick oxide film (interlayer insulating film) 128 again, the p-type source,
On the region including between the drain regions 11F1 and 119, and n
The oxide film 128 on the region including between the raw source and drain regions 126 and 127 is selectively etched and removed, and then thermal oxidation treatment is performed to form a thin r-) oxide film 12 f t 1
298 was formed. Subsequently, a contact hole is formed in the oxide film 128 portion on each region using photoetching technology, and after depositing, for example, an AJ film on the entire surface, turning is performed to form a paste, emitter, and collector AI electrode 130 to 1.
32 and □)Ajff-)electrode I
J 31 e 13 J 鵞 i, source + )' Rain extraction kl electrodes 134 to 131 are formed to form npn non-polar transistors, p-channel MO8) transistors, and n-channel MO8) transistors.
A composite device in which O2 coexisted was manufactured (Fig. 2 (g)
).

According to the first method of the present invention, the well region 11 is placed at the bottom of the p-well region 115 as shown in FIG. 2(g).
By forming a heavily doped p-type buried region 109 in contact with the p-well region 115, the layer resistance of the p-well region 115 can be reduced. This can reduce the occurrence of crawling and the Chiazo phenomenon. Furthermore, by forming the p-type buried region 109, the heat treatment time for activating and diffusing the p-well region 115 can be shortened, so as shown in FIG. Well region 1 with multiple ion implantation whose impurity profile determines the transistor performance
15 can be formed, and the properties of CuO2 can be greatly improved.

Further, at the same time as the formation process of the p-type buried region 109, an isolation region 1 is formed near the interface between the p-type silicon substrate 101 and the "type silicon layer 106."
01J, 1011 and further p-well region 115.
At the same time as the formation process of the p-type region 1011.101J
By forming p-type regions 113 and 113 connected to the p-type regions 113 and 113, it is possible to reliably electrically isolate CuO2 by a short heat treatment without depending on the depth of the p-Lewell region 115 (, tlpn/polar transistor, CuO2). In particular, by growing a thick n-type silicon layer 106' on a p-type silicon substrate 101 as shown in FIG. When forming an apaidera transistor, at the same time as the step of forming the p-type buried region 109', Kp-decade type regions 0B' and 10B' are formed near the interface between the substrate 101 and the silicon layer 106', and the p-well region 116
At the same time as the formation process of ', p-type regions 11 J', JJ,
9' by forming p-well region 115'.
without the impurity profile deviating from the design value.
Isolation regions '', 114'' that can reliably electrically isolate the thick silicon layer 106' can be formed. Moreover, since the lower side of the p-type isolation region 114.114 is composed of a low-resistance p-type region 108.108, the p-type head region 113.113 on the upper surface of the isolation region 114.114 is grounded. By this, the potential of the p-type silicon substrate 101 can be stabilized.

Therefore, in the conventional method, the thickness of the n-type silicon layer and 0
The depth of the MO8 well region has been extremely limited due to the relationship between latch-up prevention and element isolation, but according to the method of the present invention, the thickness of the n-type silicon 7 layer 106 and the depth of the MO8 well region 115 can be reduced. can be set independently, so
It is possible to increase the manufacturing margin, improve latch amplifier resistance, further miniaturize OMO8 and form a linear bipolar transistor with high breakdown voltage, and stabilize the potential of the substrate 101.

Furthermore, the island area 116. where the CMOB is built. Lower board 10
A p-type source region 118 (or a p-type drain region 119) is formed to reduce the layer resistance of the n-type silicon layer 106 in which an n+$$ MO9) transistor is formed near the interface between the silicon layer 106 and the silicon layer 106. Emi, Ri, n' type silicon Ht
The current amplification factor of the parasitic PNP (106T pace, p-type silicon substrate 101 as the collector) transistor can be reduced, and the latch amplifier resistance can be further improved.

Still n-type buried area 1o7! Board 1 under 0MO8
By providing it at the interface between 0 and the silicon layer 106,
It becomes possible to operate CMo5 with respect to the substrate 101 using a different potential system. That is, when the current in the substrate 101 caused by the .polar analog elements coexisting around the p-well region 115 is large, the potential of the substrate 101 rises; the shape
The potential of p-well region 115 (
Vss) and the potential of the substrate Ioi (GND) can be made independent by separate wiring systems. Also, with dual power supply system etc.
A third bias can be applied independently to p-well region 115. On the other hand, by omitting the n4-type buried region 107, the layer resistance of the p-well region 115 of the n-channel MO8 transistor is reduced when a large current flows in the input/output section of 1c, and the substrate 101 potential If a wiring system can be established that can sufficiently stabilize the p-type embedded region, it is preferable to ground the p-type embedded region to the substrate in order to prevent z, thia, and zo.

Example 2 Example 2 is applied to the manufacture of a composite device in which a vertical pnp bipolar transistor and an OMO8 coexist as shown in the steps of FIGS. 5(a) to (,).

(1) First, the surface of the p-type silicon substrate 201 is selectively doped with an n-type impurity having a small diffusion coefficient such as sb.
A ten-shaped diffusion layer 202152022 was formed. Continuing,
A thermal oxide film 203 is grown on the surface of the substrate 101, and a resist glossy turn 204 is formed on the thermal oxide film 203 by photolithography in which the planned p+ type buried region and the planned p green region are opened. Using the resist noturn 204 as a mask, p-type impurities such as zolon are applied at an accelerating voltage of 150
ksv, dose amount 1×1o14/6n2~4X10
Zolone ion implantation layer 2051 is implanted into the substrate 201 and the - type diffusion layer 2011 t202g by ion implantation under the condition of '%-.
12051 +205! , 2053 were selectively formed (as shown in FIG. 2(,)). After removing the resist gloss turn 204 and the thermal oxide film 203, an n-type silicon layer 206 having a thickness of, for example, about 6 μm was epitaxially grown. At this time, the meter-shaped diffusion layer 202. ．． 202.
The "type silicon layer 20" is damaged by heat during epitaxial growth.
Substrate 20 oozes out by causing an autodoping phenomenon in 6.
A meter-shaped embedded region 20 is formed near the interface between the silicon layer 10g and the silicon layer 10g.
Y! , 207fi were selectively formed. 1 at the same time
The zolon ion implantation layer 20512051 similarly undergoes autodoping and diffusion to form the substrate 201 and the silicon layer 20.
．． Type 1 regions 201J, 2011 are formed near the interfaces of 2θ21 . 202. Zolon ion implantation N2os, 2 (753 is the diffusion R202
The needle-shaped embedded region 207. has a larger diffusion coefficient than the sb of 1°202 goose. , 207. upper silicon layer 2
A p half-type buried region 209 which becomes the collector region of the vertical pnp bipolar transistor and a p half-type buried region 21θ for reducing the layer resistance of the p-well region are formed in the 06 portion (FIG. 5(b)). (Illustrated).

(11) Next, a thermal oxide film 110 is grown on the surface of the n-type silicon layer 206, and photolithography is performed on the thermal oxide film 211 to form the p-type region 208, 208, the planned p-type collector portion, and the p-half region. After forming a resist pattern (not shown) in which a portion corresponding to the mold burying region 210 is opened, p-type impurity,
For example, Zarron was ion-implanted under conditions of an acceleration voltage of 100 keV and a dose of 2 x 10' drops to 2 x 6 x 10' drops, and was activated and diffused. In this step, p-type regions 212.212 connected to the −-type regions 208.208 are formed, and these make the n-type silicon layer 206 into a vertical p-type region.
Island region 21311 as np/J polar transistor formation region, island region 213 as CMO8 formation region
A p-type isolation region 21 that electrically isolates the
4°214 was formed. At the same time, the island area 213
The p-type collector region 215 is located at the island region 213, and the p-half type buried region 209. A p-well region 216 was formed thereon, respectively. Next, an n-type impurity such as arsenic is selectively ion-implanted into the island region 2131 through the thermal oxide film 211, activated and diffused, and the transistor output current at a large current is activated and diffused. An n-type region 217 was formed to increase the expansion. Subsequently, a p-type impurity such as zolon is applied to the p-type region 212 of the isolation region 214 through the thermal oxide film 210.
Island region 2131 □ n-type region 217 and p-type collector region 216 . l' island area 213m, same area 213! Ions are selectively implanted and diffused into each of the C p-well regions 216 to form a p-type electrode extraction region 218 for substrate grounding in the p-type region 212 and an island region 213.
A p-type emitter region 219 is placed in the n-type region 217 of the
A p-type collector extraction region 22 is provided in the mold collector region 215.
0 to the p-type source and drain regions 22 electrically isolated from each other by the n-type silicon layer 206 of the island region 2132.
1,222 and a p medium channel cut region 223 in the p-well region 216 were formed simultaneously (fifth
Figure (e) shown).

(In step 11bθζ, the thermal oxide film 211 is removed and a thick oxide film 224 is grown again on the entire surface, and then the υ base extraction region is to be formed, the n-type channel cut region is to be formed, and the ?-type source are Then, the oxide film 224 in the area where the drain region was to be formed was selectively removed by etching to form the openings 225. Next, using the oxide film 224 as a mask, ions of, for example, arsenic were implanted through the openings 225. Then, by diffusing, the n-type pace extraction region 226 is placed in the pace region 217 of the island region 2131, and the
13. An n-type channel cut region 227 is provided in the silicon layer 206, an n-type source is provided in the p-well region 215,
Drain regions 228° and 229 were formed simultaneously (
(Illustrated in FIG. 5(d)).

(2) Next, the oxide film 224 is removed, and a thick oxide film (field insulating film) 230 is formed again on the region including between the p-type source and drain regions 221 and 222, and ? The oxide film 230 on the region including between the source and drain regions 221J and 229 of the mold is selectively etched away,
Further thermal oxidation treatment is performed to form a thin f-) oxide film 2311*2
31! was formed. Next, a contact hole is formed in the oxide film 230 on each region using photoetching technology, and after depositing, for example, an AI film on the entire surface, gloss turning is performed to form a kl electrode 232I for grounding the substrate, a paste,
Emitter, collector AIM, poles 233 to 235 are formed, and A4r-) electrodes 2361 + 236
@ * Source + )"L'-in extraction AI electrodes 237 to 240 were formed to manufacture a composite device in which vertical pnp pie era transistors and 0MO8 consisting of p-channel MO8) transistors and n-channel MO3) transistors coexisted. (Illustrated in Figure 5(, )).

According to the second invention method of the present application, as shown in FIG.
At the same time, a p-type buried collector region 209 is formed in the island region of the planned vertical pnp bipolar transistor by forming a high-concentration p-type buried region 210 in contact with the p-type p-type bipolar transistor. Excellent 0MO8
It is possible to easily manufacture a composite device in which a vertical plpzJ polar transistor, which can achieve high speed and high output, coexists. At the same time as the formation of the p-type buried region 21o1p-type buried collector region 209, a p-type region 208. 2
08, it is possible to form fine p-type isolation regions 214, 214 that can reliably electrically isolate vertical pnp bipolar transistors and cMOS.

In the above embodiment, the p-type buried region formed at the bottom of the p-well region was formed in the n-type silicon layer portion above the male-type buried region, but for example, the n-type buried region directly under the well could be omitted. An r-type buried region may be formed near the interface between the p-type silicon substrate and the n-type silicon layer, and the p-well may be grounded.

In the above embodiment, a method of forming a single silicon layer was adopted, but a double epitaxial growth method was used to form a thick silicon layer, and an interface between these two n-type silicon layers below the planned well region was used. By forming a p-type buried region nearby, a bipolar transistor is formed in the two silicon layer portions, an 0MO8 is formed in the upper silicon layer, and a composite device is created in which a high breakdown voltage linear transistor and a fine 0MO8 coexist. It is also possible to manufacture a nose chair.

In the above embodiment, the bipolar element and the C21l108 element were separated by isolation, but an oxide film was formed by selective oxidation technology on the silicon layer portion above the p+ mold region previously formed near the interface between the substrate and the mold silicon layer. , they may be separated by a dielectric film.

In Example 1 above, the n-type buried region under the piezilla element formation region and the n+-type buried region under the 0MO8 element formation region were formed in the same process, but the layer resistance of the p-type buried region at the bottom of the well region increased. From the viewpoint of preventing this, it is desirable to form each of the n-type buried regions in separate steps.

That is, the meter-shaped buried region under the 0MO8 element formation region is
When forming directly under the green mold embedding area, is this? The upward seepage from the mold buried region increases the layer resistance of the p-type buried region. In order to reduce this increase in layer resistance, there is a method of forming the n-type buried region under the 0MO8 element by a different diffusion from the n-type buried region under the npn bipolar transistor, that is, the n-half type subcollector region. Adopt. In this case, possible means for forming the n-type buried region under the 0MO8 element include a method of using an impurity with a small diffusion coefficient (for example, sb, etc.) or a method of lowering the surface concentration of the impurity. Specifically, after forming a deep n-type diffusion layer with a low surface concentration in the region directly under the 0MO8 element of a p-type silicon substrate, an n-type silicon layer is epitaxially grown on the entire surface of the substrate, thereby increasing the upward diffusion. It is desirable to form an n-type buried region with a small amount of n-type buried region.

In the above Example 2, the space region (n-type silicon layer 2o6) was formed in the form of an island using the collector region 2 J 5.215. forming an n-type space region within the collector region, and further forming a p-type space region within the space region.
A triple diffusion method may be used to form a type emitter region. If such a triple diffusion method is adopted, the collector region does not need to be formed into a ring shape by matching the masks, so the degree of integration can be improved, and the pace width of the pace region can be reduced.
The influence of the thickness of the p-type silicon layer and the upward diffusion of the p-type buried collector region can be avoided, and a composite device in which a vertical pnp bipolar transistor and an OMO8 coexist can be mass-produced.

〔Effect of the invention〕

As described in detail above, according to the present invention, a highly reliable and fine 0MO that prevents latch-up and improves element isolation is achieved.
A semiconductor device with a composite structure that coexists with a high-reliability, fine OMO8 and a high-speed, high-output vertical pnp bipolar transistor. Accordingly, it is possible to provide a method for manufacturing semiconductor devices in mass production.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a composite device manufactured by a conventional method in which an npn piezilla transistor and an 0MO8 coexist, and FIGS. of? FIG. 3 is a cross-sectional view showing the manufacturing process of a composite device in which a polar transistor and 0MO8 coexist.
Diagram showing the impurity profile of the green mold embedding region and the sand mold embedding region, FIG. 4 is a sectional view of a composite device showing a modification of Example 1, and FIGS. 5(9) to (e) are examples of the present invention. FIG. 2 is a cross-sectional view showing the manufacture of a composite device in which a vertical POP/Ipolar transistor and an OMO8 are coexisted in FIG. 101,! 01...p-type silicon substrate, 7071+
107m + 2071+ 2071...n green type buried region, 101J, 20B...p ten type region, 109
．． 210... p-type embedded region, 11j, 212...
・P-type head area, 114.214...p-type isolation region, 115.216...p-well region, 116
1. 116 years + 2131 +! ' 13g...Island region, 117...p ten-shaped base region, 11111221
...p ten type source region, 119.222...p ten type drain region, 120.223...p raw type channel cut region, 123...? type emitter region, 125.
227...n ten-type channel cut area, 126.1
! :1B...n-type source region, 127.229...
・n tenyaku P rain region, 11!8.230...Oxide film, 1291*129 Snow 52311-231 False...Dart oxide film, 130~IJ2.134~1 3 7
, 23! ~235°237~240...AI electrode, 1331. 133%. 2361.236.・l'-) electrode, 209-p biotype buried region (p collector buried region), 215・
...p-type collector region, 217...n-type pace region,
219...p-type emitter region.

Claims (9)

[Claims] (1) A semiconductor layer of a second conductivity type is provided on a semiconductor substrate of a first conductivity type, and at least a bipolar element and a semiconductor layer of a first conductivity type are provided in a plurality of island regions formed by gaseously separating the semiconductor layer. In manufacturing a semiconductor device having a structure including a CMO8 element having a well region, a high concentration buried region of the second conductivity type is selectively formed in the vicinity of the interface between the semiconductor substrate and the semiconductor layer under the planned formation of the pie-ra element. selectively forming a high concentration buried region of the first conductivity type in at least a portion of the semiconductor layer immediately below the planned well region, and at the same time forming a part of the isolation region near the interface between the semiconductor substrate and the semiconductor layer; selectively forming a high concentration first conductivity type region constituting the semiconductor layer; and selectively forming a first conductivity type well region connected to the first conductivity type buried region in the semiconductor layer portion on the first conductivity type buried region. 1. A method of manufacturing a semiconductor device, comprising a step of forming a semiconductor device. (2) It is confirmed that the high concentration buried region of the first conductivity type, which is selectively formed directly under the planned well region, is arranged in a portion extending from the semiconductor layer of the second conductivity type to the semiconductor substrate of the first conductivity type. A method for manufacturing a semiconductor device according to claim 1. (3) Highly concentrated buried region of the second conductivity type
- selectively formed near the interface between the semiconductor substrate of the first conductivity type and the semiconductor layer of the second conductivity type, not only under the planned formation of the CMO8 element but also under the planned formation of the well region; 2. The method of manufacturing a semiconductor device according to claim 1, wherein a high concentration buried region of the first conductivity type is selectively formed in a portion of the semiconductor layer above the buried region of the second conductivity type. (4) Place the high concentration second conductivity type buried region in the first region under the bipolar element formation plan and under the C'MO8 element formation plan area.
CMO8 is selectively formed near the interface between the conductive type semiconductor substrate and the second conductive type semiconductor layer in separate steps.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is formed using an impurity that is below the planned element formation level or has a small diffusion coefficient. (5) At the same time as forming the well region of the first conductivity type, an isolation region of the first conductivity type connected to the high concentration first conductivity type region is formed in the surface portion of the semiconductor layer of the second conductivity type. A method for manufacturing a semiconductor device according to claim 1. (6) the first conductivity type is p type, the second conductivity type is n type,
6. A method of manufacturing a semiconductor device according to claim 1, wherein an npn bipolar transistor is formed as a bipolar element in an island region of an n-type semiconductor layer. (7) A semiconductor layer of a second conductivity type is provided on a semiconductor substrate of a first conductivity type, and at least a bipolar element and a semiconductor layer of a first conductivity type are provided in a plurality of island regions formed electrically separated from the semiconductor layer. In manufacturing a semiconductor device having a structure in which a 0MO8 element having a well region is provided, a high concentration of a second
a step of selectively forming a buried region of a conductive type, and selectively forming a buried region of a first conductive type with a high concentration to connect with the well in at least a portion of the semiconductor layer under the planned well region of the first conductive type; At the same time, a high concentration buried region of the first conductivity type is selectively formed in a portion of the semiconductor layer above the second conductive buried region under which a bipolar element is planned to be formed. (8) The high concentration buried region of the first conductivity type, which is selectively formed under the planned well region, is arranged in a portion extending from the semiconductor layer of the second conductivity type to the semiconductor substrate of the first conductivity type. A method for manufacturing a semiconductor device according to claim 7, characterized in that: (9) The high concentration second conductivity type buried region is
- selectively formed near the interface between the semiconductor substrate of the first conductivity type and the semiconductor layer of the second conductivity type, not only under the planned formation of the CMO8 element, but also under the planned well region area; 8. The method of manufacturing a semiconductor device according to claim 7, wherein a high concentration buried region of the first conductivity type is selectively formed in a portion of the semiconductor layer above the buried region of the second conductivity type. (4) A vertical structure in which the first conductivity type is p type, the second conductivity type is n type, and the high concentration buried region of the first conductivity type on the high concentration buried region of the second conductivity type is the p type collector region. 10. The method of manufacturing a semiconductor device according to claim 7, wherein a pnp type polar transistor is formed as a non-Ibolar element in an island region of an n-type semiconductor layer.