JPS6380559A - Bipolar cmos semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a latchup phenomenon by providing other conductivity type isolation layer which passes one conductivity type layer between a p- channel MOSFET and a C-channel MOSFET of CMOS unit. CONSTITUTION:After an n<+> type buried layer 2 is provided partly on a p-type Si substrate 1, an n<-> type epitaxial layer 3 is grown on the substrate 1. When a bipolar unit is separated by a p<+> type diffused layer 4, a p<+> type diffused layer 41 which arrives at the substrate 1 is formed between regions formed at an n-channel MOSFET and a p-channel MOSFET of a CMOS unit, and a p<-> type well layer 5 is formed by ion implanting to an n-channel MOSFET. Then, a p-type base layer 6, an n<+> type emitter layer 7 and an n<+> type collector electrode layer 8 are provided on the bipolar unit, an n<+> type source/drain diffused layer 9 is formed in the layer 5, and a p<+> type source/drain diffused layer 10 is formed in the layer 3. Further, a base electrode 12, an emitter electrode 13 and a collector electrode 14 are provided in an n-p-n transistor 21, a gate electrode 15 is provided on an oxide film 11 between the source and the drain, and electrodes 16, 17 are provided at the source/drain 9, 10. Thus, a latchup due to a thyristor effect can be prevented.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a bipolar CMOS semiconductor device in which a bipolar transistor and an OMO3 coexist on one semiconductor substrate.

[Prior art and its problems]

Bipolar transistor and 0MO on one semiconductor substrate
3 to coexist, conventionally, as shown in the process diagram of Fig. 2, an n-buried layer 2 is provided on a part of the p-type St substrate 1 (Fig. a).
Next, an n-layer 3 is epitaxially grown on the substrate 1, a p-type isolating diffusion layer 4 is provided that reaches the p-substrate 1 from the surface of the n-layer 3, and each bipolar transistor is electrically insulated by a PN junction. Furthermore, in the n-channel MOSFET section, a p-well layer 5 is provided by ion implantation (Figure b), and in the bipolar section, a p'' base diffusion layer 6, an n'' emitter diffusion layer 7 and an n0 collector electrode layer 8 are provided. On the other hand, in the CMOS part, an n source/drain diffusion layer 9 is provided in the region of the p-well layer 5, and a p source/drain diffusion layer 10 is provided in other parts (Figure c), followed by a surface oxide film. Open the window at the predetermined position of layer 11 and remove the base layer 6.
．． Emitter layer 7. Base electrode 1 on each collector layer 8
2. Emintaden m 13. A collector electrode 14 is deposited, and an oxide film 1 is formed on the surface between each source/drain of the CMOS section.
A gate electrode 15 is provided via 1, and a source/
Source/drain to drains 9 and 10. By depositing the in-electrodes 16.17, the npn bipolar transistor 21. n-channel MOSFET22
．． A bipolar CM'O3 semiconductor device consisting of a p-channel MOSFET 23 is constructed. However, in such a structure, as shown by the transistor symbol in FIG. n-epitaxial layer 3-p-well layer 5-n″″″ source/de 1
A 42-layer, 9-pn) transistor 32 is constructed. Moreover, at this time, since the n-epitaxial layer 3 and the p-well layer 5, which correspond to the base of each parasitic transistor, have a low impurity concentration in order to maintain the breakdown voltage, Threnshold voltage v7, the h4 of the parasitic transistor is large, and a latch amplifier occurs due to the thyristor effect. Also, this launch amplifier phenomenon is caused by I
This problem is more likely to occur in the output stage FET which requires current than in the logic section in which almost no current flows inside C, because the parasitic transistor is more likely to turn on due to the voltage drop in the base layer of the parasitic transistor.

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks and provides a bipolar C
The purpose is to provide a MOS semiconductor device.

[Key points of the invention]

In the present invention, an isolation layer of a different conductivity type is formed in a layer of one conductivity type on one semiconductor substrate and penetrates through that layer.
Between the p-channel MOSFET and n-channel MOSFET of the CMOS part of the semiconductor device in which the bipolar transistor part and the CMOS part exist, a layer of the other conductivity type that is of the same conductivity type as the isolation layer and that similarly penetrates the layer of the one conductivity type is formed. The above objective is achieved by providing an isolation layer to separate both channel MO8FETs.

[Embodiments of the invention]

The manufacturing process of an embodiment of a bipolar CMOS semiconductor device according to the present invention is shown in FIG. 1 (al to +d), in which the same parts as in FIG. 2 are given the same reference numerals. Figure 1 + al is n゛ buried 1 in a part on the p-type S1 substrate l.
The step of providing n=epitaxial layer 3 on the substrate 1 is similar to the step shown in FIG. 2 fa), but in FIG.
When the bipolar part is separated by the p'' diffusion layer 4, a p'' diffusion FJ 41 reaching the substrate 1 is also formed between the regions formed for the n-channel MO8FET and the p-channel/l/MOSFET in the CMOS section. Then, a p-well layer 5 is formed by ion implantation into the n-channel MOSFET section.
This shows the process of providing. Next, in FIG. 1(C), a p base layer 6. n0 processing layer 7゜n゛ collector voltage fi[8 is provided, p-well layer 5 of CMOS section
The process of forming an n0 source/drain layer 9 in the epitaxial layer 3 and a p'' source/drain diffusion layer 10 in the epitaxial layer 3 is shown. Further, FIG. 1 (dl) is the same as FIG. 2 (dl), the p base layer 6.
゛Collector electrode 1i8, base electrode 12゜emitter electrode 13. A collector electrode 14 is provided, and a gate electrode 1 is provided on the oxide film 11 between each source and drain in the 0M08 section.
5 and also provide source/drain electrodes 16 and 17 at source/drain 9 and 10, respectively.As is clear from the above, a bipolar CMOS semiconductor device is constructed by this process. , can be carried out using the same number of manufacturing steps as the conventional bipolar CMOS semiconductor device shown in FIG. It is also effective to provide the isolation layer 41 according to the present invention only in the 0M08 portion that is directly connected to the external output terminal of the semiconductor integrated circuit. Effects of the Invention According to the present invention, in a bipolar CMOS semiconductor device, the isolation layer penetrating the semiconductor layer can be formed not only between the bipolar part and the CMOS part, but also between the n-channel FET and the p-channel FET in the CMOS part. By providing a
Since the formation of a parasitic npn (npn) transistor and a parasitic pnp transistor spanning the OS FET 8N region is suppressed, latch-up due to the silisk effect can be prevented. Particularly, the effect is great when used in an output stage FET that requires current, while there is no need to add a manufacturing process, and the effect on the chip size is small.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view sequentially showing the manufacturing process of an embodiment of the present invention, FIG. 2 is a cross-sectional view sequentially showing the manufacturing process of a conventional device, and FIG.
The figure is a partially enlarged sectional view of the apparatus of FIG. 2. Lap type S1 substrate, 3:n epitaxial layer, 4°41
:p” isolation layer, 5: well layer, 21: bipolar transistor, 22: n-channel MO3 Fig. 1 Fig. 3

Claims (1)

[Claims] 1) In a device in which a bipolar transistor section and a CMOS section are present in a layer of one conductivity type on one semiconductor substrate through an isolation layer of another conductivity type penetrating the layer, the CMOS p-channel MOSFET and C-channel M
A bipolar CMOS semiconductor device, characterized in that an isolation layer of another conductivity type is provided between the OSFETs, penetrating the layer of one conductivity type. 2) The device according to claim 1, in which the isolation layer is directly connected to the external output terminal.
p-channel MOSFET and n-channel MOSFET in S section
Bipolar CM characterized by being provided between T.
OS semiconductor device.