JPS61168259A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61168259A JPS61168259A JP860085A JP860085A JPS61168259A JP S61168259 A JPS61168259 A JP S61168259A JP 860085 A JP860085 A JP 860085A JP 860085 A JP860085 A JP 860085A JP S61168259 A JPS61168259 A JP S61168259A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon oxide
- base region
- emitter
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 19
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 3
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特にウォール
ドエミッタ構造を有するバイポーラ型トランジスタの歩
留を向上させる製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a bipolar transistor having a walled emitter structure to improve the yield.
従来、バイポーラ型半導体装置では、装置の小型化、高
性能化を計る為に、エミッタ領域を素子分離用の比較的
厚い選択酸化膜と接触させる所謂ウォールドエミッタ構
造が考えられている。Conventionally, in bipolar semiconductor devices, a so-called walled emitter structure has been considered in which the emitter region is brought into contact with a relatively thick selective oxide film for element isolation in order to reduce the size and improve the performance of the device.
第２図（ａ）〜げ）はウォールドエミッタ構造のバイポ
ーラ型トランジスタの製造方法を説明するために工程順
に示した断面図である。FIGS. 2(a) to 2(a) are cross-sectional views shown in order of steps to explain a method of manufacturing a bipolar transistor having a walled emitter structure.
才ず、第２図（ａ）に示すように、Ｎ型エピタキシャル
層１１上に素子領域のみ−にシリコン酸化膜１２、シリ
コン窒化膜】３を選択的に形成する。As shown in FIG. 2(a), a silicon oxide film 12 and a silicon nitride film 3 are selectively formed on the N-type epitaxial layer 11 only in the element region.
次に第２図（ｂ）に示すように、通常の方法により素子
分離用の厚いシリコン酸化膜１４を形成する。Next, as shown in FIG. 2(b), a thick silicon oxide film 14 for element isolation is formed by a conventional method.
次に第２図（Ｃ）に示すように、前記シリコン窒化膜１
３を除去し、残存する前記シリコン酸化膜１２を通して
イオン注入法によりホウ素をエピタキシャル層１１内に
添加してベース領域１５を形成する。Next, as shown in FIG. 2(C), the silicon nitride film 1
3 is removed, and boron is added into the epitaxial layer 11 by ion implantation through the remaining silicon oxide film 12 to form a base region 15.
次に、第２図（ｄｌに示すように、残存するシリコン酸
化膜Ｊ２をバッフアート弗酸液により除去する。Next, as shown in FIG. 2 (dl), the remaining silicon oxide film J2 is removed using a buffered hydrofluoric acid solution.
次に、第２図（ｅ）に示すように、ベース領域１５を含
む半導体基板表面に約１０００Ｘの多結晶シリコン膜１
７を形成し、多結晶シリコン膜１７全通して燐あるいは
砒素をベース領域１５内に添加してエミッタ領域１６を
形成する。Next, as shown in FIG.
7 is formed, and phosphorus or arsenic is doped into the base region 15 through the entire polycrystalline silicon film 17 to form an emitter region 16.
次に第２図（ｆ）に示すよう番こ、多結晶シリコン膜１
７表面に金属膜を形成し、パターニングして電極を形成
し、装置の製造を完了する。Next, as shown in FIG. 2(f), a polycrystalline silicon film 1 is formed.
7. A metal film is formed on the surface and patterned to form electrodes, completing the manufacturing of the device.
しかしながら、上記従来の製造方法では、第２図（ｄ）
においてシリコン酸化膜１２をバッフアート弗酸液で除
去する際、素子分離領域のシリコン酸化膜１４も同時に
除去され、更に、該シリコン酸化膜１４とベース領域１
５との境界でシリコン酸化膜１４のエツチング速度が速
く高性能化の為に、ベース接合を浅く形成したトランジ
スタでは後工程でエミッタ不純物を添加した際にエミッ
タとコレクタ間の耐圧が劣下するという問題があった。However, in the conventional manufacturing method described above, as shown in FIG.
When the silicon oxide film 12 is removed using a buffered hydrofluoric acid solution, the silicon oxide film 14 in the element isolation region is also removed at the same time, and the silicon oxide film 14 and the base region 1 are also removed at the same time.
The etching speed of the silicon oxide film 14 at the boundary with 5 is fast, and in order to improve performance, transistors with shallow base junctions are said to have a lower withstand voltage between the emitter and collector when emitter impurities are added in a later process. There was a problem.
第３図は第２図（ｄ）の破線で囲んだ部分の拡大図であ
る。FIG. 3 is an enlarged view of the part surrounded by the broken line in FIG. 2(d).
即ち第３図において、シリコン酸化膜】４とベース領域
１５の境界でバッフアート弗酸液に対するエツチングレ
ートの速い領域が存在し、上記シリコン酸化膜１２を除
去した際に、コレクタ・ベース接合表面点ａとエミッタ
不純物を添加する開孔部端点すとの距離が短かくなりこ
の状態でエミッタ不純物を添加すると、コレクタ・エミ
ッタ間の耐圧が劣下し、それを防ぐためにベース領域を
深（形成しなければならず、ベース幅を狭くし高性能ト
ランジスタを形成する上で問題となっていた。That is, in FIG. 3, there is a region where the etching rate for the buffered hydrofluoric acid solution is high at the boundary between the silicon oxide film 4 and the base region 15, and when the silicon oxide film 12 is removed, the collector-base junction surface point The distance between a and the end point of the opening where the emitter impurity is added becomes shorter, and if the emitter impurity is added in this state, the withstand voltage between the collector and emitter will deteriorate. This has caused problems in narrowing the base width and forming high-performance transistors.
前記問題点に対して、従来次に示す改善策がとられてい
た。即ち、ベース領域１５を形成する前に前記シリコン
酸化膜１２を除去しその後ｌこイオン注入法によシベー
ス領域１５を形成する。これにより、前記点ａと点すの
距離を長くすることが可能である。Conventionally, the following improvement measures have been taken to address the above-mentioned problems. That is, before forming the base region 15, the silicon oxide film 12 is removed, and then the base region 15 is formed by ion implantation. Thereby, it is possible to increase the distance between the point a and the point.
しかしながら、上記製法では、基板に直接イオン注入す
る為該イオン注入による損傷によりトランジスタ歩留シ
を低下させるという問題点があった。However, in the above manufacturing method, since ions are directly implanted into the substrate, there is a problem in that the transistor yield is reduced due to damage caused by the ion implantation.
本発明は、上記欠点を解消し、ウォールドエミッタ構造
のトランジスタを形成する際、エミッタ不純物添加用の
開孔部を異方性ドライエッチによ多形成することによシ
高歩留りで高性能な半導体装置を製造する方法を提供す
ることを目的とする。The present invention eliminates the above-mentioned drawbacks and creates a high-performance semiconductor with high yield by forming multiple openings for adding emitter impurities by anisotropic dry etching when forming a transistor with a walled emitter structure. The purpose is to provide a method for manufacturing a device.
本発明の半導体装置の製造方法は、少なくとも一辺が比
較的厚い選択酸化膜に接触する開孔部を形成するに際し
、該開孔部を異方性ドライエツチングを用いて形成する
工程を含んで構成される。The method for manufacturing a semiconductor device of the present invention includes the step of forming an opening that contacts a comparatively thick selective oxide film on at least one side by using anisotropic dry etching. be done.
以下、本発明の実施例について、図面を参照して説明す
る。Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を説明するための一工程の要
部拡大断面図である。FIG. 1 is an enlarged sectional view of a main part of one process for explaining an embodiment of the present invention.
本実施例においては従来例の第２図（ａ）〜（ｆ）にお
いて、第２図（ａ）より第２図（Ｃ）までの工程は本実
施例と同様に実施する。In this embodiment, the steps from FIG. 2(a) to FIG. 2(C) in FIGS. 2(a) to 2(f) of the conventional example are performed in the same manner as in this embodiment.
第２図（ｄ）工程における残存するベース領域上のシリ
コン酸化膜１２を除去するに際しては、本実施例では例
えば、ＣＦ、とＨ２の混合ガスを用いた異方性ドライエ
ツチングにより除去する。この時は、従来のバッフアー
ト弗酸液によるエツチングで見られたシリコン酸化膜１
４とベース領域１５の境界での増速エツチングが防止さ
れ、第１図に示されているようにコレクタ・ベース接合
表面点ａｌ とエミッタ不純物を添加する開孔部端点ｂ
１との距離が第３図に示した従来例よりも長（なる。In this embodiment, the remaining silicon oxide film 12 on the base region in the step of FIG. 2(d) is removed by anisotropic dry etching using a mixed gas of CF and H2, for example. At this time, the silicon oxide film 1 that was seen in the conventional etching using buffered hydrofluoric acid solution was removed.
4 and the base region 15 is prevented, and as shown in FIG.
1 is longer than the conventional example shown in FIG.
次に、第２図（ｅ）と同様に、多結晶シリコン膜を形成
、線膜を通して燐あるいは砒素を添加しエミッタ領域を
形成する。Next, as in FIG. 2(e), a polycrystalline silicon film is formed, and phosphorus or arsenic is added through the line film to form an emitter region.
次に、第２図（ｆ）と同様に、金属膜を被着、パターニ
ングして電極を形成すれば本実施例は完成する。Next, as in FIG. 2(f), a metal film is deposited and patterned to form electrodes, thereby completing the present embodiment.
以上説明したように、本実施例では、異方性ドライエツ
チングによシ、エミッタ不純物添加用の開孔部を形成す
るため、シリコン酸化膜１４とベース領域１５での増速
エツチングが防止され、その結果点ａ１と点ｂ１の距離
が従来の点ａと点すの距離よシ長くなる。従って浅いベ
ース接合を形成した場合でも、コレクタとエミッタの耐
圧の低下が防止できる。また、従来の改良法のように、
ベース領域の形成前に酸化膜を除去しイオン注入法によ
シベース領域を形成する方法と異なり、基板に直接イオ
ン注入する工程がないのでイオン注入による横脇は生じ
ない。従って高歩留りで、高性能なトランジスタを形成
することができる。As explained above, in this embodiment, since the opening for adding emitter impurities is formed by anisotropic dry etching, accelerated etching in the silicon oxide film 14 and the base region 15 is prevented. As a result, the distance between points a1 and b1 becomes longer than the conventional distance between points a and b1. Therefore, even when a shallow base junction is formed, a decrease in breakdown voltage between the collector and emitter can be prevented. Also, like the conventional improvement method,
Unlike the method in which the oxide film is removed before the base region is formed and the base region is formed by ion implantation, there is no step of directly implanting ions into the substrate, so no sidewalls occur due to ion implantation. Therefore, a high-performance transistor can be formed with high yield.
以上１本発明をＮＰＮ型バイポーラトランジスタに実施
した場合につき説明したが、導電型を変えることによシ
、ＰＮＰ型トランジスタに適用できるし、これらを含む
集積回路装置に適用することができる。Although the present invention has been described above in the case where it is applied to an NPN type bipolar transistor, it can be applied to a PNP type transistor by changing the conductivity type, and it can also be applied to an integrated circuit device including these.
以上説明したように、本発明によれば、厚いシリコン酸
化膜とベース領域境界での増速エッチを防止することが
可能となシ、従ってベース接合が浅くても、コレクタと
エミッタの耐圧が劣下することなく高歩留のウォールド
エミッタ構造のトランジスタが実現できる。As explained above, according to the present invention, it is possible to prevent accelerated etching at the boundary between a thick silicon oxide film and the base region, and therefore, even if the base junction is shallow, the withstand voltage of the collector and emitter is degraded. A high-yield walled emitter structure transistor can be realized without any degradation.
第１図は本発明の一実施例を説明するための一工程の要
部拡大断面図、第２図（ａ）〜（ｆ）は従来のウォール
ドエミッタ構造のバイポーラ型トランジスタの製造方法
を説明するために工程順に示した断面図、第３図は第２
図（ｄ）の点線部内の拡大断面図である。
１１・・・・・・Ｎ型エピタキシャル層、１２．１４・
・・・・・シリコン酸化膜、１３・・・・・・シリコン
窒化膜、】５・・・・・・ベース領域、１６・・・・・
・エミッタ領域、Ｊ７・・・・・・多結晶シリコン膜、
１８・・・・・・金属膜。FIG. 1 is an enlarged sectional view of a main part of one process for explaining an embodiment of the present invention, and FIGS. 2(a) to (f) illustrate a conventional method for manufacturing a bipolar transistor with a walled emitter structure. Figure 3 is a cross-sectional view shown in order of process.
It is an enlarged cross-sectional view within the dotted line part of figure (d). 11...N-type epitaxial layer, 12.14.
...Silicon oxide film, 13...Silicon nitride film, ]5...Base region, 16...
・Emitter region, J7...polycrystalline silicon film,
18...Metal film.
Claims (1)
部を形成するに際し、該開孔部を異方性ドライエッチン
グを用いて形成することを特徴とする半導体装置の製造
方法。1. A method of manufacturing a semiconductor device, characterized in that when forming an opening that contacts a selective oxide film that is relatively thick on at least one side, the opening is formed using anisotropic dry etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP860085A JPS61168259A (en) | 1985-01-21 | 1985-01-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP860085A JPS61168259A (en) | 1985-01-21 | 1985-01-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61168259A true JPS61168259A (en) | 1986-07-29 |
Family
ID=11697459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP860085A Pending JPS61168259A (en) | 1985-01-21 | 1985-01-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61168259A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010642A (en) * | 1983-06-29 | 1985-01-19 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1985
- 1985-01-21 JP JP860085A patent/JPS61168259A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010642A (en) * | 1983-06-29 | 1985-01-19 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
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