JPS61220466A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor integrated circuit device having characteristics of high speed and low power consumption.

2. Description of the Related Art A cross-sectional view of a bipolar transistor manufactured by a conventional manufacturing method is shown in FIG. In the figure, 1 is a p-type semiconductor Si substrate, 2 is an n+ buried layer, 3 is an isolation oxide film, 4 is an n-type collector and epitaxial layer, 6 is a base region, 6 is an n+ emitter, and 7 is an n+ polycrystalline SL. Emi Lid, 8 is polycrystalline S
9 is an insulating film separating the emitter 6.7 and the base extraction electrode 8, 10 is a base metal electrode, and 11 is an emitter metal electrode. In such a transistor, the base area of the transistor is reduced by using the base lead-out electrode 8, but since polycrystalline SL is used as the base lead-out line, the resistivity is high < (approx. 50-600°Ω/mouth) Therefore, the base resistance increases. This was a drawback that hindered the speeding up of transistors.

Problems to be Solved by the Invention In such conventional bipolar transistors, the base area can be reduced by using a base lead electrode, but the base resistance is high. Therefore, the speed of transistors could not be increased sufficiently. The present invention has been made in view of the above, and an object of the present invention is to provide a high-speed method of manufacturing a bipolar transistor by achieving reduction in base area and base resistance using a simple method.

Means for Solving the Problems In order to solve the above problems, the present invention forms a convex emitter region whose side surfaces are covered with an insulating film, and then forms a base lead-out electrode with low resistance using a metal thin film. It forms the

Operation The present invention achieves high-speed bipolar transistors by reducing the space area and base resistance by the above-described method.

Examples Examples of the present invention will be described below with reference to FIGS. 1 to 10. FIG. 1 is a sectional view of a bipolar transistor in an embodiment of the present invention.

In the figure, 12 is a p-type substrate, 13 is an n+ buried layer, and 14 is a p-type substrate.
1 is an isolation oxide film, 16 is an n-type collector epitaxial layer, 16 is a base region, 17 is a polycrystalline St n-type oxide film, 19 is an n-type oxide film, 21 is an insulating film that covers the side surface of the emitter, and 22 is an insulating film that covers the side surface of the emitter. Metal thin film base extraction electrode, 24
2 is an insulating film covering the metal thin film base extraction electrode;
6 is a base electrode, 26 is an emitter electrode, and a is the length of the base region 16.

In the figure, the interval between the two base electrodes 26 is sufficiently larger than the length a of the base region 16. However, since the base lead electrode is used, the length a of the base region can be reduced. Without the base extraction electrode, the length a of the base region would be approximately the same as the spacing between the base electrodes 26. As a result, the pace area can be significantly reduced, resulting in smaller parasitic capacitance. Furthermore, since the metal thin film 22 is used as the base lead wire, the resistivity is low.
Base resistance can be significantly reduced.

This greatly increases the speed of the transistor. Materials for the base extraction electrode 22 include AI, Ti, M
A high melting point metal such as O, W, etc. or a silicide film thereof is used.

Next, the method for manufacturing the transistor of this embodiment will be explained using FIG. 2 to FIG. 10 together with FIG.

In FIG. 2, a p-type substrate 12 includes an n+ buried layer 13.degree. insulating isolation layer 14. An n-type epitaxial layer 15 is formed. After that, the base region 16 is formed.

In FIG. 3, after depositing polycrystalline silicon 17 on the entire surface, arsenic ions are implanted into the polycrystalline silicon 17 to form a 513N4 film 18 on the entire surface. A heat treatment is performed to form an n+ layer 19 in the n-type epitaxial layer. This region becomes the n+ emitter.

In FIG. 4, using the photoresist 20 as a mask, 51
3N4 membrane 18. Polycrystalline silicon: ff:/17. n+ layer 19
A convex emitter pattern is formed by etching.

In FIG. 6, selective oxidation is performed using the S 1 s N 4 film 18 as a mask. An 8102 film 21 is formed on the side surfaces of the polycrystalline silicon 17 and the surface of the base region 16. The thickness of this S102 film 21 is about 2000 to 3000. Next, the surface of the base region 16 is etched using anisotropic dry etching in which etching progresses only in the vertical direction.
Only the film 21 is removed. However, at this time, the 513N4 film is also slightly etched and becomes thinner. The 5102 film 21 remains on the side surfaces of the polycrystalline silicon 17 and the n+ emitter region 19.

In FIG. 6, a silicide film 22 of Al or a high melting point metal is deposited on the entire surface. In this figure, A4 is taken as an example. ), then a resist film 23 is applied. At this time, the resist film 23 is applied thinly to the convex portions and thickly to the concave portions. #) It is applied thinly on the S13N418 and thickly on the base region 16. The entire resist film 23 is etched using anisotropic dry etching to form a 5i3
Only the resist film on N418 is removed. base area 1
The resist film 23 on the resist film 6 is also etched, but it remains because it is thick.

In FIG. 7, using the resist film 23 as a mask, A11
Etch B. The A122 on the S13N418 and on the upper side of the polycrystalline silicon 17 is removed. Next, the resist film 23 is removed.

In FIG. 8, after a CvDS1o2 film 24 is deposited on the entire surface, a resist film 26 is applied on the entire surface. By the same method as described in FIG. 6, the resist film 26 is left only on the upper part of A122 on the base region. The upper part of the CVD3102 film 24 is exposed.

In FIG. 9, CVD is performed using the resist film 26 as a mask.
S 102 film 24 is completely removed. The CV D S 102 film 24 on top of the 5i3N418 is removed.

In FIG. 10, the resist film 26 is removed.

Finally, as shown in FIG. 10, after removing the 5t3N41 B, an Al film is deposited on the entire surface to form a base electrode 26 and an emitter electrode 26. The Ad film 24 is connected to the pace extraction electrode 22.

After that, the base electrode 26. After forming the emitter electrode 26 and the like, the transistor shown in FIG. 1 is completed.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, a reduction in pace collector capacitance and a significant reduction in pace resistance can be simultaneously achieved in a simple manner, so that semiconductors including ultra-high speed, low power consumption bipolar transistors can be realized. Integrated circuit devices have become possible and are extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a bipolar transistor according to an embodiment of the present invention, and FIGS. 2 to 10 are cross-sectional views for explaining the manufacturing process of the above bipolar transistor.
FIG. 1 is a sectional view showing a conventional bipolar transistor. 12...p-type substrate, 13...n+ buried layer, 14...isolation oxide film, 16...n
Shape collector, 16...Base area, 17...
...N+ emitter of polycrystalline Si, 19...n
+ Emitter, 21...Insulating film on the side of the emitter,
22...Metal thin film base extraction electrode, 24
...Insulating film covering metal thin film, 26...
...Base electrode, 26...Emitter electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure tt---pp5I antif7-9jt6δi4n"

Claims (1)

[Claims] A step of selectively forming a convex emitter region whose side surfaces are covered with a first insulating film in a predetermined opening on the semiconductor substrate, after forming a metal thin film or its silicide film on the entire surface, a step of selectively removing the metal thin film or its silicide film on the region that will become the convex emitter; and after forming a second insulating film on the entire surface, removing the second insulating film on the region that will become the convex emitter; A semiconductor integrated circuit device comprising the steps of: selectively removing an insulating film; and forming a base contact hole in a predetermined region of a second insulating film covering the metal thin film or its silicide film. Production method.