JPS63204649A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce series resistance of a collector and to obtain a transistor saturated at a lower voltage, by anisotropically etching an epitaxial layer on a semiconductor substrate for forming a groove excavated up to a buried collector layer and filling the groove with a metal for providing electrical connection to the buried collector layer. CONSTITUTION:A semiconductor device comprises a buried collector layer 1 formed on a semiconductor substrate, an epitaxial layer 2 on the buried collector layer 1, a base layer 5 in the epitaxial layer 2, an emitter layer 6 on the surface of the base layer 5, a groove 3 excavated from the surface of the epitaxial layer 2 up to the buried collector layer 1 and a metallic layer 4 in the groove. Thereby, the series resistance of the collector is decreased and a transistor saturated at a low voltage is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a low saturation type transistor.

[Conventional technology]

Conventionally, a low saturation type transistor is manufactured by forming an N+ type buried collector layer l on a semiconductor substrate, as shown in FIG.
An N-type epitaxial layer 2 is formed on the entire surface, a P-type base layer 5 and an N-type emitter layer 6 are formed in this N-type epitaxial layer 2, and an N+-type buried collector layer 1 and a collector electrode 7 are formed.
The space between them was connected through an N+ type diffusion layer 9, resulting in a structure in which series resistance was reduced.

[Problem that the invention seeks to solve]

However, in the conventional structure described above, the N+ type forming diffusion layer 9
In order to reduce the series resistance of the collector by increasing the concentration of impurity atoms diffused into the N-type epitaxial layer 2 to form the N-type epitaxial layer 2, the diffusion time becomes long and there is a limit due to constraints such as manufacturing cost and element size. was there.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a semiconductor device in which the series resistance of the collector is reduced.

[Means for solving problems]

A semiconductor device of the present invention includes a buried collector layer formed on a semiconductor substrate, an epitaxial layer formed on this buried collector layer, a base layer formed on this epitaxial layer, and a base layer formed on this epitaxial layer. The epitaxial layer includes an emitter layer formed on the surface, a groove formed from the surface of the epitaxial layer to the buried collector layer, and a metal layer buried in the groove.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

In FIG. 1, an N+ type buried collector layer 1 is formed on a semiconductor substrate, and an N type epitaxial layer 2 is formed on the entire surface including this buried collector layer 1. A P-type base layer is formed on the N-type epitaxial layer 2, and an N-type emitter layer 6 is formed on the surface of the F)-type base layer 5, forming transistors 1 to 1. In particular, a well 3 is formed reaching the N+ type buried collector layer 1 from the surface of the N type epitaxial layer 2, and the aluminum layer 4 buried in this groove 3 allows the N+ type buried collector layer 1 to become a collector layer. It is connected to electrode 7. The groove 3 can be formed by sputtering, and the aluminum layer 4 can be formed by CVD or the like.

In addition, in FIG. 1, 8 is an oxide film.

In the first embodiment configured in this manner, the N+ type buried collector layer 1 is connected to the collector electrode 7 through the aluminum R4, so that the series resistance of the collector is significantly reduced.

FIG. 2 is a cross-sectional view of a second embodiment of the present invention;
The difference from the first embodiment shown in the figure is that the present invention is applied to a vertical PNP transistor.

In other words, a part of the P+ type layer 11A which becomes the collector is 5vj
, a P+ type buried collector layer 11 is formed using a directional etching method.
In this structure, a groove 3 is formed to reach the depth of the groove 3, and the groove 3 is filled with an aluminum layer 4. In the second embodiment as well, the electrical resistance between the P+ type buried collector layer 11 and the collector electrode 7 can be reduced without increasing the impurity concentration of the P+ type layer 11A. This has the advantage of reducing collector resistance.

〔Effect of the invention〕

9 (2) As mentioned above, the present invention uses anisotropic etching in the epitaxial layer on a semiconductor substrate to form a groove up to the buried collector layer, embeds metal in the groove, and electrically connects the buried collector layer. By connecting the transistor to the transistor, the collector series resistance can be lowered, which has the effect of realizing a transistor with a lower saturation voltage than conventional transistors.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... N+ type buried collector layer, 2... N type epitaxial layer, 3... Groove, 4... Aluminum layer, 5...
・P type base layer, 6... N type emitter layer, 7... Collector' pole, 8... Oxide film, 9... N+ type diffusion layer, 11... P+ type buried collector layer , IIA...P+
type layer, 15...N type base layer, 16...P type emitter layer. Muscle II￥] 〃Dobuki Sho layer, Z/Ban 3 figure

Claims (1)

[Claims] a buried collector layer formed on a semiconductor substrate; an epitaxial layer formed on the buried collector layer; a base layer formed on the epitaxial layer; an emitter layer formed on the surface of the base layer; A semiconductor device comprising: a groove formed to reach the buried collector layer from the surface of an epitaxial layer; and a metal layer buried in the groove.