JP2817307B2 - Semiconductor protection element - Google Patents
Semiconductor protection elementInfo
- Publication number
- JP2817307B2 JP2817307B2 JP1686290A JP1686290A JP2817307B2 JP 2817307 B2 JP2817307 B2 JP 2817307B2 JP 1686290 A JP1686290 A JP 1686290A JP 1686290 A JP1686290 A JP 1686290A JP 2817307 B2 JP2817307 B2 JP 2817307B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- diffusion region
- type
- region
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体保護素子に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor protection device.
従来の半導体保護素子は第３図に示すように、Ｐ型シ
リコン基板１の上に選択的に設けたN+型埋込領域２と、
N+型埋込領域２を含む表面に設けたＮ型エピタキシャル
層４と、Ｎ型エピタキシャル層４の表面からN+型埋込領
域２に達するように設けた環状のN+型拡散領域３と、N+
型拡散領域３の内側のＮ型エピタキシャル層４の表面に
選択的に設けたP+型拡散領域５と、全面に設けた酸化シ
リコン膜７を開孔してP+型拡散領域５に接続して設けた
電極８と、N+型拡散領域３に接続して設けた電極９を有
して構成され、電極９を正極電源に、電極８を入力端子
及び内部回路素子にそれぞれ接続して使用される。As shown in FIG. 3, a conventional semiconductor protection element includes an N + type buried region 2 selectively provided on a P type silicon substrate 1,
N + -type buried region 2 N-type epitaxial layer 4 provided on the surface including an annular N + -type diffusion region 3 provided so as to reach from the surface of N-type epitaxial layer 4 in the N + buried region 2 , N +
The P + -type diffusion region 5 selectively provided on the surface of the N-type epitaxial layer 4 inside the type diffusion region 3 and the silicon oxide film 7 provided on the entire surface are opened to connect to the P + -type diffusion region 5. And an electrode 9 connected to the N + type diffusion region 3. The electrode 9 is connected to a positive electrode power supply, and the electrode 8 is connected to an input terminal and an internal circuit element. Is done.
上述した従来の半導体保護素子は、静電破壊に対する
保護効果を上げるには保護素子のダイオードの抵抗を小
さくする必要があるが、ダイオードの一方を構成する逆
導電型エピタキシャル層の抵抗が大きく、ダイオードの
抵抗を小さくするためには逆導電型エピタキシャル層に
設けた一導電型拡散領域とエピタキシャル層とのPN接合
面積を大きくしなければならないが、そのためには素子
領域の面積を広げなければならず、高集積化を妨げると
いう問題点がある。In the conventional semiconductor protection element described above, the resistance of the diode of the protection element must be reduced in order to increase the protection effect against electrostatic breakdown. In order to reduce the resistance of the device, the PN junction area between the one conductivity type diffusion region provided in the opposite conductivity type epitaxial layer and the epitaxial layer must be increased, but for that purpose, the area of the element region must be increased. However, there is a problem that high integration is hindered.
本発明の目的は、素子領域の面積を広げることはな
く、抵抗の小さい半導体保護素子を提供することにあ
る。An object of the present invention is to provide a semiconductor protection element having a small resistance without increasing the area of an element region.
本発明の第１の半導体保護素子は、一導電型半導体基
板上に設けた逆導電型の埋込領域と、前記埋込領域を含
む表面に設けた逆導電型のエピタキシャル層と、前記エ
ピタキシャル層の表面に設けて、前記埋込領域に達する
環状の逆導電型拡散領域と、前記逆導電型拡散領域内の
前記エピタキシャル層の表面に設けた凹部と、前記凹部
の内面に設けた一導電型の拡散領域と、前記凹部内を充
填して設けた低比抵抗の金属層とを有している。A first semiconductor protection element according to the present invention includes a reverse conductivity type buried region provided on a one conductivity type semiconductor substrate, a reverse conductivity type buried region provided on a surface including the buried region, and the epitaxial layer An annular reverse conductivity type diffusion region reaching the buried region, a recess provided in the surface of the epitaxial layer in the reverse conductivity type diffusion region, and one conductivity type provided on the inner surface of the recess. And a low resistivity metal layer provided by filling the recess.
本発明の第２の半導体保護素子は、一導電型半導体基
板上に設けた一導電型埋込領域と、前記一導電型埋込領
域を含む表面に設けた逆導電型のエピタキシャル層と、
前記エピタキシャル層の表面に設けて前記埋込領域に達
する一導電型の拡散領域と、前記一導電型拡散領域の表
面に設けた凹部と、前記凹部の内面に設けた逆導電型の
拡散領域と、前記凹部内を充填して設けた低比抵抗の金
属層とを有している。A second semiconductor protection element according to the present invention includes a one-conductivity-type buried region provided on a one-conductivity-type semiconductor substrate, and a reverse-conductivity-type epitaxial layer provided on a surface including the one-conductivity-type buried region.
One conductivity type diffusion region provided on the surface of the epitaxial layer and reaching the buried region, a concave portion provided on the surface of the one conductivity type diffusion region, and a reverse conductivity type diffusion region provided on the inner surface of the concave portion. And a metal layer having a low specific resistance provided by filling the inside of the concave portion.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ）は本発明の第１の実施例の製造
方法を説明するための工程順に示した半導体チップの断
面図である。FIGS. 1A and 1B are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a first embodiment of the present invention.
まず、第１図（ａ）に示すように、Ｐ型シリコン基板
１の表面にN+型埋込領域２を選択的に設け、N+型埋込領
域２を含む表面にＮ型にエピタキシャル層４を成長させ
る。次に、Ｎ型エピタキシャル層４の表面からN+型埋込
領域２に達する環状のN+型拡散領域３を設けた後、全面
に設けた酸化シリコン膜７及びＮ型エピタキシャル層４
を順次異方性のドライエッチングにて選択的にエッチン
グして凹部を設ける。次に、酸化シリコン膜７をマスク
として凹部内面にＰ型不純物を拡散し、P+型拡散領域５
を形成する。次に、気相成長法によりアルミニウム等の
低比抵抗の金属層６を堆積して凹部内を充填する。First, as shown in FIG. 1A, an N + -type buried region 2 is selectively provided on the surface of a P-type silicon substrate 1, and an N-type epitaxial layer is formed on the surface including the N + -type buried region 2. Grow 4. Next, after providing an annular N + -type diffusion region 3 reaching the N + -type buried region 2 from the surface of the N-type epitaxial layer 4, the silicon oxide film 7 and the N-type epitaxial layer 4
Are successively selectively etched by anisotropic dry etching to form recesses. Then, by diffusing P-type impurities into the recess inner surface a silicon oxide film 7 as a mask, P + -type diffusion region 5
To form Next, a low resistivity metal layer 6 such as aluminum is deposited by a vapor phase growth method to fill the recess.
次に、第１図（ｂ）に示すように、全面を異方性ドラ
イエッチングによりエッチバックし、凹部内にのみ金属
層６を埋込む。次に、N+型拡散領域３上の酸化シリコン
膜７を選択的に開孔し、正極電源に接続される電極９と
金属層６上に電極８を形成する。Next, as shown in FIG. 1B, the entire surface is etched back by anisotropic dry etching, and the metal layer 6 is buried only in the recess. Next, the silicon oxide film 7 on the N + type diffusion region 3 is selectively opened, and the electrode 8 connected to the positive electrode power supply and the metal layer 6 are formed.
第２図は本発明の第２の実施例の断面図である。 FIG. 2 is a sectional view of a second embodiment of the present invention.
第２図に示すように、Ｐ型シリコン基板１の表面にP+
型埋込領域10を設け、P+型埋込領域10を含む表面にＮ型
エピタキシャル層４を設ける。次に、Ｎ型エピタキシャ
ル層４にP+型埋込領域10に達するＰ型拡散領域11及びP+
型拡散領域12を設ける。次に、全面に設けた酸化シリコ
ン膜７及びＰ型拡散領域11を選択的に順次異方性エッチ
ングして凹部を設け、酸化シリコン膜７をマスクとして
凹部内面にＮ型不純物を拡散してN+型拡散領域13を形成
する。次に第１の実施例と同様にして凹部内に低比抵抗
の金属層６を埋込んだ後、P+型領域12上の酸化シリコン
膜７を開孔して、GND電源に接続される電極14と金属層
６上に電極８を形成する。As shown in FIG. 2, P +
The N type epitaxial layer 4 is provided on the surface including the P + type embedding region 10. Then, the N-type epitaxial layer 4 reaches the P + -type buried region 10 P type diffusion region 11 and P +
A mold diffusion region 12 is provided. Next, the silicon oxide film 7 and the P-type diffusion region 11 provided over the entire surface are selectively and sequentially anisotropically etched to form a concave portion, and the silicon oxide film 7 is used as a mask to diffuse an N-type impurity into the inner surface of the concave portion. A + type diffusion region 13 is formed. Next, a low resistivity metal layer 6 is buried in the concave portion in the same manner as in the first embodiment, and then the silicon oxide film 7 on the P + type region 12 is opened and connected to the GND power supply. The electrode 8 is formed on the electrode 14 and the metal layer 6.
この実施例は、保護用のPNダイオードを外部端子と、
GND電極との間に接続する場合の実施例である。In this embodiment, a PN diode for protection is connected to an external terminal,
This is an embodiment in the case where a connection is made between the GND electrode.
以上説明したように本発明は、保護素子のダイオード
を構成する一方の半導体領域に凹部を設け、凹部に形成
されたPN接合の内側の拡散層に低比抵抗の金属層を設け
ることによって、第１の実施例の場合P+型拡散領域５直
下のＮ型エピタキシャル層４の厚さが薄くなり素子領域
の面積を大きくすることなく抵抗の低減が図れ、さらに
凹部に低比抵抗の金属層を設けることによって、より抵
抗の低減が可能となる効果がある。As described above, the present invention provides a concave portion in one semiconductor region constituting a diode of a protection element, and a low specific resistance metal layer in a diffusion layer inside a PN junction formed in the concave portion. In the case of the first embodiment, the thickness of the N-type epitaxial layer 4 immediately below the P + -type diffusion region 5 is reduced, so that the resistance can be reduced without increasing the area of the element region. By providing such a structure, there is an effect that the resistance can be further reduced.
第２の実施例の場合には同様にＮ型拡散領域13直下の
Ｐ型拡散領域11の厚さを薄くすることによって抵抗の低
減が図れる効果がある。In the case of the second embodiment, similarly, the resistance can be reduced by reducing the thickness of the P-type diffusion region 11 immediately below the N-type diffusion region 13.
第１図（ａ），（ｂ）は本発明の第１の実施例の製造方
法を説明するための工程順に示した半導体チップの断面
図、第２図は本発明の第２の実施例の断面図、第３図
は、従来の半導体保護素子の断面図である。 １……Ｐ型シリコン基板、２……N+型埋込領域、３……
N+型拡散領域、４……Ｎ型エピタキシャル層、５……P+
型拡散領域、６……金属層、７……酸化シリコン膜、8,
9……電極、10……P+型埋込領域、11……Ｐ型拡散領
域、12……P+型拡散領域、13……N+型拡散領域、14……
電極。1 (a) and 1 (b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method of a first embodiment of the present invention, and FIG. 2 is a view of the second embodiment of the present invention. FIG. 3 is a sectional view of a conventional semiconductor protection element. 1 ... P-type silicon substrate, 2 ... N + type buried region, 3 ...
N + type diffusion region, 4 ... N-type epitaxial layer, 5 ... P +
Mold diffusion region, 6 metal layer, 7 silicon oxide film, 8,
9 ... electrode, 10 ... P + type buried region, 11 ... P type diffusion region, 12 ... P + type diffusion region, 13 ... N + type diffusion region, 14 ...
electrode.
Claims (2)
埋込領域と、前記埋込領域を含む表面に設けた逆導電型
のエピタキシャル層と、前記エピタキシャル層の表面に
設けて、前記埋込領域に達する環状の逆導電型拡散領域
と、前記逆導電型拡散領域内の前記エピタキシャル層の
表面に設けた凹部と、前記凹部の内面に設けた一導電型
の拡散領域と、前記凹部内を充填して設けた低比抵抗の
金属層とを有することを特徴とする半導体保護素子。A buried region of a reverse conductivity type provided on a semiconductor substrate of one conductivity type, an epitaxial layer of a reverse conductivity type provided on a surface including the buried region, and provided on a surface of the epitaxial layer; An annular reverse conductivity type diffusion region reaching the buried region, a recess provided on the surface of the epitaxial layer in the reverse conductivity type diffusion region, and a one conductivity type diffusion region provided on the inner surface of the recess; A low-resistance metal layer provided by filling the inside of the recess.
込領域と、前記一導電型埋込領域を含む表面に設けた逆
導電型のエピタキシャル層と、前記エピタキシャル層の
表面に設けて前記埋込領域に達する一導電型の拡散領域
と、前記一導電型拡散領域の表面に設けた凹部と、前記
凹部の内面に設けた逆導電型の拡散領域と、前記凹部内
を充填して設けた低比抵抗の金属層とを有することを特
徴とする半導体保護素子。2. A buried region of one conductivity type provided on a semiconductor substrate of one conductivity type, an epitaxial layer of the opposite conductivity type provided on a surface including the buried region of one conductivity type, and provided on a surface of the epitaxial layer. A diffusion region of one conductivity type reaching the buried region, a recess provided on the surface of the diffusion region of one conductivity type, a diffusion region of the opposite conductivity type provided on the inner surface of the recess, and filling the inside of the recess. And a metal layer having a low specific resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1686290A JP2817307B2 (en) | 1990-01-25 | 1990-01-25 | Semiconductor protection element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1686290A JP2817307B2 (en) | 1990-01-25 | 1990-01-25 | Semiconductor protection element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03220779A JPH03220779A (en) | 1991-09-27 |
| JP2817307B2 true JP2817307B2 (en) | 1998-10-30 |
Family
ID=11928030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1686290A Expired - Lifetime JP2817307B2 (en) | 1990-01-25 | 1990-01-25 | Semiconductor protection element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2817307B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3485081B2 (en) * | 1999-10-28 | 2004-01-13 | 株式会社デンソー | Semiconductor substrate manufacturing method |
| JP5206104B2 (en) * | 2008-05-13 | 2013-06-12 | 株式会社デンソー | Zener diode manufacturing method |
-
1990
- 1990-01-25 JP JP1686290A patent/JP2817307B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03220779A (en) | 1991-09-27 |
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