JPH0258265A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of breakdown strength of a collector base junction after writing, even if an epitaxial layer is thinned, to facilitate high density integration, and increase writing yield and reliability by constituting a base region, of a deep impurity region of low concentration and of a shallow impurity region of high concentration. CONSTITUTION:The title device is provided with the following; a collector region 2 of inverse conductivity type formed on a semiconductor substrate 1 of one conductivity type, a low concentration base region 5 of one conductivity type formed deeply in the collector region 2, a high concentration base region 6 of one conductivity type formed to a shallow depth in the low concentration base region 5, and an emitter region 7 of inverse conductivity type formed in the high concentration base region 6. For example, on the main surface of the P-type Si substrate 1, the N<+> type buried layer 2 for a collector region is arranged, on the surface of which an N-type epitaxial layer 3 is arranged. After a silicon oxide layer 4 reaching the buried layer 2 is arranged, the P<-> type base region 5 is arranged by deeply introducing P-type impurity, and the P<+> type base region 6 is arranged by introducing P-type impurity to a shallow depth. Next, the N-type emitter region 7 is arranged by introducing N-type impurity through a polycrystalline Si layer 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a programmable read-only memory element.

[Conventional technology]

Programmable read-only memory element (FROM)
In view of its intended use, high density storage capacity and reliable programming are particularly desired.

FIG. 4 is a cross-sectional view of a semiconductor chip for explaining a conventional semiconductor memory device. An N+ type buried layer 2 is formed on a P type silicon substrate 1, and an N type epitaxial layer 3 is formed on the surface including the N+ type buried layer 2. Next, the N-type epitaxial layer 3 is selectively oxidized to form a silicon oxide film 4 that reaches the N+-type buried layer 2 to define an element formation region. next,
A P+ type base region 6 is provided in the element formation region, and a P+ type base region 6 is provided in the element forming region.
A polycrystalline silicon layer 8 is provided on the surface including the opening provided on the mold base region 6, and P+
N type impurities are introduced into type base region 6 to provide N+ type emitter region 7. Next, an aluminum layer 9 is deposited on the polycrystalline silicon layer 8, and the aluminum layer 9 and the polycrystalline silicon layer 8 are selectively and sequentially etched to form an emitter electrode.

When writing information, an overcurrent is applied to the emitter-base junction and the base-collector junction to destroy only the reverse biased emitter-base junction. The spike 10 may destroy not only the emitter-base junction but also the base-collector junction.

[Problem to be solved by the invention]

In the conventional semiconductor memory device mentioned above, the thickness of the epitaxial layer is made thinner, the overall junction is made shallower, and the spacing between elements is narrowed to achieve higher integration. Therefore, the withstand voltage of the entire element is low, and in order to prevent write current leakage, it is necessary to reduce the resistance component of the memory cell and suppress the voltage drop. In order to suppress this voltage drop, impurities in the base region of the memory cell! The depth of the base-collector junction was controlled to increase the IJ7J concentration and obtain the minimum necessary withstand voltage. For example, the concentration of boron impurities in the base region is about 1019 cIo-3, and the depth of the base-collector junction is about 0.6 μm. Therefore, the write spike that occurs during writing destroys not only the base-emitter junction but also the collector-base junction breakdown voltage, reducing the collector-base junction breakdown voltage. At times, leakage of write current occurs, making writing impossible or insufficient writing, which has the drawback of deteriorating the writing yield of the semiconductor memory device and deteriorating its quality.

[Means to solve the problem]

The semiconductor recording device of the present invention includes a collector region of an opposite conductivity type provided on a semiconductor substrate of a -conductivity type, a low concentration base region of one conductivity type provided deeply within the collector region, and a low concentration base region of one conductivity type provided deeply within the collector region. It has a shallowly provided highly doped base region of one conductivity type and an emitter region of the opposite conductivity type provided within the highly doped base region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.9 FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

As shown in FIG. 1, an N+ type buried layer 2 for a collector region is provided on the main surface of a P type silicon substrate 1.
N-type epitaxy cell P! on the surface containing 3 will be provided. Next, silicon oxide M4 is provided by selectively oxidizing the N type epitaxial layer 3 to reach the N+ type buried layer 2, thereby defining an element formation region. Next, P-type low concentration impurities are deeply introduced into the element forming region to form a P- type base region 5, and further P-type high concentration impurities are introduced shallowly to form a P+ type base region 6. Next, a polycrystalline silicon layer 8 is provided on the surface including the opening provided above the P+ type base region 6, and an N-type impurity is introduced into the P+ type base region 6 through the polycrystalline silicon layer 8 to form an N-type Formation of emitter region 7 Next, an aluminum layer 9 is deposited on the polycrystalline silicon layer 8, and the aluminum layer 9 and the polycrystalline silicon layer 8 are selectively and sequentially etched to form an emitter electrode.

In such a structure, since the collector-base junction can be formed deeply, the alloy spike formed during writing does not reach the collector-base junction, and deterioration of the withstand voltage of the collector-base junction can be prevented.

Furthermore, since the shallow P+ type base region 6 containing highly concentrated impurities is provided, the resistance component of the memory cell is also small, and the withstand voltage of the entire device can be kept low.

Furthermore, it is preferable that the deep P-type base region 5 containing low concentration impurities has its impurity concentration suppressed to a withstand voltage that does not itself become a source of write current leakage. Based on the impurity concentration profile, the depth of the base-collector junction for low concentration impurities was set at 1.3 m (1 m).
Conventionally, the impurity concentration was 0.6 μm) 10]6 to 1017
When cI11-3 (the impurity is boron), the collector-base junction breakdown voltage is about 20V when the epitaxial layer has a thickness of 2.0 μrn. This is because, as is well known, when a reverse voltage is applied between the collector-base junction, the depletion layer extends well toward the side with lower impurity concentration (base side), making it difficult for the electric field strength to increase.

In this way, by forming the base region of the memory cell of the present invention into a double structure consisting of a deep low-concentration impurity region and a shallow high-concentration impurity region, the memory cell can be used without deteriorating the collector-base junction after writing. Since the resistance component of the cell can also be reduced, it is easy to achieve high integration, and the write yield and reliability can be improved. Furthermore, since the present invention can form a double base of a memory cell using a self-aligned cell line, there is no need to increase the number of manufacturing steps.

FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention. This case is an example in which the film thickness of the epitaxial layer is made thinner in order to achieve higher integration.

As shown in FIG. 3, a low concentration P-type impurity is introduced throughout the N-type epitaxial layer 3, and a P- type base region 5 reaching the N+-type buried layer 2 is provided. It has the same configuration as the example, and with this structure, even if the epitaxial layer is thin, the collector-base junction of the memory cell can be made sufficiently deep, so that the alloy spike will not reach the collector-base junction in the event of damage. Therefore, it is possible to obtain collector-base junction breakdown voltage without deterioration. Therefore, there is an advantage that higher integration becomes easier.

〔Effect of the invention〕

As explained above, in the present invention, by configuring the base region of a junction breakdown type memory cell with a deep low-concentration impurity region and a shallow high-concentration impurity region, even if the thickness of the epitaxial layer is reduced, the collector Base junction breakdown voltage does not deteriorate.

Further, as in the conventional case, since the resistance component of the memory cell is small, the withstand voltage of the entire device can also be kept low. Therefore, there is an effect that it is possible to provide a semiconductor memory device that can easily achieve high integration and improve write yield and reliability.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor chip for explaining the first embodiment of the present invention, FIG. 2 is a diagram showing the impurity concentration profile of the base region of the present invention, and FIG. FIG. 4 is a cross-sectional view of a semiconductor chip for explaining a conventional semiconductor memory device. l...P type silicon substrate, 2...N' type buried layer, 3...
...N-type epitaxial layer, 4...silicon oxide film,
5... P- type base region, 6... P+ type base region, 7... N-type emitter region, 8... Polycrystalline silicon layer, 9... Aluminum layer, 10... Alloy spike . Akira 1 figure

Claims (1)

[Claims] A collector region of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, a low concentration base region of one conductivity type provided deeply within the collector region, and a high concentration base region of one conductivity type provided shallowly within the low concentration base region. A semiconductor memory device comprising a doped base region and an emitter region of opposite conductivity type provided within the heavily doped base region.