JP2596132Y2 - Semiconductor device - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bipolar IC having a plurality of circuit elements such as NPN transistors having a predetermined characteristic ratio based on the area of a pattern formed on a substrate. It is.

[0002]

2. Description of the Related Art Conventionally, as such a semiconductor device, a bipolar IC is configured as shown in FIG. 2, for example.

That is, in FIG. 2, a bipolar IC 1
Forms an n + -type buried layer 3 on the surface of a p-type silicon substrate 2 by thermal diffusion or the like, and forms an n-type layer 4 by epitaxial growth over the entire surface of the substrate 2. The n-type layer 4 is separated by forming the p + -type layer 5 around the n-type layer 4.

Subsequently, similarly, a p-type base layer 6 and an n + -type collector layer 7 are formed on the surface of the n-type layer 4 by thermal diffusion, and the surface of the p-type base layer 6 is thermally diffused. To form an n + -type emitter layer 8,
Base layer 6, n + type collector layer 7 and n + type layer 8
Are formed by forming contact portions 6a, 7a, 8a on the surface of the.

According to the bipolar IC 1 thus configured, the p-type base layer 6, the n + -type collector layer 7, and the n-type
By the + type emitter layer 8 acting as the base, collector and emitter of the transistor, respectively,
An NPN transistor can be formed on the substrate 2.

[0006]

However, according to the bipolar IC 1 having such a structure, when the bipolar IC 1 is manufactured, in the epitaxial growth step, as shown in FIG. A shift occurs, and a part of the p-type base layer 6 is separated from the upper part of the n + -type buried layer 3, so that an ideal sectional structure cannot be obtained.

Therefore, for example, as shown in FIG. 4, when a plurality (two in the illustrated case) of NPN transistors are formed on the substrate 2, the characteristic ratio generally becomes good. As described above, the p-type base layer 6 and the n + -type emitter layer 8 are arranged so as to be arranged in a line along the direction of the pattern shift, and the NPN on the right side in the drawing.
In the transistor, two n + type emitter layers 8
b, 8c, the base and emitter areas are formed differently as compared to the left NPN transistor, but due to the pattern shift during epitaxial growth, the left and right NPN transistors Since the n + type buried layer 3 is shifted to the left by the same width in the drawing, the area of the n-type base layers 6b and 6c that deviates from the upper part of the buried layer 3 is substantially the same. Therefore, the n-type base layers 6b and 6c and the n-type base layers 6b and 6c
The area ratios to the + type emitter layers 8b and 8c are different from each other, so that a desired characteristic ratio based on the pattern area ratio cannot be satisfactorily obtained, and there is a problem that the characteristic variation increases.

Further, for this reason, the pattern area must be determined in consideration of the effect of the pattern shift at the design stage, which causes a problem that the design work becomes complicated.

In view of the above, it is an object of the present invention to provide a semiconductor device which can easily obtain a characteristic ratio based on an emitter area ratio even when affected by a pattern shift.

[0010]

An object of the present invention is to provide a semiconductor device having a plurality of bipolar transistors having a predetermined characteristic ratio based on the area of a pattern formed side by side on a substrate. The buried layer is arranged side by side in the direction perpendicular to the direction of the pattern shift, has the same length in the direction of the pattern shift, and , Having a width corresponding to the area ratio, wherein the pattern is affected by the pattern shift at the same area ratio.

[0011]

According to the above arrangement, each pattern is composed of a pattern
With respect to the direction of the shift, they have the same length, and the area is determined by the width. Therefore, the part of the pattern deviating from the upper part of the buried layer due to the pattern shift of the buried layer by epitaxial growth is the pattern As for the direction of the shift, since they have the same length, their area is
It is determined by the width of the pattern, the area ratio to the pattern is constant regardless of the area,
Therefore, the characteristic ratio based on the area ratio of the pattern is
A desired characteristic ratio can be obtained without being changed by the shift.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. FIG. 1 shows a bipolar IC according to the present invention.
1 shows an embodiment applied to the present invention.

The bipolar IC 10 forms an n + -type buried layer (not shown) on the surface of the p-type silicon substrate 11 by thermal diffusion or the like, and epitaxially grows the n + -type buried layer over the entire surface of the substrate 11. After forming the mold layer 12, the p-type layer 13 is formed around the n-type layer 12, thereby separating the n-type layer 12.

Further, in the same manner, a p-type base layer 14 and an n + -type collector layer 15 are formed on the surface of the n-type layer 12 by thermal diffusion, and the surface of the p-type base layer 14 is formed by thermal diffusion. An n + type emitter layer 16 is formed, and finally, a contact portion 1 is formed on the surface of the p type base layer 14, the n + type collector layer 15 and the n + type emitter layer 16, respectively.
7, 18, and 19 are formed.

The above configuration is the same as that of the conventional bipolar IC 1 shown in FIG. 4, but in the bipolar IC 10 according to the present invention, the pattern formed by the emitter layer 16 is the same as that used in the epitaxial growth of the n-type layer 12 described above. Are arranged side by side in the direction y perpendicular to the pattern shift direction x of the n-type buried layer generated at the same time, and have the same length with respect to the pattern shift direction x;
In addition, it has a width corresponding to the area ratio in the direction y perpendicular to it.

The bipolar IC 10 according to the present invention is configured as described above, and includes the p-type base layer 14 and the n +
Each pattern of the mold emitter layer 16 has the same length in the direction x of the pattern shift, and the area is determined by the width.

Therefore, the portion of the pattern deviating from the upper part of the buried layer due to the pattern shift of the buried layer due to the epitaxial growth (shown by hatching in FIG. 1) has the same length in the direction x of the pattern shift. So that
The area is determined by the width of the pattern, and the area ratio to the pattern is constant regardless of the area.

As described above, since the patterns of the p-type base layer 14 and the n + -type emitter layer 16 are affected by the above-mentioned pattern shift at the same rate, the area ratio between the patterns remains unchanged. Accordingly, a desired characteristic ratio can be obtained without changing the characteristic ratio based on the area ratio of the pattern due to the pattern shift.

[0019]

As described above, according to the present invention, even if it is affected by the pattern shift, the characteristic ratio can be easily obtained by the emitter area ratio, and the variation in the characteristics can be reduced. An extremely excellent semiconductor device having high matching characteristics can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing one embodiment of a semiconductor device according to the present invention.

2A and 2B show an example of a conventional semiconductor device, wherein FIG. 2A is a plan view and FIG. 2B is a cross-sectional view.

3 is a cross-sectional view showing a shift of a buried layer due to a pattern shift in the semiconductor device of FIG.

4A and 4B show another example of a conventional semiconductor device, wherein FIG. 4A is a plan view and FIG. 4B is a cross-sectional view.

[Explanation of symbols]

 Reference Signs List 10 semiconductor device 11 p-type silicon substrate 12 n-type layer 13 p + -type layer 14 p-type base layer 15 n + -type collector layer 16 n + -type emitter layer 17, 18, 19

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 21/8222 H01L 21/8222-21/8228 H01L 21/8232 H01L 27/06 H01L 27/08 H01L 27 / 082

Claims (1)

(57) [Scope of request for utility model registration] 1. A plurality of bipolar transistors having a predetermined characteristic ratio based on the area of a pattern formed side by side on a substrate
In the semiconductor device provided with the transistor , the pattern is arranged in a direction perpendicular to the direction of the pattern shift of the buried layer at the time of pattern formation, and is the same in the direction of the pattern shift. Having a length and a width corresponding to an area ratio in a direction perpendicular to the length, wherein the pattern is affected by the same area ratio due to the pattern shift. Semiconductor device.