JP2002184985A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2002184985A JP2002184985A JP2000383440A JP2000383440A JP2002184985A JP 2002184985 A JP2002184985 A JP 2002184985A JP 2000383440 A JP2000383440 A JP 2000383440A JP 2000383440 A JP2000383440 A JP 2000383440A JP 2002184985 A JP2002184985 A JP 2002184985A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- silicon single
- type silicon
- peripheral portion
- super junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 60
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000002093 peripheral effect Effects 0.000 claims description 76
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 105
- 229910052710 silicon Inorganic materials 0.000 abstract description 105
- 239000010703 silicon Substances 0.000 abstract description 105
- 239000013078 crystal Substances 0.000 abstract description 98
- 230000005669 field effect Effects 0.000 abstract description 35
- 230000015556 catabolic process Effects 0.000 abstract description 30
- 239000012535 impurity Substances 0.000 description 20
- 238000004088 simulation Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、スーパージャンク
ション構造部を有する半導体装置に関する。The present invention relates to a semiconductor device having a super junction structure.
【０００２】[0002]
【背景技術】縦型ＭＯＳ電界効果トランジスタに代表さ
れる縦型半導体装置は、例えば、家庭用電気機器や自動
車のモータの電力変換や電力制御に使われる。縦型半導
体装置のうち、スーパージャンクション構造部を備えた
ものが、例えば、特開平１１−２３３７５９号公報や特
開平９−２６６３１１号公報に開示されている。スーパ
ージャンクション構造部とは、第１導電型の第１半導体
領域と第２導電型の第２半導体領域とが交互に、半導体
基板上に並ぶ構造のことである。この構造部によれば、
シリコンリミットを超える性能を実現できるので、縦型
半導体装置の低オン抵抗化を図るには有効である。2. Description of the Related Art A vertical semiconductor device typified by a vertical MOS field-effect transistor is used, for example, for power conversion and power control of home electric appliances and motors of automobiles. Among the vertical semiconductor devices, those having a super junction structure are disclosed in, for example, JP-A-11-233759 and JP-A-9-26631. The super junction structure is a structure in which first semiconductor regions of the first conductivity type and second semiconductor regions of the second conductivity type are alternately arranged on the semiconductor substrate. According to this structure,
Since the performance exceeding the silicon limit can be realized, it is effective to reduce the on-resistance of the vertical semiconductor device.
【０００３】[0003]
【発明が解決しようとする課題】スーパージャンクショ
ン構造部は、終端にある半導体領域のところで、第１導
電型の半導体領域と第２導電型の半導体領域とが交互に
並ぶ構造が終わる。よって、スーパージャンクション構
造部の終端にある半導体領域をいかにするかが問題とな
る。何ら手段を施さないと、第１導電型の半導体領域と
第２導電型の半導体領域との接合耐圧より、電圧が大き
くなると、スーパージャンクション構造部の終端にある
半導体領域のところで、絶縁破壊が起こる。その結果、
シリコンリミットを超える耐圧を実現できなくなるので
ある。In the super junction structure, a structure in which semiconductor regions of the first conductivity type and semiconductor regions of the second conductivity type are alternately arranged at the terminal semiconductor region ends. Therefore, there is a problem how to make the semiconductor region at the end of the super junction structure part. If no measures are taken, if the voltage becomes larger than the junction breakdown voltage between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, dielectric breakdown occurs at the semiconductor region at the end of the super junction structure. . as a result,
It is impossible to realize a withstand voltage exceeding the silicon limit.
【０００４】本発明の目的は、高耐圧な半導体装置を提
供することである。An object of the present invention is to provide a semiconductor device having a high breakdown voltage.
【０００５】[0005]
【課題を解決するための手段】本発明は、縦型半導体素
子を備えた半導体装置であって、第１導電型の半導体基
板と、電極部と、前記半導体基板と前記電極部との間に
位置し、第１導電型の第１半導体領域と第２導電型の第
２半導体領域とが、前記半導体基板上で交互に並ぶ構造
部と、を備え、前記半導体基板と前記第１半導体領域と
は電気的に導通され、前記構造部は、前記縦型半導体素
子の形成部と、前記形成部の周辺に位置し、前記構造部
の終端を含む周辺部と、を含み、前記電極部は、前記構
造部の終端と距離を設けた位置にあり、かつ、前記周辺
部を構成する前記第２半導体領域と電気的に導通されて
いる。SUMMARY OF THE INVENTION The present invention relates to a semiconductor device having a vertical semiconductor element, comprising a semiconductor substrate of a first conductivity type, an electrode portion, and a space between the semiconductor substrate and the electrode portion. A first conductive type first semiconductor region and a second conductive type second semiconductor region, wherein the first and second semiconductor regions are alternately arranged on the semiconductor substrate. Is electrically conductive, the structure portion includes a formation portion of the vertical semiconductor element, a peripheral portion located around the formation portion, including a termination of the structure portion, the electrode portion, It is located at a distance from the end of the structure, and is electrically connected to the second semiconductor region forming the peripheral portion.
【０００６】第１導電型の第１半導体領域と第２導電型
の第２半導体領域とが、半導体基板上で交互に並ぶ構造
部とは、スーパージャンクション構造部のことである。
本発明は、構造部の終端と距離を設けた位置にあり、か
つ、周辺部を構成する第２半導体領域と電気的に導通さ
れている電極部を備える。このため、構造部の内部にお
いて、構造部の終端に向けて空乏層を広げることが可能
となるほか、構造部のうち、電極部が配置されている側
において、構造部の終端に向けて空乏層を広げることが
可能となる。これにより、構造部のうち、電極部が配置
されている側（つまり、構造部の表面近傍）の電界集中
を緩和できるので、半導体装置の耐圧向上が可能とな
る。この結果、本発明によれば、シリコンリミットを超
える耐圧を得ることが可能となる。A structure in which first semiconductor regions of the first conductivity type and second semiconductor regions of the second conductivity type are alternately arranged on a semiconductor substrate is a super junction structure.
The present invention includes an electrode portion which is located at a distance from the end of the structural portion and which is electrically connected to the second semiconductor region forming the peripheral portion. Therefore, the depletion layer can be expanded toward the end of the structure inside the structure, and the depletion toward the end of the structure on the side of the structure where the electrode is disposed. It is possible to expand the layer. Thus, the concentration of the electric field on the side of the structure where the electrode portion is arranged (that is, near the surface of the structure) can be reduced, so that the breakdown voltage of the semiconductor device can be improved. As a result, according to the present invention, it is possible to obtain a withstand voltage exceeding the silicon limit.
【０００７】本発明は、前記電極部と前記周辺部との間
に位置し、前記周辺部の前記第２半導体領域および前記
電極部と電気的に導通する、第２導電型の第３半導体領
域を備える。According to the present invention, a third semiconductor region of a second conductivity type is located between the electrode portion and the peripheral portion and is electrically connected to the second semiconductor region and the electrode portion in the peripheral portion. Is provided.
【０００８】本発明によれば、スーパージャンクション
により基板内を完全空乏化できること、及び、基板表面
近傍の空乏層を伸ばすことにより電界集中を緩和でき
る。よって、耐圧を、さらに、向上させることが可能と
なる。According to the present invention, the inside of the substrate can be completely depleted by the super junction, and the electric field concentration can be reduced by extending the depletion layer near the substrate surface. Therefore, the withstand voltage can be further improved.
【０００９】本発明は、前記周辺部の内部に位置し、前
記周辺部の前記第１半導体領域同士を導通させる、第１
導電型の第４半導体領域を備える。According to the present invention, there is provided a semiconductor device according to the first aspect, wherein the first semiconductor regions are located inside the peripheral portion and the first semiconductor regions in the peripheral portion are electrically connected to each other.
A fourth semiconductor region of a conductivity type is provided.
【００１０】本発明によれば、半導体装置のＯＦＦ時
に、半導体基板および電極部に電圧が印加されると、空
乏層は、垂直電界と水平電界とに分割される。特に、水
平電界により、低電圧時のリーク電流低減に効果があ
る。According to the present invention, when a voltage is applied to the semiconductor substrate and the electrode portion when the semiconductor device is turned off, the depletion layer is divided into a vertical electric field and a horizontal electric field. In particular, the horizontal electric field is effective in reducing the leak current at a low voltage.
【００１１】[0011]
【発明の実施の形態】［第１実施形態］図１は、本発明
の第１実施形態の断面図である。第１実施形態は、縦型
ＭＯＳ電界効果トランジスタ１に本発明を適用してい
る。縦型ＭＯＳ電界効果トランジスタ１の大まかな構造
を説明する。縦型ＭＯＳ電界効果トランジスタ１は、多
数のセル３９（つまり、多数の縦型半導体素子）で構成
される。セル３９は、縦型ＭＯＳ電界効果トランジスタ
１の動作の一単位となる。セル３９は、図１の紙面に対
して、左右方向および垂直方向に並んでいる。スーパー
ジャンクション構造部１３は、セル３９の形成部１３ａ
と、形成部１３ａの周辺に位置する周辺部１３ｂと、を
含む。第１実施形態は、電極部３１と周辺部１３ｂのＰ
型シリコン単結晶領域１５（１５ａ）とを接続すること
により、電極部３１とＰ型シリコン単結晶領域１５（１
５ａ）とを電気的に導通したことを特徴の一つする。[First Embodiment] FIG. 1 is a sectional view of a first embodiment of the present invention. In the first embodiment, the present invention is applied to a vertical MOS field-effect transistor 1. A rough structure of the vertical MOS field effect transistor 1 will be described. The vertical MOS field-effect transistor 1 includes a large number of cells 39 (that is, a large number of vertical semiconductor elements). The cell 39 is one unit of the operation of the vertical MOS field-effect transistor 1. The cells 39 are arranged in the left-right direction and the vertical direction with respect to the paper surface of FIG. The super junction structure 13 includes a formation portion 13 a of the cell 39.
And a peripheral portion 13b located around the formation portion 13a. In the first embodiment, the electrode portion 31 and the P
The electrode portion 31 is connected to the P-type silicon single crystal region 15 (1a) by connecting the
5a) is electrically conducted.
【００１２】次に、縦型ＭＯＳ電界効果トランジスタ１
の詳細な構造を説明する。縦型ＭＯＳ電界効果トランジ
スタ１は、Ｎ+型ドレイン領域１１、スーパージャンク
ション構造部１３およびＮ+型ソース領域２１を備えて
いる。Ｎ+型ドレイン領域１１は、シリコン基板に形成
されている。このシリコン基板下には、例えば、アルミ
ニウムからなる電極部１４が取り付けれている。Next, the vertical MOS field effect transistor 1
Will be described in detail. The vertical MOS field effect transistor 1 includes an N + type drain region 11, a super junction structure portion 13, and an N + type source region 21. The N + type drain region 11 is formed on a silicon substrate. An electrode portion 14 made of, for example, aluminum is attached below the silicon substrate.
【００１３】Ｎ+型ドレイン領域１１上には、スーパー
ジャンクション構造部１３が位置している。スーパージ
ャンクション構造部１３は、Ｐ型シリコン単結晶領域１
５とＮ型シリコン単結晶領域１７とが、Ｎ+型ドレイン
領域１１（シリコン基板）上で交互に並んでいる。Ｎ型
シリコン単結晶領域１７は、ドリフト領域であり、電流
はドリフト領域を流れる。スーパージャンクション構造
部１３の終端１３ｂ１は、周辺部１３ｂに含まれてい
る。A super junction structure 13 is located on the N + type drain region 11. The super junction structure 13 is a P-type silicon single crystal region 1
5 and N-type silicon single crystal regions 17 are alternately arranged on the N + -type drain region 11 (silicon substrate). N-type silicon single crystal region 17 is a drift region, and current flows through the drift region. The end 13b1 of the super junction structure 13 is included in the peripheral portion 13b.
【００１４】スーパージャンクション構造部１３の外側
には、Ｎ型シリコン単結晶領域１２が位置している。Ｎ
型シリコン単結晶領域１２が縦型ＭＯＳ電界効果トラン
ジスタ１の側部となる。Ｎ型シリコン単結晶領域１２
は、Ｎ型シリコン単結晶領域１７とＮ型不純物濃度が同
じである。The N-type silicon single crystal region 12 is located outside the super junction structure 13. N
The silicon single crystal region 12 is a side portion of the vertical MOS field effect transistor 1. N-type silicon single crystal region 12
Has the same N-type impurity concentration as the N-type silicon single crystal region 17.
【００１５】形成部１３ａ上には、Ｐ型シリコン単結晶
領域１９が位置している。Ｐ型シリコン単結晶領域１９
には、Ｎ型シリコン単結晶領域１７に到達するトレンチ
２３が形成されている。トレンチ２３には、例えば、ポ
リシリコン膜からなるトレンチゲート電極２５が埋め込
まれている。トレンチ２３の底面とトレンチゲート電極
２５との間、およびトレンチ２３の側面とトレンチゲー
ト電極２５との間には、例えば、シリコン酸化膜からな
るゲート絶縁膜２７が形成されている。Ｐ型シリコン単
結晶領域１９のうち、トレンチ２３の側面に沿った領域
にチャネルが形成される。Ｎ+型ソース領域２１は、ト
レンチ２３の周囲であって、かつＰ型シリコン単結晶領
域１９の表面に位置している。Ｐ型シリコン単結晶領域
１９上および周辺部１３ｂ上には、例えば、シリコン酸
化膜からなる絶縁膜２９が位置している。絶縁膜２９に
は、Ｎ+型ソース領域２１の一部およびＰ型シリコン単
結晶領域１９の一部を露出させるコンタクトホール３７
が形成されている。また、絶縁膜２９には、Ｐ型シリコ
ン単結晶領域１５（１５ａ）を露出させるコンタクトホ
ール３５が形成されている。Ｐ型シリコン単結晶領域１
５（１５ａ）は、スーパージャンクション構造部１３の
終端１３ｂ１から離れた位置にある。A P-type silicon single crystal region 19 is located on formation portion 13a. P-type silicon single crystal region 19
A trench 23 reaching the N-type silicon single crystal region 17 is formed. A trench gate electrode 25 made of, for example, a polysilicon film is embedded in the trench 23. A gate insulating film 27 made of, for example, a silicon oxide film is formed between the bottom surface of the trench 23 and the trench gate electrode 25 and between the side surface of the trench 23 and the trench gate electrode 25. In the P-type silicon single crystal region 19, a channel is formed in a region along the side surface of the trench 23. N + type source region 21 is located around trench 23 and on the surface of P type silicon single crystal region 19. An insulating film 29 made of, for example, a silicon oxide film is located on P-type silicon single crystal region 19 and peripheral portion 13b. A contact hole 37 exposing a part of the N + type source region 21 and a part of the P type silicon single crystal region 19 is formed in the insulating film 29.
Is formed. In the insulating film 29, a contact hole 35 exposing the P-type silicon single crystal region 15 (15a) is formed. P-type silicon single crystal region 1
5 (15a) is located away from the terminal end 13b1 of the super junction structure 13.
【００１６】絶縁膜２９上には、例えば、アルミニウム
からなる電極部３１が位置している。電極部３１は、コ
ンタクトホール３７、３９に充填されている。これらを
介して電極部３１は、Ｎ+型ソース領域２１、Ｐ型シリ
コン単結晶領域１９、Ｐ型シリコン単結晶領域１５（１
５ａ）と接続されている。An electrode portion 31 made of, for example, aluminum is located on the insulating film 29. The electrode portion 31 is filled in the contact holes 37 and 39. Through these, the electrode portion 31 is connected to the N + type source region 21, the P type silicon single crystal region 19, and the P type silicon single crystal region 15 (1
5a).
【００１７】次に、第１実施形態の主な効果を説明す
る。電極部３１は、スーパージャンクション構造部１３
の終端１３ｂ１と距離を設けた位置にあり、かつ、周辺
部１３ｂを構成するＰ型シリコン単結晶領域１５（１５
ａ）と電気的に接続されている。このため、スーパージ
ャンクション構造部１３の内部において、終端１３ｂ１
に向けて空乏層を広げることが可能となるほか、スーパ
ージャンクション構造部１３のうち、電極部３１が配置
されている側において、終端１３ｂ１に向けて空乏層を
広げることが可能となる。これにより、スーパージャン
クション構造部１３のうち、電極部１３ｂ１が配置され
ている側（つまり、スーパージャンクション構造部１３
の表面近傍）の電界集中を緩和できるので、縦型ＭＯＳ
電界効果トランジスタ１の耐圧向上が可能となる。Next, main effects of the first embodiment will be described. The electrode section 31 is provided in the super junction structure section 13.
P-type silicon single crystal region 15 (15) which is located at a distance from end 13b1 of
a). For this reason, the termination 13b1
In addition, the depletion layer can be expanded toward the terminal 13b1 on the side of the super junction structure portion 13 where the electrode portion 31 is disposed. Accordingly, the side of the super junction structure 13 where the electrode portion 13b1 is arranged (that is, the super junction structure 13
(In the vicinity of the surface) of the vertical MOS
The breakdown voltage of the field effect transistor 1 can be improved.
【００１８】第１実施形態には、以下の変形例がある。The first embodiment has the following modifications.
【００１９】（１）Ｎ+型ソース領域２１、Ｐ型シリコ
ン単結晶領域１９、Ｐ型シリコン単結晶領域１５（１５
ａ）は、共通の電極部３１であるが、Ｐ型シリコン単結
晶領域１５（１５ａ）の電極部と、Ｎ+型ソース領域２
１、Ｐ型シリコン単結晶領域１９の電極部とを分離して
もよい。(1) N + type source region 21, P type silicon single crystal region 19, P type silicon single crystal region 15 (15
a) is a common electrode portion 31, which includes the electrode portion of the P-type silicon single crystal region 15 (15 a) and the N + -type source region 2.
1. The electrode portion of the P-type silicon single crystal region 19 may be separated.
【００２０】（２）周辺部１３ｂを構成するＰ型シリコ
ン単結晶領域１５のうち、電極部３１と接続するＰ型シ
リコン単結晶領域１５（１５ａ）は、終端１３ｂ１と最
も離れた位置にある。しかしながら、電極部３１と接続
するＰ型シリコン単結晶領域１５（１５ａ）は、終端１
３ｂ１と離れた位置にあれば、他の位置でもよい。(2) Among the P-type silicon single crystal regions 15 constituting the peripheral portion 13b, the P-type silicon single crystal region 15 (15a) connected to the electrode portion 31 is located farthest from the terminal end 13b1. However, the P-type silicon single crystal region 15 (15a) connected to the electrode portion 31 has the terminal 1
Any other position may be used as long as the position is distant from 3b1.
【００２１】（３）トレンチゲート電極２５をゲート電
極としてるが、平面ゲート電極をゲート電極としてもよ
い。(3) Although the trench gate electrode 25 is used as the gate electrode, a planar gate electrode may be used as the gate electrode.
【００２２】（４）縦型ＭＯＳ電界効果トランジスタ１
に本発明を適用しているが、他の縦型半導体装置に本発
明を適用することもできる。(4) Vertical MOS field effect transistor 1
Although the present invention is applied to the above, the present invention can also be applied to other vertical semiconductor devices.
【００２３】（５）縦型ＭＯＳ電界効果トランジスタ１
は、Ｎ型であるが、Ｐ型でもよい。(5) Vertical MOS field effect transistor 1
Is N-type, but may be P-type.
【００２４】なお、これらの変形例は、次に説明する第
２、３実施形態にも当てはまる。Note that these modifications also apply to the second and third embodiments described below.
【００２５】［第２実施形態］図２は、本発明の第２実
施形態の断面図である。第２実施形態は、縦型ＭＯＳ電
界効果トランジスタ３に本発明を適用している。図１に
示す縦型ＭＯＳ電界効果トランジスタ１と同等の機能を
有する部分には、同一符号を付している。縦型ＭＯＳ電
界効果トランジスタ３が縦型ＭＯＳ電界効果トランジス
タ１と相違する部分を説明し、同じ部分については説明
を省略する。[Second Embodiment] FIG. 2 is a sectional view of a second embodiment of the present invention. In the second embodiment, the present invention is applied to the vertical MOS field effect transistor 3. Portions having functions equivalent to those of the vertical MOS field-effect transistor 1 shown in FIG. 1 are denoted by the same reference numerals. The portions of the vertical MOS field effect transistor 3 that differ from the vertical MOS field effect transistor 1 will be described, and descriptions of the same portions will be omitted.
【００２６】周辺部１３ｂ上には、Ｐ型シリコン単結晶
領域４１が形成されている。Ｐ型シリコン単結晶領域４
１は、周辺部１３ｂを構成するＰ型シリコン単結晶領域
１５と接続されている。Ｐ型シリコン単結晶領域４１の
Ｐ型不純物濃度は、Ｐ型シリコン単結晶領域１５のそれ
と同じでもよいし、異なっていてもよい。電極部３１
は、コンタクトホール３５を介してＰ型シリコン単結晶
領域４１と接続されている。第２実施形態によれば、後
のシミュレーションで説明するように、第１実施形態よ
りも高耐圧化が可能となる。On the peripheral portion 13b, a P-type silicon single crystal region 41 is formed. P-type silicon single crystal region 4
Numeral 1 is connected to a P-type silicon single crystal region 15 forming the peripheral portion 13b. The P-type impurity concentration of the P-type silicon single crystal region 41 may be the same as or different from that of the P-type silicon single crystal region 15. Electrode part 31
Are connected to a P-type silicon single crystal region 41 via a contact hole 35. According to the second embodiment, a higher breakdown voltage can be achieved than in the first embodiment, as described in a later simulation.
【００２７】［第３実施形態］図３は、本発明の第３実
施形態の断面図である。第３実施形態は、縦型ＭＯＳ電
界効果トランジスタ５に本発明を適用している。縦型Ｍ
ＯＳ電界効果トランジスタ１、３と同等の機能を有する
部分には、同一符号を付している。縦型ＭＯＳ電界効果
トランジスタ５が縦型ＭＯＳ電界効果トランジスタ１、
３と相違する部分を説明し、同じ部分については説明を
省略する。[Third Embodiment] FIG. 3 is a sectional view of a third embodiment of the present invention. In the third embodiment, the present invention is applied to a vertical MOS field-effect transistor 5. Vertical M
Portions having functions equivalent to those of the OS field effect transistors 1 and 3 are denoted by the same reference numerals. The vertical MOS field-effect transistor 5 is the vertical MOS field-effect transistor 1,
3 will be described, and description of the same portions will be omitted.
【００２８】周辺部１３ｂを構成するＰ型シリコン単結
晶領域１５は、それぞれ、Ｎ型シリコン単結晶領域４３
により、上下に分離されている。Ｎ型シリコン単結晶領
域４３を介して、Ｎ型シリコン単結晶領域１７同士が電
気的に導通される。Ｎ型シリコン単結晶領域４３のＮ型
不純物濃度は、Ｎ型シリコン単結晶領域１７のそれと同
じでもよいし、異なっていてもよい。Ｎ型シリコン単結
晶領域４３の形成方法は、例えば、以下のとおりであ
る。スーパージャンクション構造部１３は、エピタキシ
ャル成長層形成、エピタキシャル成長層にＮ型、Ｐ型イ
オンを選択的に注入、を繰り返すことにより形成され
る。Ｎ型シリコン単結晶領域４３は、これらの繰り返し
工程の中で形成される。つまり、Ｎ型シリコン単結晶領
域４３が形成されるべきエピタキシャル成長層形成工程
後、周辺部１３ｂの全面にＮ型不純物をイオン注入する
と、Ｎ型シリコン単結晶領域１７の一部と共に、Ｎ型シ
リコン単結晶領域４３が形成される。The P-type silicon single-crystal regions 15 forming the peripheral portion 13b are respectively N-type silicon single-crystal regions 43.
Are separated vertically. The N-type silicon single crystal regions 17 are electrically connected to each other via the N-type silicon single crystal region 43. The N-type impurity concentration of the N-type silicon single crystal region 43 may be the same as or different from that of the N-type silicon single crystal region 17. The method for forming the N-type silicon single crystal region 43 is, for example, as follows. The super junction structure 13 is formed by repeatedly forming an epitaxial growth layer and selectively implanting N-type and P-type ions into the epitaxial growth layer. N-type silicon single crystal region 43 is formed during these repetitive steps. That is, after the step of forming an epitaxial growth layer in which the N-type silicon single crystal region 43 is to be formed, when N-type impurities are ion-implanted into the entire surface of the peripheral portion 13b, the N-type silicon Crystal region 43 is formed.
【００２９】第３実施形態によれば、縦型ＭＯＳ電界効
果トランジスタ５のＯＦＦ時に、空乏層は、垂直電界と
水平電界とに分割される。特に、水平電界により、低電
圧時のリーク電流低減に効果がある。また、シミュレー
ションによれば、電圧５０Ｖ以下において通常よりもリ
ーク電流を約１／３に低減できた。According to the third embodiment, when the vertical MOS field effect transistor 5 is turned off, the depletion layer is divided into a vertical electric field and a horizontal electric field. In particular, the horizontal electric field is effective in reducing the leak current at a low voltage. Further, according to the simulation, the leakage current was reduced to about 1/3 of that at a voltage of 50 V or less than usual.
【００３０】［シミュレーション］図４〜図１２のそれ
ぞれ（Ａ）に示すスーパージャンクション構造部の周辺
部についてシミュレーションを行った。図４の（Ａ）に
示す周辺部（例１）は、第１実施形態の縦型ＭＯＳ電界
効果トランジスタ１と対応する。図５の（Ａ）に示す周
辺部（例２）、図６の（Ａ）に示す周辺部（例３）、図
７の（Ａ）に示す周辺部（例４）は、第２実施形態の縦
型ＭＯＳ電界効果トランジスタ３と対応する。図８の
（Ａ）に示す周辺部（例５）、図９の（Ａ）に示す周辺
部（例６）、図１０の（Ａ）に示す周辺部（例７）は、
第３実施形態の縦型ＭＯＳ電界効果トランジスタ５と対
応する。図１１の（Ａ）に示す周辺部（例８）は、比較
例である。図１２の（Ａ）に示す周辺部（例９）は、従
来例である。[Simulation] A simulation was performed on the periphery of the super junction structure shown in FIG. 4A to FIG. The peripheral portion (Example 1) shown in FIG. 4A corresponds to the vertical MOS field-effect transistor 1 of the first embodiment. A peripheral portion (Example 2) shown in FIG. 5A, a peripheral portion (Example 3) shown in FIG. 6A, and a peripheral portion (Example 4) shown in FIG. Corresponding to the vertical MOS field-effect transistor 3. The peripheral portion (Example 5) shown in FIG. 8A, the peripheral portion (Example 6) shown in FIG. 9A, and the peripheral portion (Example 7) shown in FIG.
This corresponds to the vertical MOS field effect transistor 5 of the third embodiment. A peripheral portion (Example 8) shown in FIG. 11A is a comparative example. The peripheral portion (Example 9) shown in FIG. 12A is a conventional example.
【００３１】｛周辺部の条件｝ （例１の周辺部の条件） Ｎ+型ドレイン領域１１のｎ型不純物濃度：１×１０19
／ｃｍ3 Ｎ型シリコン単結晶領域１２、１７のｎ型不純物濃度：
１×１０16／ｃｍ3 Ｐ型シリコン単結晶領域１５、１５（１５ａ）のｐ型不
純物濃度：１×１０ 16／ｃｍ3 Ｎ型シリコン単結晶領域１７の幅：０．５μｍ Ｎ型シリコン単結晶領域１７の深さ：１５μｍ Ｐ型シリコン単結晶領域１５、１５（１５ａ）の幅：
０．５μｍ Ｐ型シリコン単結晶領域１５、１５（１５ａ）の深さ：
１５μｍ （例２〜例４の周辺部の条件） Ｎ+型ドレイン領域１１のｎ型不純物濃度：１×１０19
／ｃｍ3 Ｎ型シリコン単結晶領域１２、１７のｎ型不純物濃度：
１×１０16／ｃｍ3 Ｐ型シリコン単結晶領域１５、１５（１５ａ）のｐ型不
純物濃度：１×１０ 16／ｃｍ3 Ｎ型シリコン単結晶領域１７の幅：０．５μｍ Ｎ型シリコン単結晶領域１７の深さ：１４．５μｍ、１
５μｍ Ｐ型シリコン単結晶領域１５、１５（１５ａ）の幅：
０．５μｍ Ｐ型シリコン単結晶領域１５、１５（１５ａ）の深さ：
１４．５μｍ、１５μｍ Ｐ型シリコン単結晶領域４１の深さ：０．５μｍ 図５のＰ型シリコン単結晶領域４１の横方向の長さ：
５．０μｍ 図６のＰ型シリコン単結晶領域４１の横方向の長さ：１
５μｍ 図７のＰ型シリコン単結晶領域４１の横方向の長さ：２
５μｍ （例５〜例７の周辺部の条件） Ｎ+型ドレイン領域１１のｎ型不純物濃度：１×１０19
／ｃｍ3 Ｎ型シリコン単結晶領域１２、１７のｎ型不純物濃度：
１×１０16／ｃｍ3 Ｐ型シリコン単結晶領域１５のｐ型不純物濃度：１×１
０16／ｃｍ3 Ｎ型シリコン単結晶領域１７の幅：１．０μｍ Ｎ型シリコン単結晶領域１７の深さ：１４μｍ Ｐ型シリコン単結晶領域１５の幅：１．０μｍ Ｐ型シリコン単結晶領域１５の深さ：１４μｍ Ｐ型シリコン単結晶領域４１の深さ：１．０μｍ 図８〜図１０のＰ型シリコン単結晶領域４１の横方向の
長さ：２５μｍ 図８〜図１０のＮ型シリコン単結晶領域４３の幅：１．
０μｍ 図８〜図１０のＮ型シリコン単結晶領域４３の深さ：
１．０μｍ （例８の周辺部の条件） Ｎ+型ドレイン領域１１のｎ型不純物濃度：１×１０19
／ｃｍ3 Ｎ型シリコン単結晶領域１２、１７のｎ型不純物濃度：
１×１０16／ｃｍ3 Ｐ型シリコン単結晶領域１５のｐ型不純物濃度：１×１
０16／ｃｍ3 Ｎ型シリコン単結晶領域１７の幅：０．５μｍ Ｎ型シリコン単結晶領域１７の深さ：１４．５μｍ Ｐ型シリコン単結晶領域１５の幅：０．５μｍ Ｐ型シリコン単結晶領域１５の深さ：１４．５μｍ Ｐ型シリコン単結晶領域４１の深さ：０．５μｍ Ｐ型シリコン単結晶領域４１の横方向の長さ：２５μｍ （例９の周辺部の条件） Ｎ+型ドレイン領域１１のｎ型不純物濃度：１×１０19
／ｃｍ3 Ｎ型シリコン単結晶領域１２、１７のｎ型不純物濃度：
１×１０16／ｃｍ3 Ｐ型シリコン単結晶領域１５のｐ型不純物濃度：１×１
０16／ｃｍ3 Ｎ型シリコン単結晶領域１７の幅：０．５μｍ Ｎ型シリコン単結晶領域１７の深さ：１４．５μｍ Ｐ型シリコン単結晶領域１５の幅：０．５μｍ Ｐ型シリコン単結晶領域１５の深さ：１４．５μｍ ｛耐圧特性｝上記スーパージャンクション構造部の周辺
部の耐圧特性（ドレイン電圧Ｖdとドレイン電流Ｉd）の
シミュレーションをした。その結果を図４〜図１２の
（Ｂ）のグラフに示す。なお、条件は、次のとおりであ
る。{Conditions of Peripheral Part} (Conditions of Peripheral Part of Example 1) N+-Type impurity concentration of the drain region 11 of 1 × 1019
/ CmThree N-type impurity concentration of N-type silicon single crystal regions 12 and 17:
1 × 1016/ CmThree P-type silicon single crystal regions 15, 15 (15a)
Pure substance concentration: 1 × 10 16/ CmThree Width of N-type silicon single crystal region 17: 0.5 μm Depth of N-type silicon single crystal region 17: 15 μm Width of P-type silicon single crystal regions 15, 15 (15a):
0.5 μm Depth of P-type silicon single crystal regions 15, 15 (15a):
15 μm (Conditions of peripheral part of Examples 2 to 4) N+-Type impurity concentration of the drain region 11 of 1 × 1019
/ CmThree N-type impurity concentration of N-type silicon single crystal regions 12 and 17:
1 × 1016/ CmThree P-type silicon single crystal regions 15, 15 (15a)
Pure substance concentration: 1 × 10 16/ CmThree Width of N-type silicon single crystal region 17: 0.5 μm Depth of N-type silicon single crystal region 17: 14.5 μm, 1
5 μm width of P-type silicon single crystal regions 15, 15 (15a):
0.5 μm Depth of P-type silicon single crystal regions 15, 15 (15a):
14.5 μm, 15 μm Depth of P-type silicon single crystal region 41: 0.5 μm Lateral length of P-type silicon single crystal region 41 in FIG. 5:
5.0 μm Lateral length of P-type silicon single crystal region 41 in FIG. 6: 1
5 μm Length of P-type silicon single crystal region 41 in FIG. 7 in the horizontal direction: 2
5 μm (Conditions of peripheral parts of Examples 5 to 7) N+-Type impurity concentration of the drain region 11 of 1 × 1019
/ CmThree N-type impurity concentration of N-type silicon single crystal regions 12 and 17:
1 × 1016/ CmThree P-type impurity concentration of P-type silicon single crystal region 15: 1 × 1
016/ CmThree Width of N-type silicon single crystal region 17: 1.0 μm Depth of N-type silicon single crystal region 17: 14 μm Width of P-type silicon single crystal region 15: 1.0 μm Depth of P-type silicon single crystal region 15: 14 μm Depth of P-type silicon single crystal region 41: 1.0 μm In the lateral direction of P-type silicon single crystal region 41 in FIGS.
Length: 25 μm Width of N-type silicon single crystal region 43 in FIGS.
0 μm Depth of N-type silicon single crystal region 43 in FIGS. 8 to 10:
1.0 μm (Conditions of peripheral portion of Example 8) N+-Type impurity concentration of the drain region 11 of 1 × 1019
/ CmThree N-type impurity concentration of N-type silicon single crystal regions 12 and 17:
1 × 1016/ CmThree P-type impurity concentration of P-type silicon single crystal region 15: 1 × 1
016/ CmThree Width of N-type silicon single crystal region 17: 0.5 μm Depth of N-type silicon single crystal region 17: 14.5 μm Width of P-type silicon single crystal region 15: 0.5 μm Depth of P-type silicon single crystal region 15 : 14.5 μm Depth of P-type silicon single crystal region 41: 0.5 μm Horizontal length of P-type silicon single crystal region 41: 25 μm (Conditions of peripheral portion of Example 9) N+-Type impurity concentration of the drain region 11 of 1 × 1019
/ CmThree N-type impurity concentration of N-type silicon single crystal regions 12 and 17:
1 × 1016/ CmThree P-type impurity concentration of P-type silicon single crystal region 15: 1 × 1
016/ CmThree Width of N-type silicon single crystal region 17: 0.5 μm Depth of N-type silicon single crystal region 17: 14.5 μm Width of P-type silicon single crystal region 15: 0.5 μm Depth of P-type silicon single crystal region 15 : 14.5 μm ｛Withstand voltage characteristics 周 辺 Around the super junction structure
Withstand voltage characteristics (drain voltage VdAnd drain current Id)of
I did a simulation. The results are shown in FIGS.
It is shown in the graph of (B). The conditions are as follows:
You.
【００３２】ゲート電圧：０Ｖ ドレイン電圧：０〜３００Ｖの範囲において、０．５Ｖ
づつ電圧を上昇 ソース電圧：０Ｖ ボディ電圧：０Ｖ 図４の（Ｂ）は、例１のスーパージャンクション構造部
の周辺部の耐圧特性を示している。図４の（Ｂ）のグラ
フから分かるように、ドレイン電圧が１９５Ｖで、この
構造は、絶縁破壊している。よって、上記条件におい
て、この周辺部の耐圧は、１９５Ｖであることが分か
る。なお、図４の（Ａ）の４５は等電位線であり、例１
のスーパージャンクション構造部の周辺部を含む縦型Ｍ
ＯＳ電界効果トランジスタのＯＦＦ時において、ドレイ
ン電圧が１９０Ｖにおける電位分布を示している。等電
位は、１０Ｖステップで分布している。図４の（Ａ）か
ら分かるように、スーパージャンクション構造部の周辺
部の全体に、等電位線４５が分布している。これは、ス
ーパージャンクション構造部の周辺部が完全空乏化して
いることを意味している。このように、ドレイン電圧が
１９０Ｖにおいて、スーパージャンクション構造部の周
辺部には空乏層があるので、絶縁破壊していないことが
分かる。Gate voltage: 0 V Drain voltage: 0.5 V in the range of 0 to 300 V
Source voltage: 0 V Body voltage: 0 V FIG. 4B shows withstand voltage characteristics of the peripheral portion of the super junction structure of Example 1. As can be seen from the graph of FIG. 4B, when the drain voltage is 195 V, the structure has dielectric breakdown. Therefore, it is understood that the breakdown voltage of this peripheral portion is 195 V under the above conditions. Note that 45 in FIG. 4A is an equipotential line, and Example 1
Vertical M including the periphery of the super junction structure
The potential distribution at a drain voltage of 190 V when the OS field-effect transistor is off is shown. Equipotentials are distributed in 10 V steps. As can be seen from FIG. 4A, equipotential lines 45 are distributed over the entire periphery of the super junction structure. This means that the periphery of the super junction structure is completely depleted. As described above, when the drain voltage is 190 V, the dielectric breakdown does not occur because the depletion layer exists around the super junction structure.
【００３３】図５の（Ｂ）は、例２のスーパージャンク
ション構造部の周辺部の耐圧特性を示している。この周
辺部の耐圧は、２４０Ｖであることが分かる。なお、図
５の（Ａ）の４５は等電位線であり、例２のスーパージ
ャンクション構造部の周辺部を含む縦型ＭＯＳ電界効果
トランジスタのＯＦＦ時において、ドレイン電圧が２３
０Ｖにおける電位分布を示している。このように、ドレ
イン電圧が２３０Ｖにおいて、スーパージャンクション
構造部の周辺部には空乏層があるので、絶縁破壊してい
ないことが分かる。FIG. 5B shows the breakdown voltage characteristics of the peripheral portion of the super junction structure of Example 2. It can be seen that the withstand voltage of this peripheral portion is 240V. In FIG. 5A, reference numeral 45 denotes an equipotential line, and when the vertical MOS field effect transistor including the peripheral portion of the super junction structure in Example 2 is turned off, the drain voltage is 23.
The potential distribution at 0 V is shown. As described above, when the drain voltage is 230 V, since the depletion layer exists in the peripheral portion of the super junction structure, it can be seen that the dielectric breakdown has not occurred.
【００３４】図６の（Ｂ）は、例３のスーパージャンク
ション構造部の周辺部の耐圧特性を示している。この周
辺部の耐圧は、２７５Ｖであることが分かる。なお、図
６の（Ａ）の４５は等電位線であり、例３の（Ａ）に示
すスーパージャンクション構造部の周辺部を含む縦型Ｍ
ＯＳ電界効果トランジスタのＯＦＦ時において、ドレイ
ン電圧が２７０Ｖにおける電位分布を示している。この
ように、ドレイン電圧が２７０Ｖにおいて、スーパージ
ャンクション構造部の周辺部には空乏層があるので、絶
縁破壊していないことが分かる。FIG. 6B shows the breakdown voltage characteristics of the peripheral portion of the super junction structure of Example 3. It can be seen that the withstand voltage of this peripheral portion is 275V. Note that 45 in FIG. 6A is an equipotential line, and the vertical M including the peripheral portion of the super junction structure shown in FIG.
The potential distribution at a drain voltage of 270 V when the OS field-effect transistor is off is shown. As described above, when the drain voltage is 270 V, there is a depletion layer in the peripheral portion of the super junction structure portion, and thus it can be seen that the dielectric breakdown has not occurred.
【００３５】図７の（Ｂ）は、例４のスーパージャンク
ション構造部の周辺部の耐圧特性を示している。この周
辺部の耐圧は、２７５Ｖであることが分かる。なお、図
７の（Ａ）の４５は等電位線であり、例４のスーパージ
ャンクション構造部の周辺部を含む縦型ＭＯＳ電界効果
トランジスタのＯＦＦ時において、ドレイン電圧が２７
０Ｖにおける電位分布を示している。このように、ドレ
イン電圧が２７０Ｖにおいて、スーパージャンクション
構造部の周辺部には空乏層があるので、絶縁破壊してい
ないことが分かる。FIG. 7B shows the breakdown voltage characteristics of the peripheral portion of the super junction structure of Example 4. It can be seen that the withstand voltage of this peripheral portion is 275V. Note that 45 in FIG. 7A is an equipotential line, and when the vertical MOS field-effect transistor including the peripheral portion of the super junction structure in Example 4 is turned off, the drain voltage is 27.
The potential distribution at 0 V is shown. As described above, when the drain voltage is 270 V, there is a depletion layer in the peripheral portion of the super junction structure portion, and thus it can be seen that the dielectric breakdown has not occurred.
【００３６】図８の（Ｂ）は、例５のスーパージャンク
ション構造部の周辺部の耐圧特性を示している。この周
辺部の耐圧は、２５０Ｖであることが分かる。なお、図
８の（Ａ）の４５は等電位線であり、例５のスーパージ
ャンクション構造部の周辺部を含む縦型ＭＯＳ電界効果
トランジスタのＯＦＦ時において、ドレイン電圧が２４
０Ｖにおける電位分布を示している。このように、ドレ
イン電圧が２４０Ｖにおいて、スーパージャンクション
構造部の周辺部には空乏層があるので、絶縁破壊してい
ないことが分かる。FIG. 8B shows the breakdown voltage characteristics of the peripheral portion of the super junction structure of Example 5. It can be seen that the withstand voltage of this peripheral portion is 250V. Note that 45 in FIG. 8A is an equipotential line, and when the vertical MOS field-effect transistor including the peripheral portion of the super junction structure in Example 5 is turned off, the drain voltage becomes 24.
The potential distribution at 0 V is shown. As described above, when the drain voltage is 240 V, there is a depletion layer in the peripheral portion of the super junction structure portion, and thus it can be seen that there is no dielectric breakdown.
【００３７】図９の（Ｂ）は、例６のスーパージャンク
ション構造部の周辺部の耐圧特性を示している。この周
辺部の耐圧は、２４５Ｖであることが分かる。なお、図
９の（Ａ）の４５は等電位線であり、例６のスーパージ
ャンクション構造部の周辺部を含む縦型ＭＯＳ電界効果
トランジスタのＯＦＦ時において、ドレイン電圧が２４
０Ｖにおける電位分布を示している。このように、ドレ
イン電圧が２４０Ｖにおいて、スーパージャンクション
構造部の周辺部には空乏層があるので、絶縁破壊してい
ないことが分かる。FIG. 9B shows the breakdown voltage characteristics of the peripheral portion of the super junction structure of Example 6. It can be seen that the withstand voltage of this peripheral portion is 245V. Note that 45 in FIG. 9A is an equipotential line, and when the vertical MOS field effect transistor including the peripheral portion of the super junction structure in Example 6 is turned off, the drain voltage becomes 24.
The potential distribution at 0 V is shown. As described above, when the drain voltage is 240 V, there is a depletion layer in the peripheral portion of the super junction structure portion, and thus it can be seen that there is no dielectric breakdown.
【００３８】図１０の（Ｂ）は、例７のスーパージャン
クション構造部の周辺部の耐圧特性を示している。この
周辺部の耐圧は、２４５Ｖであることが分かる。なお、
図１０の（Ａ）の４５は等電位線であり、例７のスーパ
ージャンクション構造部の周辺部を含む縦型ＭＯＳ電界
効果トランジスタのＯＦＦ時において、ドレイン電圧が
２４０Ｖにおける電位分布を示している。このように、
ドレイン電圧が２４０Ｖにおいて、スーパージャンクシ
ョン構造部の周辺部には空乏層があるので、絶縁破壊し
ていないことが分かる。FIG. 10B shows the breakdown voltage characteristics of the peripheral portion of the super junction structure of Example 7. It can be seen that the withstand voltage of this peripheral portion is 245V. In addition,
Reference numeral 45 in FIG. 10A indicates an equipotential line, and shows a potential distribution at a drain voltage of 240 V when the vertical MOS field effect transistor including the periphery of the super junction structure in Example 7 is OFF. in this way,
At a drain voltage of 240 V, there is a depletion layer in the periphery of the super junction structure, and it can be seen that there is no dielectric breakdown.
【００３９】図１１の（Ｂ）は、例８のスーパージャン
クション構造部の周辺部の耐圧特性を示している。この
周辺部の耐圧は、４０Ｖであることが分かる。なお、図
１１の（Ａ）の４５は等電位線であり、例８のスーパー
ジャンクション構造部の周辺部を含む縦型ＭＯＳ電界効
果トランジスタのＯＦＦ時において、ドレイン電圧が約
３５Ｖにおける電位分布を示している。このように、ド
レイン電圧が約３５Ｖにおいて、スーパージャンクショ
ン構造部の周辺部には空乏層があるので、絶縁破壊して
いないことが分かる。但し、例８では、完全空乏化して
いなので、耐圧が低くなる。FIG. 11B shows the breakdown voltage characteristics of the peripheral portion of the super junction structure of Example 8. It can be seen that the withstand voltage of this peripheral portion is 40V. Note that 45 in FIG. 11A is an equipotential line, and shows a potential distribution at a drain voltage of about 35 V when the vertical MOS field-effect transistor including the periphery of the super junction structure in Example 8 is OFF. ing. As described above, when the drain voltage is about 35 V, since the depletion layer exists in the peripheral portion of the super junction structure portion, it can be seen that the dielectric breakdown has not occurred. However, in Example 8, the withstand voltage is low because it is completely depleted.
【００４０】図１２の（Ｂ）は、例９のスーパージャン
クション構造部の周辺部の耐圧特性を示している。この
周辺部の耐圧は、１００Ｖであることが分かる。なお、
図１２の（Ａ）の４５は等電位線であり、例９のスーパ
ージャンクション構造部の周辺部を含む縦型ＭＯＳ電界
効果トランジスタのＯＦＦ時において、ドレイン電圧が
約９５Ｖにおける電位分布を示している。このように、
ドレイン電圧が約９５Ｖにおいて、スーパージャンクシ
ョン構造部の周辺部には空乏層があるので、絶縁破壊し
ていないことが分かる。FIG. 12B shows the breakdown voltage characteristics of the peripheral portion of the super junction structure of Example 9. It can be seen that the withstand voltage of this peripheral portion is 100V. In addition,
Numeral 45 in FIG. 12A indicates an equipotential line, and shows a potential distribution at a drain voltage of about 95 V when the vertical MOS field effect transistor including the periphery of the super junction structure in Example 9 is OFF. . in this way,
At a drain voltage of about 95 V, there is a depletion layer in the periphery of the super junction structure, and it can be seen that dielectric breakdown has not occurred.
【００４１】これらの耐圧をグラフに表すと図１３のよ
うになる。横軸は、Ｐ型シリコン単結晶領域４１の横方
向の長さを示している。但し、例１（図４）は、Ｐ型シ
リコン単結晶領域４１を有しないが、表面部にＰ型シリ
コン単結晶領域１５（１５ａ）があるので、Ｐ型シリコ
ン単結晶領域１５（１５ａ）の幅をＰ型シリコン単結晶
領域４１の幅と見なしている。FIG. 13 is a graph showing these breakdown voltages. The horizontal axis indicates the length of the P-type silicon single crystal region 41 in the horizontal direction. However, Example 1 (FIG. 4) does not have the P-type silicon single-crystal region 41, but has the P-type silicon single-crystal region 15 (15a) on the surface, so that the P-type silicon single-crystal region 15 (15a) The width is regarded as the width of the P-type silicon single crystal region 41.
【００４２】例１０は、従来の通常の場合（片面階段接
合）の耐圧を示している。片面階段接合の耐圧は、基板
のうち、空乏層を広げる側の領域の不純物濃度で決定さ
れる。今回の基板のｎ型不純物濃度は、１×１０16／ｃ
ｍ3であるから、Physics ofSemiconductor Devices,S.
M.Szeの第１０５頁によれば、理論上の最大耐圧は約６
０Ｖ程度である。実際の耐圧は、不純物濃度分布、すな
わち、拡散層の曲率形状やエピ厚みに依存して耐圧が６
０Ｖ以下（約４０Ｖ）となる。Example 10 shows the withstand voltage in the conventional ordinary case (single-sided step junction). The withstand voltage of the single-sided step junction is determined by the impurity concentration in the region of the substrate on which the depletion layer is expanded. The n-type impurity concentration of the substrate this time is 1 × 10 16 / c
because it is m 3, Physics ofSemiconductor Devices, S .
According to page 105 of M. Sze, the theoretical maximum withstand voltage is about 6
It is about 0V. The actual breakdown voltage is 6 depending on the impurity concentration distribution, that is, the curvature shape and the epi thickness of the diffusion layer.
0 V or less (about 40 V).
【００４３】図１３を見れば分かるように、例１〜例７
（本発明）によれば、例８（比較例）、例９（従来
例）、例１０（従来の片面階段接合の例）と比べて、優
れた耐圧になる。また、例２〜例７のように、Ｐ型シリ
コン単結晶領域４１を設ければ、例１のようにＰ型シリ
コン単結晶領域４１を設けない場合に比べて、耐圧を高
くすることができる。As can be seen from FIG.
According to (the present invention), the withstand voltage is excellent as compared with Example 8 (Comparative Example), Example 9 (Conventional Example), and Example 10 (Example of the conventional single-sided stepwise junction). Further, when the P-type silicon single crystal region 41 is provided as in Examples 2 to 7, the breakdown voltage can be increased as compared with the case where the P-type silicon single crystal region 41 is not provided as in Example 1. .
【図１】本発明の第１実施形態の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図２】本発明の第２実施形態の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.
【図３】本発明の第３実施形態の断面図である。FIG. 3 is a sectional view of a third embodiment of the present invention.
【図４】本実施形態に係るスーパージャンクション構造
部の周辺部のシミュレーションの結果を示す図である。FIG. 4 is a diagram showing a simulation result of a peripheral portion of a super junction structure according to the embodiment.
【図５】本実施形態に係るスーパージャンクション構造
部の周辺部のシミュレーションの結果を示す図である。FIG. 5 is a diagram showing a result of a simulation of a peripheral portion of a super junction structure according to the embodiment.
【図６】本実施形態に係るスーパージャンクション構造
部の周辺部のシミュレーションの結果を示す図である。FIG. 6 is a diagram showing a result of a simulation of a peripheral portion of a super junction structure according to the embodiment.
【図７】本実施形態に係るスーパージャンクション構造
部の周辺部のシミュレーションの結果を示す図である。FIG. 7 is a diagram showing a simulation result of a peripheral portion of a super junction structure according to the embodiment.
【図８】本実施形態に係るスーパージャンクション構造
部の周辺部のシミュレーションの結果を示す図である。FIG. 8 is a diagram showing a result of a simulation of a peripheral portion of a super junction structure according to the embodiment.
【図９】本実施形態に係るスーパージャンクション構造
部の周辺部のシミュレーションの結果を示す図である。FIG. 9 is a diagram showing a result of a simulation of a peripheral portion of a super junction structure according to the embodiment.
【図１０】本実施形態に係るスーパージャンクション構
造部の周辺部のシミュレーションの結果を示す図であ
る。FIG. 10 is a diagram showing a result of a simulation of a peripheral portion of a super junction structure according to the embodiment.
【図１１】比較例に係るスーパージャンクション構造部
の周辺部のシミュレーションの結果を示す図である。FIG. 11 is a diagram illustrating a result of a simulation of a peripheral portion of a super junction structure according to a comparative example.
【図１２】従来例に係るスーパージャンクション構造部
の周辺部のシミュレーションの結果を示す図である。FIG. 12 is a diagram showing a result of a simulation of a peripheral portion of a super junction structure according to a conventional example.
【図１３】各スーパージャンクション構造部の周辺部に
おける耐圧を示すグラフである。FIG. 13 is a graph showing a breakdown voltage in a peripheral portion of each super junction structure.
【符号の説明】 １、３、５ 縦型ＭＯＳ電界効果トランジスタ １１ Ｎ+型ドレイン領域 １２ Ｎ型シリコン単結晶領域 １３ スーパージャンクション構造部 １３ａ 形成部 １３ｂ 周辺部 １３ｂ１ 終端 １４ 電極部 １５（１５ａ） Ｐ-型シリコン単結晶領域 １７ Ｎ型シリコン単結晶領域 １９、１９ａ Ｐ型シリコン単結晶領域 ２１ Ｎ+型ソース領域 ２３ トレンチ ２５ トレンチゲート電極 ２７ ゲート絶縁膜 ２９ 絶縁膜 ３１ 電極部 ３５ コンタクトホール ３７ コンタクトホール ３９ セル ４１ Ｐ型シリコン単結晶領域 ４３ Ｎ型シリコン単結晶領域 ４５ 等電位線[Description of Signs] 1, 3, 5 Vertical MOS field-effect transistor 11 N + -type drain region 12 N-type silicon single crystal region 13 Super junction structure 13a Forming part 13b Peripheral part 13b1 Termination 14 Electrode part 15 (15a) P - -type silicon single crystal region 17 N-type silicon single crystal region 19, 19a P-type silicon single crystal region 21 N + -type source region 23 trenches 25 the trench gate electrode 27 a gate insulating film 29 insulating film 31 electrode portion 35 contact hole 37 the contact hole 39 cell 41 P-type silicon single crystal region 43 N-type silicon single crystal region 45 Equipotential line
フロントページの続き (72)発明者 上杉 勉 愛知県愛知郡長久手町大字長湫字横道41番 地の１ 株式会社豊田中央研究所内 (72)発明者 戸倉 規仁 愛知県刈谷市昭和町１丁目１番地 株式会 社デンソー内Continuing from the front page (72) Inventor Tsutomu Uesugi 41-41, Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture Inside of Toyota Central Research Institute, Inc. (72) Inventor Norihito Tokura 1-1-1, Showa-cho, Kariya-shi, Aichi Stock Inside the company DENSO
Claims (3)
って、 第１導電型の半導体基板と、 電極部と、 前記半導体基板と前記電極部との間に位置し、第１導電
型の第１半導体領域と第２導電型の第２半導体領域と
が、前記半導体基板上で交互に並ぶ構造部と、 を備え、 前記半導体基板と前記第１半導体領域とは電気的に導通
され、 前記構造部は、前記縦型半導体素子の形成部と、前記形
成部の周辺に位置し、前記構造部の終端を含む周辺部
と、を含み、 前記電極部は、前記構造部の終端と距離を設けた位置に
あり、かつ、前記周辺部を構成する前記第２半導体領域
と電気的に導通されている、半導体装置。1. A semiconductor device comprising a vertical semiconductor element, comprising: a first conductivity type semiconductor substrate; an electrode portion; and a first conductivity type semiconductor substrate located between the semiconductor substrate and the electrode portion. A structure in which a first semiconductor region and a second conductivity type second semiconductor region are alternately arranged on the semiconductor substrate, wherein the semiconductor substrate and the first semiconductor region are electrically connected to each other; The structure portion includes a formation portion of the vertical semiconductor element, and a peripheral portion located around the formation portion and including an end of the structure portion. The electrode portion has a distance from the end of the structure portion. A semiconductor device which is located at the provided position and is electrically connected to the second semiconductor region forming the peripheral portion;
前記第２半導体領域および前記電極部と電気的に導通す
る、第２導電型の第３半導体領域を備える、半導体装
置。2. The second conductive type of the first conductive type according to claim 1, wherein the second conductive type is located between the electrode portion and the peripheral portion and is electrically connected to the second semiconductor region and the electrode portion in the peripheral portion. A semiconductor device comprising three semiconductor regions.
体領域同士を導通させる、第１導電型の第４半導体領域
を備える、半導体装置。3. The semiconductor device according to claim 1, further comprising: a first conductivity type fourth semiconductor region located inside the peripheral portion and electrically connecting the first semiconductor regions in the peripheral portion.
Priority Applications (3)
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| JP2000383440A JP3899231B2 (en) | 2000-12-18 | 2000-12-18 | Semiconductor device |
| US10/015,917 US6639260B2 (en) | 2000-12-18 | 2001-12-17 | Semiconductor device having a vertical semiconductor element |
| US10/634,819 US6982459B2 (en) | 2000-12-18 | 2003-08-06 | Semiconductor device having a vertical type semiconductor element |
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| JP2000383440A JP3899231B2 (en) | 2000-12-18 | 2000-12-18 | Semiconductor device |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20040026735A1 (en) | 2004-02-12 |
| JP3899231B2 (en) | 2007-03-28 |
| US6639260B2 (en) | 2003-10-28 |
| US6982459B2 (en) | 2006-01-03 |
| US20020074596A1 (en) | 2002-06-20 |
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