JP2008504697A - Power semiconductor device provided with a MOS gate having a source field electrode - Google Patents

Power semiconductor device provided with a MOS gate having a source field electrode Download PDF

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JP2008504697A
JP2008504697A JP2007518368A JP2007518368A JP2008504697A JP 2008504697 A JP2008504697 A JP 2008504697A JP 2007518368 A JP2007518368 A JP 2007518368A JP 2007518368 A JP2007518368 A JP 2007518368A JP 2008504697 A JP2008504697 A JP 2008504697A
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gate electrode
electrode
source
gate
source field
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エヌ ソール アンドリュー
チャオ ジアンジュン
エム キンザー ダニエル
ケント デイヴ
ターパー ナレシュ
ハーヴェイ ポール
ソディー リトゥ
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インターナショナル レクティファイアー コーポレイション
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Priority to PCT/US2005/022917 priority patent/WO2006004746A2/en
Publication of JP2008504697A publication Critical patent/JP2008504697A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/407Recessed field plates, e.g. trench field plates, buried field plates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41766Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Abstract

A power semiconductor device is easily manufactured.
A source field electrode (30) and at least one insulated gate electrode (24, 26) adjacent to each side surface of the source field electrode (30) are provided, and the insulated source field electrode (30) and the gate electrode are provided. Are a power semiconductor device arranged in a common trench (10) and a method for manufacturing this device.
[Selection] Figure 1

Description

  The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device provided with a MOS gate.

  Breakdown voltage and operating resistance (on-resistance, ie Rdson) are important characteristics of power semiconductors. The power semiconductor device Rdson and the breakdown voltage have an inverse relationship. That is, if one characteristic is improved, the other characteristic is adversely affected.

  To solve this problem, U.S. Pat.No. 5,998,833 describes an electrode embedded in the same trench as the gate electrode to combine common conducting regions and improve device break voltage under reverse voltage conditions. We have proposed a trench type power semiconductor with an arrangement. This can improve the efficiency of the common conductive region without adversely affecting the break voltage.

  The embedded electrode shown in said US Pat. No. 5,998,833 is connected to the source contact of a remote device, thereby limiting the switching speed of the device. In addition, the device shown in this US patent may require at least one additional masking step.

  US Pat. No. 6,649,975 and US Pat. No. 6,710,403 disclose power semiconductor devices that include trenches that are deeper than gate trenches to support field electrodes that are electrically connected to source contacts.

  The devices shown in U.S. Pat. Nos. 6,649,975 and 6,710,403 require an additional mask step to form a trench that accommodates the field electrode, thus increasing manufacturing costs. Furthermore, this extra trench increases the cell pitch, thus reducing the cell density, which is undesirable.

  A power semiconductor device provided with a MOS gate according to the invention has at least one gate electrode and a source field electrode arranged in the same trench, which source field electrode is used to increase the switching speed. Connected locally (ie, within each unit cell).

A device according to a preferred embodiment of the present invention is:
An active area including at least one active cell, the active cell including at least one source region, a source contact electrode connected to the source region, and a source field electrode electrically connected to the source contact; An insulating gate electrode adjacent to one side of the source field electrode and the base region, wherein the source field electrode is deeper than a depth of the insulating gate electrode and higher than a height of the insulating gate electrode. The source field electrode and the insulated gate electrode extend in a common trench.

  The device according to the invention has a low Rdson, a high breakdown voltage, a very low Qgd, and a very low Qgd / Qgs ratio.

  Other features and advantages of the present invention will become apparent from the following description of the invention with reference to the accompanying drawings.

  The power semiconductor device according to a preferred embodiment of the present invention shown in FIG. 1 is a trench type MOSFET, which includes a trench 10 provided in a semiconductor body 56 in its active area. . This trench extends from the top 14 of the semiconductor body 56 through the source region 16 and the base region 18 into the drift region 20.

  A device according to an embodiment of the present invention includes a first gate electrode 22 extending to the base region 18 adjacent to the sidewall of the trench 10 and a second gate extending to the base region 18 adjacent to the opposite sidewall of the trench 10. The electrode 24, the first gate insulating part 26 interposed between the base region 18 and the first gate electrode 22, and the second gate insulating part 28 interposed between the second gate electrode 24 and the base region 18. And a first portion disposed between the first gate electrode 20 and the second gate electrode 24, and a second field portion disposed below the first gate electrode 22 and the second gate electrode 24 30.

  The first gate electrode 22 and the second gate electrode 24 can be energized together, but are electrically connected to each other so as to be insulated from the source field electrode 38. More specifically, the first portion of the source field electrode 30 is insulated from the first gate electrode 22 and the second gate electrode 24 by the insulating body 32, respectively, and insulated from the drift region 20 by the bottom insulating body 34. The bottom insulating body 34 is preferably thicker than the first gate insulating part 26 and the second gate insulating part 28. The bottom insulating body 34 preferably extends below the first gate electrode 22 and the second gate electrode 24.

  The device further includes a source contact 36 electrically connected to the source region 16, a source field electrode 30, and a highly conductive contact region 38 provided in the base region 18. In order to insulate the gate electrodes 24, 26 from the source contact 36, a first insulating cap 30 is interposed between the source contact 36 and the first gate electrode 22, and between the source contact 36 and the second gate electrode 24. In addition, a second insulating cap cap 42 is interposed.

  Thus, the device according to the present invention comprises a source field electrically connected to two insulated gate electrodes and a source contact and disposed between the two gate electrodes and extending below these gate electrodes. Electrode.

  In the preferred embodiment of the present invention, the first portion of the source field electrode 30 extends outward from the trench 10 and above the surface 14 of the semiconductor body 56. Note that the caps 40, 42 may extend outwardly from the trench 10 of the semiconductor body 56 and on the surface 14.

  The semiconductor body 56 is preferably composed of a semiconductor substrate 58, for example, silicon epitaxially formed on a silicon substrate. The preferred embodiment further includes a drain contact 43, which is in ohmic contact with the substrate 58, thus permitting vertical conduction between the source contact 36 and the drain contact 43.

  As will be readily appreciated by those skilled in the art, source region 16 is of the same conductivity type as drift region 20 and substrate 58, eg, N type, but base region 18 and high conductivity type contact region 38 are separate. The conductive type, for example, P type. Further, in the preferred embodiment, the first gate electrode 22 and the second gate electrode 24 and the source field electrode 30 are made of conductive polysilicon, and the gate insulating portions 26 and 28, the insulating portion caps 40 and 42, the insulating body. 32 and bottom insulating body 34 are constructed of silicon dioxide.

  The features described above are also present in a single active cell among the devices in the active area of the device according to the invention. The device according to the present invention includes a plurality of active cells in the active area, not shown for the sake of brevity.

  A device according to a preferred embodiment of the present invention includes a termination structure disposed within a termination area surrounding the active area. The termination structure in the preferred embodiment includes a termination trench 44 and a field oxide 46 disposed within the termination trench 44, the field oxide being adjacent to at least the active area and the bottom of the termination trench 44. However, it is preferable that both side walls of the termination trench 44 and the bottom thereof are adjacent to each other.

  A termination field plate 47 is disposed adjacent to the field oxide film 44. The termination field plate 47 is preferably made of conductive polysilicon, and the termination field plate 47 is connected to the source contact 36.

  Also shown in FIG. 1 is a gate contact 48. This gate contact 48 is connected to a gate runner 50, which in turn is connected to the gate electrodes 22, 24. More specifically, the gate runner 50 is electrically connected to a second gate electrode disposed in the termination trench 44, and similarly, all the gate electrodes 22, 24 in the active area are electrically connected. Connected. The gate runner 50 is preferably made of conductive polysilicon and rests on a thick insulating body 52.

  In the preferred embodiment, source contact 36, drain contact 42, and gate contact 48 are constructed of a suitable metal, such as aluminum or aluminum silicon.

  Next, a method for manufacturing a device according to the present invention will be described with reference to FIGS.

Reference is first made to FIG. 2A. A pad oxide film 54 is grown on the semiconductor body 56. The semiconductor body 56 is preferably one conductivity type, such as N type epitaxial silicon, and is grown on the semiconductor substrate 58. On the other hand, the semiconductor substrate 58 is preferably a silicon substrate having the same conductivity type but a low resistivity (higher dopant concentration). Next, a layer 60 of silicon nitride (Si 3 0 4 ) (which is an oxidation suppressing material) is deposited on the pad oxide film 54.

Reference is now made to FIG. The Si 3 N 4 layer 60 and the pad oxide film 54 are patterned so as to form a trench mask on the semiconductor body 56, and the termination trench 44 and the trench 10 are formed in the semiconductor body 56 in an etching step. Although not shown, a plurality of trenches 10 are formed in the active area of the device during this step. Thereafter, a sacrificial oxide film is grown on the sidewalls and bottom of the termination trench 44 and the trench 10 and etched, and then a pad oxide film is grown on the sidewall and bottom of the termination trench 44 and the trench 10. The structure shown in 2C is obtained.

Reference is now made to FIG. 2D. A polysilicon film 62 is deposited on the structure shown in FIG. 2C. Thereafter, the polysilicon film 62 is oxidized to form a silicon dioxide film 64 (SiO 2 ) as shown in FIG. 2E. It should be noted that the oxide film 64 does not completely fill the trench 10 and the termination trench 44, leaving a space 65 in both trenches.

  Next, as shown in FIG. 2F, a conductive polysilicon body 66 is formed in each space 65. Depositing polysilicon, doping this polysilicon, and then etching the doped polysilicon to form or dope in place of body 66 (ie, doping while depositing polysilicon) Thus, the polysilicon main body 66 is formed. Thereafter, except for the oxide film 64, a bottom oxide film 45 and a field oxide film 46 are formed in the termination trench 44 as shown in FIG. 2G.

  Reference is now made to FIG. The exposed portion of the conductive polysilicon body 66 extending above the bottom oxide film 34 and the field oxide film 46 is oxidized to form the insulating body 32 on the termination field plate 47 and the source field electrode 34. During this oxidation step, the exposed portions of the sidewalls of trench 10 and termination trench 44 are also oxidized to form gate insulations 26,28.

  Next, the polysilicon for forming the gate electrodes 22, 24 and the gate runner 30 is deposited and rendered conductive by implanting the dopant after depositing or during deposition (ie during in-situ doping). .

  Thereafter, the deposited polysilicon is selectively removed, preferably using photolithography, to form gate electrodes 22, 24 and gate bus 50 as shown in FIG. 2I.

  Next, a low density oxide, for example, TOS or the like is deposited on the structure shown in FIG. Etch selectively to form openings for access.

  Next, as shown in FIG. 2J, the oxide film is removed from the top surface of the source field electrode 30 to expose the top portion of the source field electrode 30.

Next, the Si 3 N 4 film 60 is removed from the active area, a base region 88 is formed, and channel dopants are implanted and driven to form the drift region 20. Preferably, channel dopants are not implanted beyond the termination trench 44.

  Thereafter, a source mask is applied, the pad oxide film 54 is etched from the active area, the base region 18 is exposed, and a source dopant is implanted so as to form a source implanted region 48 as shown in FIG. 2L.

  Reference is now made to FIG. An oxidized spacer is formed adjacent to the insulating caps 40 and 42 and extending over the source implant region 48. Next, a part of the base region 18 is removed, and a recess 70 is formed therein. It should be noted that the top surface of the semiconductor body 56 becomes the top surface 14 of the source implant region 68, and the source field electrode 30 rises above the surface 14 as shown in FIG. 2M.

  Next, the source implantation in the source implantation region 48 is driven by a diffusion drive to form the source region 16. Thereafter, at the bottom of the recess 70, a dopant of the same conductivity type as the base region 18 is implanted and the dopant is activated to form a high conductivity type contact region 38, as shown in FIG. 2N.

  Finally, the top metal film is deposited and patterned to form the source contact 36 and the gate contact 48, and the bottom metal film is deposited to form the drain contact 43, as shown in FIG. Get devices related to.

  The preferred embodiment shown herein is a power MOSFET. However, other power devices, IGBTs, ACCUFETs, and the like can be devices according to the principles disclosed herein without departing from the spirit of the invention.

  Although the invention has been described with reference to specific embodiments of the invention, many variations and modifications other than those described above and other uses will be apparent to those skilled in the art. Accordingly, the present invention is not limited by the specific disclosures provided herein, but only by the claims.

RELATED APPLICATION This application is based on the right of US Provisional Patent Application No. 60 / 582,898, filed on June 24, 2005, entitled “Trench FET with Deep Source Poly Electrode and its Manufacturing Process”. The contents of this US provisional patent application are incorporated as reference examples.

It is a schematic sectional drawing of the semiconductor device concerning one Example of this invention. 1 schematically shows one of the intermediate structures obtained as a result of the method for manufacturing a device according to the invention. 1 schematically shows one of the intermediate structures obtained as a result of the method for manufacturing a device according to the invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention. 1 is a schematic diagram showing one of the intermediate structures obtained by the method for manufacturing a device according to the present invention.

Explanation of symbols

10 trench 14 top 16 source region 18 base region 20 drift region 22 first gate electrode 24 second gate electrode 26 first gate insulating portion 28 second gate insulating portion 30 source field electrode 32 insulating body 34 bottom insulating body 36 source contact 38 Source field electrode 40 First insulating cap 42 Second insulating cap 43 Drain contact 44 Termination trench 46 Field oxide film 47 Termination field plate 48 Gate contact 50 Gate runner 56 Semiconductor body 58 Substrate 60 Si3N4 layer 62 Polysilicon film 64 Oxide film 65 Space 66 Polysilicon body 68 Embedded area 70 Recess

Claims (20)

  1. A semiconductor body having a common conductive region of one conductivity type and a base region of another conductivity type and comprising a first surface;
    A trench comprising at least two opposing sidewalls and a bottom extending from the first surface through the base region to the common conductive region;
    A first gate insulator adjacent to one of the sidewalls;
    A first gate electrode extending adjacent to the first gate insulating portion and extending in the base region; a second gate insulating portion adjacent to the other of the sidewalls;
    A second gate electrode adjacent to the second gate insulating portion and extending in the base region;
    A source field electrode having a first part and a second part, wherein the first part of the source field electrode is disposed between the first gate electrode and the second gate electrode, The first gate electrode and the second gate electrode are insulated from each other, and the second portion of the source field electrode is disposed below the first portion and the gate electrode,
    A source region adjacent to each sidewall of the trench;
    A power semiconductor device comprising: the source field electrode; and a source contact electrically connected to the source region.
  2.   The source field electrode further comprising: a first insulating cap interposed between the source contact and the first gate electrode; and a second insulating cap interposed between the source contact and the second gate electrode. The semiconductor device according to claim 1, wherein the semiconductor device is disposed between the first insulating cap and the second insulating cap.
  3.   The semiconductor device of claim 1, wherein the source field electrode extends from the trench of the semiconductor body and extends above the first surface.
  4.   The semiconductor device of claim 1, further comprising a bottom insulating body disposed between a second portion of the source field electrode and a sidewall and bottom of the trench.
  5.   The semiconductor device according to claim 4, wherein the bottom insulating body is thicker than the gate insulating part.
  6.   The semiconductor device according to claim 5, wherein the insulating body is disposed below both gate electrodes.
  7.   The semiconductor device according to claim 1, wherein the source field electrode is made of conductive polysilicon.
  8.   The semiconductor device according to claim 1, wherein the gate electrode is made of conductive polysilicon.
  9.   The semiconductor device according to claim 1, wherein the semiconductor body is made of epitaxial silicon.
  10.   The semiconductor device of claim 9, wherein the epitaxial silicon is configured on a silicon substrate and further includes a drain contact that is ohmically connected to the silicon substrate.
  11.   An active area comprising at least one active cell, the active cell comprising at least one source region, a source contact electrode connected to the source region, and a source field electrode electrically connected to the source contact; An insulating gate electrode adjacent to one side of the source field electrode and the base region, the source field electrode being deeper than the depth of the insulating gate electrode and higher than the height of the insulating gate electrode. A power semiconductor device provided with a MOS gate, extending to a high level, wherein the source field electrode and the insulated gate electrode exist in a common trench.
  12.   The device of claim 11, further comprising another insulated gate electrode located in the common trench and adjacent to another side of the source field electrode and the base region.
  13.   The device of claim 12, wherein each insulated gate electrode has a respective electrode, the electrodes being electrically connected to each other.
  14.   The device of claim 11, further comprising an insulating body adjacent a bottom of the source field electrode.
  15.   The common trench is configured in a semiconductor body, extends from a top surface of the semiconductor body to a drift region in the semiconductor body, and the source field electrode extends above the top surface of the semiconductor body. The device of claim 11.
  16.   The device of claim 11, further comprising a termination area adjacent to the active region having a termination structure, wherein the termination structure includes a termination trench adjacent to the active area.
  17.   The device of claim 11, wherein the insulated gate electrode comprises a conductive gate electrode, and further comprises a gate bus and a gate contact electrically connected to the gate electrode.
  18.   The device of claim 11, further comprising a drain contact.
  19.   The device of claim 11, wherein the insulated gate electrode includes an insulating cap extending over an insulated source region.
  20.   The device of claim 12, wherein each insulated gate electrode comprises an insulating cap, and the insulated source field electrode extends above the insulating cap.
JP2007518368A 2004-06-25 2005-06-27 Power semiconductor device provided with a MOS gate having a source field electrode Pending JP2008504697A (en)

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