JP2001111041A - Super-junction semiconductor device and manufacturing method thereof - Google Patents

Super-junction semiconductor device and manufacturing method thereof

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JP2001111041A
JP2001111041A JP23728699A JP23728699A JP2001111041A JP 2001111041 A JP2001111041 A JP 2001111041A JP 23728699 A JP23728699 A JP 23728699A JP 23728699 A JP23728699 A JP 23728699A JP 2001111041 A JP2001111041 A JP 2001111041A
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conductivity
drift region
semiconductor device
type
partition regions
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JP3799888B2 (en
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Tatsuhiko Fujihira
Susumu Iwamoto
Yasushi Miyasaka
Yasuhiko Onishi
Katsunori Ueno
勝典 上野
泰彦 大西
靖 宮坂
進 岩本
龍彦 藤平
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Fuji Electric Co Ltd
富士電機株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Abstract

PROBLEM TO BE SOLVED: To ease realization of mass production by clarifying the effect of parameters of a super-junction semiconductor device having a drift layer comprising parallel pn layers which depletes in OFF state while conducting current in ON state. SOLUTION: The impurity amount in an (n) drift region 12a is in the range of 100-150% or of 110-150% of the impurity amount in a (p) partitioning region. Or, the impurity concentration in either of the (n) drift region 12a or the (p) partitioning region 12b is in the range of 92-108% of the impurity concentration in the other region. Besides, width of the one is in the range of 94-106% of the width of the other.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、オン状態では電流を流すとともに、オフ状態では空乏化する並列pn層からなる特別な構造を備えるMOSFET(絶縁ゲート型電界効果トランジスタ)、IGBT(絶縁ゲートバイポーラトランジスタ)、バイポーラトランジスタ、ダイオード等の半導体素子に関する。 BACKGROUND OF THE INVENTION The present invention, as well as current flow in the on state, MOSFET (insulated gate field effect transistor) with a special structure consisting of parallel pn layer depleted in the off state, IGBT (insulated gate bipolar transistor), a bipolar transistor, a semiconductor element such as a diode.

【0002】 [0002]

【従来の技術】相対向する二つの主面に設けられた電極間に電流が流される縦型半導体素子において、高耐圧化を図るには、両電極間の高抵抗層の厚さを厚くしなければならず、一方そのように厚い高抵抗層をもつ素子では、必然的に両電極間のオン抵抗が大きくなり、損失が増すことになることが避けられなかった。 In the vertical semiconductor device used to conduct current between the Related Art opposing provided two main surfaces electrodes, the achieve high breakdown voltage, by increasing the thickness of the high-resistance layer between the electrodes there must, on the one hand elements with such thick high resistance layer inevitably becomes large on-resistance between the electrodes, was inevitable that results in the loss increases. すなわちオン抵抗(電流容量)と耐圧間にはトレードオフ関係がある。 That on-resistance (current capacity) and a trade-off relationship exists between the breakdown voltage. このトレードオフ関係は、IGBT、バイポーラトランジスタ、ダイオード等の半導体素子においても同様に成立することが知られている。 This trade-off relationship, IGBT, it is known to hold also in the bipolar transistor, the semiconductor elements such as diodes. またこの問題は、オン時にドリフト電流が流れる方向と、オフ時の逆バイアスによる空乏層の延びる方向とが異なる横型半導体素子についても共通である。 Also this problem, a flow direction drift current when turned on, the direction of extension of the depletion layer due to the reverse bias when off is common for different lateral semiconductor device.

【0003】この問題に対する解決法として、ドリフト層を、不純物濃度を高めたn型の領域とp型の領域とを交互に積層した並列pn層で構成し、オフ状態のときは、空乏化して耐圧を負担するようにした構造の半導体装置が、EP0053854、USP5216275、 [0003] As a solution to this problem, the drift layer, and an n-type region and the p-type region having an increased impurity concentration constituted by parallel pn layer of alternately laminated, when the OFF state, the depletion the semiconductor device having a structure as to bear the breakdown voltage, EP0053854, USP5216275,
USP5438215および本発明の発明者らによる特開平9−266311号公報に開示されている。 USP5438215 and inventors of the present invention are disclosed in JP-A 9-266311 JP-by.

【0004】なお本発明の発明者らは、オン状態では電流を流すとともに、オフ状態では空乏化する並列pn層からなるドリフト層を備える半導体素子を超接合半導体素子と称することとした。 [0004] Note that the inventors of the present invention is to provide current flow in the on state, and be referred to a semiconductor device having a drift layer comprising a parallel pn layer depleted in the off state and the super-junction semiconductor device.

【0005】 [0005]

【発明が解決しようとする課題】しかし、前記の発明はいずれも、試作的な段階で、量産化のための検討がなされているとは言えない。 [0006] However, none foregoing invention is the prototype specific steps, it can not be said that consideration for mass production have been made. 例えば、並列pn層は、同じ不純物濃度、同じ幅とされている。 For example, the parallel pn layer is the same impurity concentration, the same width. しかし、実際の素子の製造過程では必ずばらつきを生じる。 However, always results in a variation in the manufacturing process of an actual device.

【0006】また、量産化および製品化において重要であるL負荷アバランシェ破壊電流に関する具体的な数値がこれまで規定されていない。 Further, specific values ​​are not specified so far regarding important L load avalanche breakdown current in the mass production and commercialization. 製品化のためには定格電流以上のL負荷アバランシェ破壊電流であることが望まれる。 Thing for commercialization is the rated current or more L load avalanche breakdown current is desired.

【0007】このような状況に鑑み本発明の目的は、不純物濃度、幅等について許容される範囲を明らかにすることによって、オン抵抗と耐圧とのトレードオフ関係を大幅に改善しつつ高耐圧を実現し、しかも量産に適した超接合半導体素子を提供することにある。 An object of the present invention has been made in view of such circumstances, the impurity concentration, by revealing the range allowed for the width or the like, while greatly improving the trade-off relationship between the ON resistance and the breakdown voltage of the high breakdown voltage realized, moreover to provide a super-junction semiconductor device suitable for mass production.

【0008】 [0008]

【課題を解決するための手段】上記の課題解決のため本発明は、第一と第二の主面と、主面に設けられた二つの主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列pn層とを備える超接合半導体素子において、第一導電型ドリフト領域の不純物量が第二導電型仕切り領域の不純物量の100〜150%の範囲内にあるものとする。 The present invention for the above problem solving SUMMARY In order to achieve the above, the first and the second main surface, and two main electrode provided on the principal surface, between the main electrodes, in the on state in super junction semiconductor device and a parallel pn layer disposed alternately and the first conductivity type drift region and a second conductivity-type partition regions depleted in the off state with electric current, the amount of impurities of the first conductivity type drift region there are intended to be within the scope 100-150% of the amount of impurities of the second conductivity type partition regions.

【0009】特に、第一導電型ドリフト領域の不純物量が第二導電型仕切り領域の不純物量の110〜150% In particular, the amount of impurities of the first conductivity type drift region 110 to 150% of impurities of the second conductivity type partition regions
の範囲内にあるのがよい。 It is preferable in the range of.

【0010】また、第一導電型ドリフト領域と第二導電型仕切り領域とがそれぞれほぼ同じ幅のストライプ状であることが有効である。 Further, it is effective and the first conductivity type drift region and a second conductivity-type partition regions is stripe width substantially equal, respectively.

【0011】また、これとは別に、第一と第二の主面と、主面に設けられた二つの電極と、その主電極間に、 [0011] Separately, the first and the second main surface, and two electrodes provided on the major surface, between its main electrodes,
オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列pn層とを備える超接合半導体素子において、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の不純物量が、他方の領域の不純物量の92〜108%の範囲内にあるものとする。 In super junction semiconductor device and a parallel pn layer disposed alternately and the first conductivity type drift region and a second conductivity-type partition regions depleted in the off state with current flow in the on state, the first conductivity type drift region When the amount of impurities in one region of the second conductivity type partition regions are intended to be within the scope of 92 to 108% of the amount of impurities in the other region.

【0012】特に、第一導電型ドリフト領域と第二導電型仕切り領域とがそれぞれほぼ同じ幅でありその内の一方の領域の平均不純物濃度が、他方の領域の平均不純物濃度の92〜108%の範囲内にあってもよいし、また、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の不純物濃度が、他方の領域の不純物濃度の92〜108%の範囲内にあってもよい。 [0012] In particular, the average impurity concentration of the one region of the first conductivity type drift region and a second conductivity-type partition regions of which are substantially the same width, respectively, from 92 to 108% of the average impurity concentration of the other region it may be within the range of the, also, the impurity concentration of one region of the first conductivity type drift region and a second conductivity-type partition regions, the range of 92 to 108% of the impurity concentration in the other region it may be within.

【0013】また、第一導電型ドリフト領域と第二導電型仕切り領域とがそれぞれほぼ同じ濃度でありその内の一方の領域の幅が、他方の領域の幅の94〜106%の範囲内にあるものとする。 Further, the width of one region of the first conductivity type drift region and a second conductivity-type partition regions of which is substantially the same concentration, respectively, in the range of 94 to 106% of the width of the other region and a certain thing.

【0014】第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列pn層とをオフ状態で空乏化するためには、両領域の不純物量がほぼ等量であることが必要である。 [0014] To depleted in the first conductivity type drift region off state and a parallel pn layer and a second conductivity-type partition regions arranged alternately, that amount of impurities in both regions is nearly equal amounts is necessary. 仮に一方の不純物濃度が他方の不純物濃度の半分であれば、倍の幅としなければならないことになる。 If if is one of the impurity concentration other half of the impurity concentration, it will have to be a multiple of the width. 従って、両領域は同じ不純物濃度とすると、 Therefore, when both regions are the same impurity concentration,
同じ幅ですむので、半導体表面の利用効率の点から最も良いことになる。 Since it requires only the same width, so that the best in terms of utilization efficiency of the semiconductor surface.

【0015】その同じ不純物濃度、同じ幅として、上記のようにすれば、双方の領域がほぼ均等に空乏層化するので、空乏化しない部分が残ることによる耐圧低下が、 The same impurity concentration thereof, as the same width, if as described above, since both the regions are depleted substantially uniformly, the breakdown voltage decreases due to the remaining portions not depleted,
後述するように理想的な場合の10%程度に抑えられる。 It is suppressed to approximately 10% of the ideal case, as described later.

【0016】製造方法としては、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の不純物量の92〜108%の範囲内にある不純物量の他方の領域をエピタキシャル成長により形成しても、一方の領域を形成するための不純物量の92〜108%の範囲内にある不純物量を導入した後、熱拡散により他方の領域を形成してもよい。 [0016] As a manufacturing method, by epitaxial growth and the other region of the impurity content in the range of 92 to 108% of impurities of one region of the first conductivity type drift region and a second conductivity-type partition regions it is formed, after introducing the impurity amount in the range of 92 to 108% of one of the areas the amount of impurities for forming may form the other region by thermal diffusion.

【0017】 [0017]

【発明の実施の形態】以下に本発明のためにおこなった実験とその結果について説明する。 Experiments were performed for the present invention in the following DETAILED DESCRIPTION OF THE INVENTION and their results will be described.

【0018】[実施例1]先ず、図3は実験に用いた縦型のnチャネル型の超接合MOSFETの基本的な部分の部分断面図である。 [0018] [Example 1] First, FIG. 3 is a partial cross-sectional view of a fundamental part of the vertical n-channel type super-junction MOSFET of used in the experiment. 他に、主に周縁部分に耐圧を保持するための部分が設けられるが、その部分は、例えばガードリング構造のような一般的な方法で形成される。 Otherwise, although the portion for holding the main breakdown voltage to the peripheral portion is provided, that part is formed, for example, in a conventional manner, such as a guard ring structure. なお以下でnまたはpを冠記した層や領域は、それぞれ電子、正孔を多数キャリアとする層、領域を意味している。 Incidentally layers and regions of the n or p prefixed below, a layer of electronically, a hole majority carriers respectively, which means an area. また添字の+は比較的高不純物濃度の、―は比較的低不純物濃度の領域をそれぞれ意味している。 Also of + a relatively high impurity concentration subscript, - are relatively low impurity concentration in the region of means, respectively.

【0019】図3において、11は低抵抗のn +ドレイン層、12はnドリフト領域12a、p仕切り領域12 [0019] In FIG. 3, n + drain layer of low resistance 11, 12 n drift region 12a, p partition regions 12
bとからなる並列pn層のドリフト層である。 b is a drift layer of the parallel pn layer composed of a. ドリフト層12のうちドリフト電流が流れるのは、nドリフト領域12aであるが、ここではp仕切り領域12bを含めた並列pn層をドリフト層12と呼ぶことにする。 Flowing a drift current of the drift layer 12 is the n drift region 12a, it is referred to herein as a drift layer 12 parallel pn layer including the p partition regions 12b. 表面層には、nドリフト領域12aに接続してnチャネル領域12dが、p仕切り領域12bに接続してpウェル領域13aがそれぞれ形成されている。 The surface layer, n channel regions 12d connected to the n drift region 12a is, p-well region 13a connected to the p partition regions 12b are formed, respectively. pウェル領域13 p-well region 13
aの内部にn +ソース領域14と高濃度のp +コンタクト領域13bとが形成されている。 inside the a and n + source regions 14 and the high-concentration p + contact region 13b is formed. +ソース領域14とnドリフト領域12aとに挟まれたpウェル領域13a n + source region 14 and n p-well region 13a sandwiched between the drift region 12a
の表面上には、ゲート絶縁膜15を介して多結晶シリコンのゲート電極層16が、また、n +ソース領域14と高濃度のp +コンタクト領域13bの表面に共通に接触するソース電極17が設けられている。 The on the surface, the gate electrode layer 16 of polycrystalline silicon through a gate insulating film 15, The source electrode 17 which contacts commonly with the n + source region 14 on the surface of the high concentration of p + contact region 13b is It is provided. +ドレイン層11の裏面にはドレイン電極18が設けられている。 on the back surface of the n + drain layer 11 drain electrode 18 is provided. 1
9は表面保護および安定化のための絶縁膜であり、例えば、熱酸化膜と燐シリカガラス(PSG)からなる。 9 is an insulating film for surface protection and stabilization, for example, a thermally oxidized film and phosphorous silica glass (PSG). ソース電極17は、図のように絶縁膜19を介してゲート電極層16の上に延長されることが多い。 The source electrode 17 is often extend over the gate electrode layer 16 via the insulating film 19 as shown in FIG. n型分割領域1とp型分割領域2の交互配置は、ストライプ状でも、 Alternate arrangement of the n-type divided region 1 and the p-type dividing region 2, even stripe,
一方を格子状とした他の方法でも良い。 One may be a grid with the other methods. nドリフト領域12aは、例えばエピタキシャル成長により形成される。 n drift region 12a is formed, for example by epitaxial growth. p仕切り領域12bは、nドリフト領域12aに設けられた掘り下げ部にエピタキシャル成長により充填して形成する。 p partition regions 12b is formed by filling by epitaxial growth dug portion provided in the n drift region 12a. この製造方法に関しては特願平10―20 Japanese Patent Application No. about this manufacturing method 10-20
9267号で詳細に説明している。 It is described in detail in No. 9267.

【0020】例えば、400VクラスのMOSFETとして、各部の基準的な寸法および不純物濃度等は次のような値をとる。 [0020] For example, as MOSFET of 400V class, the reference dimensions and the impurity concentration, etc. of each part takes the following values. +ドレイン層11の比抵抗は0.01 The specific resistance of the n + drain layer 11 is 0.01
Ω・cm、厚さ350μm、ドリフト層12の厚さ32 Omega · cm, the thickness of the thickness 350 .mu.m, the drift layer 12 32
μm、nドリフト領域12aおよびp仕切り領域12b [mu] m, n drift region 12a and p partition regions 12b
の幅8μm(すなわち、同じ領域の中心間間隔16μ Width 8 [mu] m (i.e., center-to-center spacing of the same region 16μ
m)、不純物濃度3.0×10 15 cm― 3 、pウェル領域13aの拡散深さ3μm、表面不純物濃度2×10 17 m), the impurity concentration of 3.0 × 10 15 cm- 3, p diffusion depth 3μm well region 13a, the surface impurity concentration of 2 × 10 17
cm― 3 、n +ソース領域14の拡散深さ0.3μm、表面不純物濃度3×10 20 cm― 3である。 cm- 3, n + diffusion depth 0.3μm source region 14, a surface impurity concentration of 3 × 10 20 cm- 3.

【0021】例えば、800VクラスのMOSFETとして、各部の基準的な寸法および不純物濃度等は次のような値をとる。 [0021] For example, as MOSFET of 800V class, like reference dimensions and the impurity concentrations of respective portions may take on these values. +ドレイン層11の比抵抗は0.01 The specific resistance of the n + drain layer 11 is 0.01
Ω・cm、厚さ350μm、ドリフト層12の厚さ48 Ω · cm, thickness 350μm, of the drift layer 12 thickness 48
μm、nドリフト領域12aおよびp仕切り領域12b [mu] m, n drift region 12a and p partition regions 12b
の幅5μm(すなわち、同じ領域の中心間間隔10μ Width 5 [mu] m (i.e., center-to-center spacing 10μ of the same region
m)、不純物濃度3.5×10 15 cm― 3 、pウェル領域13aの拡散深さ1μm、表面不純物濃度3×10 18 m), the impurity concentration of 3.5 × 10 15 cm- 3, p diffusion depth 1μm well region 13a, the surface impurity concentration of 3 × 10 18
cm― 3 、n +ソース領域14の拡散深さ0.3μm、表面不純物濃度1×10 20 cm― 3である。 cm- 3, n + diffusion depth 0.3μm source region 14, a surface impurity concentration of 1 × 10 20 cm- 3.

【0022】図3の超接合MOSFETの動作は、次のようにおこなわれる。 [0022] Operation of the super-junction MOSFET of Figure 3 is performed as follows. ゲート電極層16に所定の正の電圧が印加されると、ゲート電極層16直下のpウェル領域13aの表面層に反転層が誘起され、n +ソース領域14から反転層を通じてnチャネル領域13dに電子が注入される。 When voltage of a predetermined positive gate electrode layer 16 is applied, an inversion layer is induced in the surface layer of the p-well region 13a immediately under the gate electrode layer 16, the n-channel region 13d through the inversion layer from the n + source region 14 electrons are injected. その注入された電子がnドリフト領域12 Its injected electrons n drift region 12
aを通じてn +ドレイン層11に達し、ドレイン電極1 reached n + drain layer 11 through a, the drain electrode 1
8、ソース電極17間が導通する。 8, the conduction between the source electrode 17.

【0023】ゲート電極層16への正の電圧が取り去られると、pウェル領域13aの表面層に誘起された反転層がが消滅し、ドレイン電極18、ソース電極17間が遮断される。 [0023] positive voltage to the gate electrode layer 16 is removed, the inversion layer induced in the surface layer of the p-well region 13a is disappears, the drain electrode 18, is between the source electrode 17 is interrupted. 更に、逆バイアス電圧を大きくすると、各p仕切り領域12bはpウェル領域13aを介してソース電極17で連結されているので、pウェル領域13a Furthermore, increasing the reverse bias voltage, since the p partition regions 12b are connected by the source electrode 17 through the p-well region 13a, the p-well region 13a
とnチャネル領域12dとの間のpn接合Ja、nドリフト領域12aとp仕切り領域12bとの間のpn接合Jbからそれぞれ空乏層がnドリフト領域12a、p仕切り領域12b内に広がってこれらが空乏化される。 pn junction Ja, respectively depletion layer from the pn junction Jb between the n drift region 12a and the p partition regions 12b are n drift region 12a, these spreads in p partition regions 12b depletion between the n-channel region 12d It is of.

【0024】pn接合Jbからの空乏端は、nドリフト領域12aの幅方向に広がり、しかも両側のp仕切り領域12bから空乏層が広がるので空乏化が非常に早まる。 The depletion ends from the pn junction Jb, spread in the width direction of the n drift region 12a, moreover depletion very premature because a depletion layer spreads from both sides of the p partition regions 12b. 従って、nドリフト領域12aの不純物濃度を高めることができる。 Therefore, it is possible to increase the impurity concentration of the n drift region 12a. またp仕切り領域12bも同時に空乏化される。 The p partition regions 12b are also depleted simultaneously. p仕切り領域12bも両側のpn接合から空乏層が広がるので空乏化が非常に早まる。 Since p partition regions 12b also a depletion layer extends from both sides of the pn junction depletion is accelerated very much. p仕切り領域12bとnドリフト領域12aとを交互に形成することにより、隣接するnドリフト領域12aの双方へ空乏端が進入するようになっているので、空乏層形成のためのp仕切り領域12bの総占有幅を半減でき、その分、n By forming the p partition region 12b and the n drift region 12a alternately, since the depletion end to both of the adjacent n drift region 12a is adapted to enter, the p partition regions 12b for the depletion layer forming the total occupied width can be halved, that amount, n
ドリフト領域12aの断面積の拡大を図ることができる。 It is possible to increase the cross-sectional area of ​​the drift region 12a. [実施例2]p仕切り領域12bのボロンの不純物量(ドーズ量)を1×10 13 cm -2に固定して、これに対するnドリフト領域12aのリンの不純物量(ドーズ量)を80〜150%の範囲で変えてnチャネル型MO [Example 2] fixed amount of impurities of boron p partition regions 12b (the dose) to 1 × 10 13 cm -2, the amount of impurities of phosphorus n drift region 12a against which the (dose) 80-150 n-channel type MO change in% of range
SFETをシミュレーションし、また実際に試作して確認した。 To simulate the SFET, also it was confirmed by actual trial.

【0025】図5は、オン抵抗(Ron・A)と発生耐圧(V DSS )の不純物量依存性を示す特性図である。 FIG. 5 is a characteristic diagram showing an impurity amount dependence of on-resistance (Ron · A) and generating breakdown voltage (V DSS). 横軸は、発生耐圧(V DSS )、縦軸はオン抵抗(Ron・A) The horizontal axis, generating breakdown voltage (V DSS), the vertical axis represents the on-resistance (Ron · A)
である。 It is. p仕切り領域12bの不純物量(ドーズ量) The amount of impurities in the p partition regions 12b (dose)
は1×10 13 cm -2に固定し、幅はともに8μmとし、 Is fixed to 1 × 10 13 cm -2, width together with 8 [mu] m,
ドリフト層12の深さは32μmとした。 The depth of the drift layer 12 was set to 32 [mu] m.

【0026】例えば、 nドリフト領域12aの不純物量を1.0×10 13 cm -2 (100%)のとき、発生耐圧は445Vで、オン抵抗は38mΩ・cm 2となるが、 [0026] For example, when the impurity amount of the n-drift region 12a of 1.0 × 10 13 cm -2 (100 %), generating breakdown voltage at 445V, the on-resistance becomes a 38mΩ · cm 2,
1.3×10 13 cm -2 (130%)とすると発生耐圧は3 1.3 × 10 13 cm -2 occur breakdown voltage and a (130%) of 3
65Vでオン抵抗は24mΩ・cm 2に、1.5×10 On resistance to 24mΩ · cm 2 at 65V, 1.5 × 10
13 cm -2 (150%)とすると発生耐圧は280Vでオン抵抗は20mΩ・cm 2に低下する。 13 occurs withstand the cm -2 (150%) to the on-resistance at 280V falls 20mΩ · cm 2.

【0027】図から、 nドリフト領域12aの不純物量がp仕切り領域12bの不純物量に対して100〜1 [0027] From the figure, the amount of dopant in the n-drift region 12a is to impurities of p partition regions 12b 100 to 1
50%になるに従い、発生耐圧(V DSS )は低下するものの、オン抵抗(Ron・A)が低減されることがわかる。 According to 50% occurs withstand (V DSS) although reduced, it can be seen that the on resistance (Ron · A) is reduced. また、この100〜150%の範囲での製品毎のオン抵抗(Ron・A)のばらつきは小さいので、量産時には発生耐圧のばらつきのみを考慮して製造すればよくなるので、製造や工程管理が容易となる。 Further, since the variations in the on-resistance of each product in the range of 100~150% (Ron · A) is small, so is well be manufactured considering only variations in the occurrence breakdown voltage in mass production, easy to manufacture and process control to become. また、この実施例は400Vクラスとしたが、どの耐圧クラスでも同じことが言える。 Further, this embodiment is set to 400V class, the same is true in any Voltage class.

【0028】[実施例3]図6は、L負荷アバランシェ破壊電流(A)の不純物量依存性を示す特性図である。 [0028] [Embodiment 3] FIG. 6 is a characteristic diagram showing an impurity amount dependence of L load avalanche breakdown current (A).
横軸は、 nドリフト領域12aのリンの不純物量(ドーズ量)、縦軸はL負荷アバランシェ破壊電流(A)である。 The horizontal axis, the amount of impurities of phosphorus n drift region 12a (dose), and the vertical axis represents the L load avalanche breakdown current (A). p仕切り領域12bのボロンの不純物量(ドーズ量)を1×10 13 cm -2に固定して、これに対するn the amount of impurities of boron p partition regions 12b (the dose) was fixed to 1 × 10 13 cm -2, n for which
ドリフト領域12aのリンの不純物量(ドーズ量)を8 The amount of impurities of phosphorus in the drift region 12a (the dose) 8
0〜150%の範囲で変えた。 It was varied in the range 0 to 150%. 設定条件は実施例1と同じである。 Setting conditions were the same as in Example 1.

【0029】例えば、 nドリフト領域12aの不純物量を1.0×10 13 cm -2 (100%)のとき、アバランシェ破壊電流(A)は約7Aとなるが、1.3×10 13 [0029] For example, when the impurity amount of the n-drift region 12a 1.0 × 10 13 cm -2 (100%), an avalanche breakdown current (A) is approximately 7A, 1.3 × 10 13
cm -2 (130%)とするとアバランシェ破壊電流(A) cm -2 (130%) to the avalanche breakdown current (A)
は約63Aに、1.5×10 To about 63A, 1.5 × 10 13 cm -2 (150%)とするとアバランシェ破壊電流(A)は約72Aとなる。 13 cm -2 (150%) to the avalanche breakdown current (A) is about 72A.

【0030】図から、L負荷アバランシェ破壊電流が定格電流以上、好ましくは2倍以上要求される場合には、 [0030] From the figure, when the L load avalanche breakdown current than the rated current, preferably required twice or more,
nドリフト領域12aの不純物量(ドーズ量)を11 The amount of dopant in the n-drift region 12a (the dose) 11
0%以上にすればよいことがわかる。 It can be seen that may be set to 0% or more. また、140%以上でのL負荷アバランシェ破壊電流は飽和傾向であるので、図1での発生耐圧の低下を考慮すると150%以下であることが望ましい。 Further, the L load avalanche breakdown current at 140% or more because it is saturation tendency is desirably 150% or less in consideration of the decrease in the occurrence breakdown voltage in Fig. また、このL負荷アバランシェ破壊電流に関してもどの耐圧クラスでも同じことが言える。 Further, the same is true in any breakdown voltage class on this L load avalanche breakdown current.

【0031】以上の実験により並列pn層のnドリフト領域12aおよびp仕切り領域12bの不純物量の許容される範囲が明らかになったので、これを基に超接合半導体素子を設計すれば、オン抵抗と耐圧とのトレードオフ関係を大幅に改善しつつ、更にL負荷アバランシェ破壊の保証をした、高耐圧の超接合半導体素子の量産化が容易にできる。 The above therefore acceptable range of the impurity of the n drift region 12a and p partition regions 12b of the parallel pn layer revealed by experiments, by designing superjunction semiconductor device based on this, the on-resistance and while greatly improved trade-off relationship between the breakdown voltage was further guarantees L load avalanche breakdown, mass production of high-voltage superjunction semiconductor device can be easily. [実施例4]p仕切り領域12bの不純物濃度C Pを変えてnチャネル型MOSFETをシミュレーションし、 Simulating the n-channel type MOSFET by changing the impurity concentration C P of Example 4] p partition regions 12b,
また実際に試作して確認した。 Also it was confirmed by actual trial.

【0032】図1は、耐圧(V DSS )の不純物濃度C P依存性を示す特性図である。 [0032] Figure 1 is a characteristic diagram showing an impurity concentration C P dependence of breakdown voltage (V DSS). 横軸は、p仕切り領域12b The horizontal axis, p partition regions 12b
の不純物濃度C P 、縦軸は耐圧(V DSS )である。 Impurity concentration C P of the vertical axis represents the breakdown voltage (V DSS). nドリフト領域12aの不純物濃度C nは3.5×10 15 cm The impurity concentration of the n drift region 12a C n is 3.5 × 10 15 cm
-3に固定し、幅はともに5μmとし、ドリフト層12の深さは48μmとした。 Fixed to -3, width together with 5 [mu] m, the depth of the drift layer 12 was set to 48 [mu] m.

【0033】例えば、C n =C P =3.5×10 15 cm -3 [0033] For example, C n = C P = 3.5 × 10 15 cm -3
のとき、耐圧は最大値960Vとなるが、C P =3×1 When, while the breakdown voltage is the maximum value 960V, C P = 3 × 1
15 cm -3とすると耐圧は約750Vに、2×10 15 0 15 cm -3 to the breakdown voltage of about 750V, 2 × 10 15 c
-3とすると更に約380Vに低下する。 further decreased to about 380V When m -3.

【0034】これは、nドリフト領域12aに十分空乏化しきれない部分を生じるためである。 [0034] This is because the n drift region 12a produces a part that can not be fully depleted. 逆にp仕切り領域12bの不純物濃度をnドリフト領域12aより高くしたときは、p仕切り領域12bに十分空乏化しきれない部分を生じて、やはり耐圧が低下する。 Conversely when the impurity concentration of the p partition regions 12b and higher than the n drift region 12a is caused a portion which can not be sufficiently depleted p partition regions 12b, also the breakdown voltage is lowered.

【0035】図から、p仕切り領域12bの不純物濃度C Pが、nドリフト領域12aの不純物濃度C nに対して上下8%以内にあるならば、耐圧の低下は10%程度ですむことがわかる。 [0035] From FIG., P impurity concentration C P of the partition region 12b is, if with respect to the impurity concentration C n of the n drift region 12a is within 8% above and below, a reduction in the breakdown voltage is found to live in 10% .

【0036】この実施例は、p仕切り領域12bの不純物濃度C Pを変えた場合であるが、同じことは当然nドリフト領域12aの不純物濃度C nを変えた場合についても言える。 [0036] This embodiment is the case of changing the impurity concentration C P of the p partition regions 12b, same is true of the case where naturally changed impurity concentration C n of the n drift region 12a. また、設定耐圧に関してもどの耐圧クラスでも同じことが言える。 In addition, the same is true in any breakdown voltage class with respect to setting the breakdown voltage. [実施例5]次に、nドリフト領域12aの幅L nを5 [Example 5] Next, 5 width L n in the n drift region 12a
μm一定とし、p仕切り領域12bの幅L Pを変えてn and μm constant, n by changing the width L P of p partition regions 12b
チャネル型MOSFETをシミュレーションし、また実際に試作して確認した。 To simulate the channel type MOSFET, also it was confirmed by actual trial.

【0037】図1は、耐圧(V DSS )の寸法依存性を示す特性図である。 [0037] FIG. 1 is a characteristic diagram showing the dimensional dependency of the withstand voltage (V DSS). 横軸は、p仕切り領域12bの幅L P 、縦軸は耐圧(V DSS )である。 The horizontal axis, width L P of p partition regions 12b, and the vertical axis represents the breakdown voltage (V DSS). 不純物濃度は3.5 The impurity concentration is 3.5
×10 15 cm -3に固定し、ドリフト層12の深さは48 × fixed to 10 15 cm -3, the depth of the drift layer 12 is 48
μmとした。 It was μm.

【0038】例えば、L n =L P =5μmのとき、耐圧は最大値960Vとなるが、L P =4μmとすると耐圧は約550Vに低下する。 [0038] For example, when L n = L P = 5μm, the breakdown voltage is the maximum value 960V, the breakdown voltage when the L P = 4 [mu] m is reduced to about 550 V.

【0039】これは、nドリフト領域12aに十分空乏化しきれない部分を生じるためである。 [0039] This is because the n drift region 12a produces a part that can not be fully depleted. 逆にp仕切り領域12bをnドリフト領域12aより厚くしたときは、 When the p partition regions 12b and thicker than the n drift region 12a is reversed,
p仕切り領域12bに十分空乏化しきれない部分を生じて、やはり耐圧が低下する。 The p partition regions 12b caused a portion which can not be sufficiently depleted, still withstand voltage is lowered.

【0040】図から、p仕切り領域12bの幅L Pが、 [0040] from the figure, the width L P of the p partition regions 12b is,
nドリフト領域12aの幅L nに対して上下6%以内にあるならば、耐圧の低下は10%程度ですむことがわかる。 If the width L n in the n drift region 12a is within 6% above and below, a reduction in the breakdown voltage is found to be need about 10%.

【0041】この実施例は、p仕切り領域12bの幅L [0041] This example, the width of the p partition regions 12b L
Pを変えた場合であるが、同じことは当然nドリフト領域12aの幅L nを変えた場合についても言える。 Is a case of changing the P, same is true of the case where naturally changed width L n in the n drift region 12a. また、設定耐圧に関してもどの耐圧クラスでも同じことが言える。 In addition, the same is true in any breakdown voltage class with respect to setting the breakdown voltage.

【0042】以上の実験により並列pn層のnドリフト領域12aおよびp仕切り領域12bの不純物濃度や寸法等の許容される範囲が明らかになったので、これを基に超接合半導体素子を設計すれば、オン抵抗と耐圧とのトレードオフ関係を大幅に改善しつつ、高耐圧の超接合半導体素子の量産化が容易にできる。 The above therefore acceptable range of the impurity concentration and dimensions of the n drift region 12a and p partition regions 12b of the parallel pn layer revealed by experiments, by designing superjunction semiconductor device based on this while greatly improved trade-off relationship between the oN resistance and the breakdown voltage, mass production of high-voltage superjunction semiconductor device can be easily. [実施例6]他の製造方法として、エピタキシャル成長の前に部分的に不純物の埋め込み領域を形成しておいてから、高抵抗層をエピタキシャル成長する工程を数回繰り返した後、熱処理により拡散させて並列pn層を形成することもできる。 [Example 6] Other manufacturing methods, from left to form a partially impurity buried region prior to epitaxial growth, after the high-resistance layer was repeated several times the step of epitaxially growing, parallel to diffuse by heat treatment it is also possible to form the pn layer.

【0043】図4はそのような方法で製造した縦型のn [0043] Figure 4 is a vertical prepared in such a way n
チャネル型超接合MOSFETの基本的な部分の部分断面図である。 It is a partial cross-sectional view of a fundamental part of the channel superjunction MOSFET.

【0044】図3の超接合MOSFETの断面図と殆ど変わらないが、nドリフト領域22a、p仕切り領域2 [0044] While almost the same cross-sectional view of a super-junction MOSFET in FIG. 3, n drift region 22a, p partition regions 2
2bが均一な不純物濃度でなく、内部に不純物濃度分布があることが違っている。 2b is not uniform impurity concentration, is different that there is an impurity concentration distribution in the interior. 分かり易くするため、点線で等しい不純物濃度の線を示した。 For clarity, showing lines of equal dopant concentration in dotted lines. 等しい不純物濃度の線は、曲線(三次元的には曲面)となっている。 Lines of equal dopant concentration has a curve (curved in three dimensions). これは不純物の埋め込み領域を形成しておいてから、高抵抗層をエピタキシャル成長する工程を数回繰り返した後、熱処理により埋め込まれ不純物源から拡散したためである。 This from left to form a buried region of the impurity, after a high-resistance layer was repeated several times the step of epitaxially growing, because diffused from implanted by thermal treatment impurity source.
十分な拡散時間を経れば、nドリフト領域22aとp仕切り領域22bとの境界は図のような直線(三次元的には平面)となる。 Having passed through a sufficient diffusion time, the boundary between the n drift region 22a and the p partition regions 22b is a straight line (three-dimensional in the plane) as shown in FIG.

【0045】このような場合に、nドリフト領域22 [0045] In such a case, n-drift region 22
a、p仕切り領域22bが十分空乏化しきれない部分を生じることが無いようにするには、両領域に埋め込まれた不純物量がほぼ等しいことが重要である。 a, To p partition regions 22b are never produce parts which can not be sufficiently depleted, the amount of impurities that are embedded in both regions it is important that substantially equal.

【0046】特に、先に述べたように、nドリフト領域22a、p仕切り領域22bの幅が等しい時に、半導体結晶面の利用率が大きくなることから、nドリフト領域22a、p仕切り領域22bの平均不純物濃度がほぼ等しいことが重要である。 [0046] In particular, as previously described, n drift region 22a, when the width of the p partition regions 22b are equal, since the utilization rate of the semiconductor crystal surface is increased, n drift region 22a, the average of p partition regions 22b it is important that the impurity concentration substantially equal.

【0047】そして、この例の場合も、実施例3と全く同じく、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の不純物量が、他方の領域の不純物量の92〜108%の範囲内にあれば、耐圧の低下は10%程度に抑えられる。 [0047] Even in this case, exactly the same as in Example 3, the amount of impurities in one region of the first conductivity type drift region and a second conductivity-type partition regions, the amount of impurities in the other region if in the range of 92 to 108%, decrease in breakdown voltage is suppressed to about 10%.

【0048】幅が等しいとすれば、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の平均不純物濃度が、他方の領域の平均不純物濃度の92〜1 [0048] If the width is equal, the average impurity concentration of the one region of the first conductivity type drift region and a second conductivity-type partition regions 92-1 of the average impurity concentration of the other region
08%の範囲内にあればよいことになる。 So that may be in the 08% range.

【0049】また、nドリフト領域22a、p仕切り領域22bの幅の許容範囲としても、94〜106%の範囲内にあればよいことになる。 [0049] Also, n drift region 22a, as the allowable range of the width of the p partition regions 22b, so that may be in the range of 94-106%.

【0050】なお、nドリフト領域12aおよびp仕切り領域12bの幅を狭くし、不純物濃度を高くすれば、 [0050] Incidentally, by narrowing the width of the n drift region 12a and p partition regions 12b, if increasing the impurity concentration,
より一層のオン抵抗の低減、オン抵抗と耐圧とのトレードオフ関係の改善が可能である。 More of further on-resistance reduction, it is possible to improve the trade-off relationship between the ON resistance and the breakdown voltage.

【0051】なお、実施例は縦型のMOSFETの例を掲げたが、この問題は、オン時にドリフト電流が流れる方向と、オフ時の逆バイアスによる空乏層の延びる方向とが異なる横型半導体素子についても共通である。 [0051] Although examples listed examples of a vertical MOSFET, this problem, a direction at the time of ON flows drift current for the direction of extension of the depletion layer due to the reverse bias is different lateral semiconductor device in the OFF state it is also common. 更に、IGBTやpnダイオード、ショットキーバリアダイオード、バイポーラトランジスタでも同様の効果が得られる。 Further, IGBT or a pn diode, a Schottky barrier diode, the same effect can be obtained in the bipolar transistor.

【0052】 [0052]

【発明の効果】以上説明したように本発明は、オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列pn層とを備える超接合半導体素子において、並列pn層の第一導電型ドリフト領域と第二導電型仕切り領域との不純物濃度や寸法等の許容される範囲を明らかにすることによって、オン抵抗と耐圧とのトレードオフ関係を大幅に改善しつつ、更にL負荷アバランシェ破壊の保証をして、高耐圧の超接合半導体素子の量産化を容易にした。 The present invention described above, according to the present invention includes a parallel pn layer disposed alternately and the first conductivity type drift region and a second conductivity-type partition regions depleted in the off state with current flow in the on state in super junction semiconductor device comprising, by revealing the acceptable range of the impurity concentration and dimensions of the first conductivity type drift region and a second conductivity-type partition regions of the parallel pn layer, the on-resistance and breakdown voltage while greatly improved trade-off relationship, and further guarantees L load avalanche breakdown and facilitates mass production of the high voltage superjunction semiconductor device.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の超接合MOSFETにおける耐圧(V [1] the breakdown voltage in the super-junction MOSFET of the present invention (V
DSS )のL P幅依存性を示す特性図 Characteristic diagram showing the L P width dependence of DSS)

【図2】耐圧(V DSS )の不純物濃度C P依存性を示す特性図 [Figure 2] characteristic diagram showing an impurity concentration C P dependence of breakdown voltage (V DSS)

【図3】実施例1の超接合MOSFETの基本的な構造部分の部分断面図 Figure 3 is a partial cross-sectional view of the basic structural parts of the super-junction MOSFET of Example 1

【図4】実施例2の超接合MOSFETの基本的な構造部分の部分断面図 Figure 4 is a partial cross-sectional view of the basic structural parts of the super-junction MOSFET of Example 2

【図5】本発明の超接合MOSFETにおけるオン抵抗(Ron・A)と発生耐圧(V DS [5] on-resistance in the super-junction MOSFET of the present invention (Ron · A) and generating breakdown voltage (V DS S )の不純物量依存性を示す特性図 Characteristic diagram showing an impurity amount dependence of S)

【図6】L負荷アバランシェ破壊電流(A)の不純物量依存性を示す特性図 [6] characteristic diagram showing an impurity amount dependence of L load avalanche breakdown current (A)

【符号の説明】 DESCRIPTION OF SYMBOLS

11、21 n +ドレイン層 12、22 ドリフト層 12a、22a nドリフト領域 12b、22b p仕切り領域 13a、23a pウェル領域 13b、23b p +コンタクト領域 14、24 n +ソース領域 15 ゲート絶縁膜 16 ゲート電極層 17 ソース電極 18 ドレイン電極 19 絶縁膜 11 and 21 n + drain layer 12 and 22 drift layer 12a, 22a n drift region 12b, 22b p partition regions 13a, 23a p-well region 13b, 23b p + contact region 14, 24 n + source region 15 a gate insulating film 16 gate electrode layer 17 source electrode 18 drain electrode 19 insulating film

フロントページの続き (72)発明者 大西 泰彦 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式 会社内 (72)発明者 上野 勝典 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式 会社内 (72)発明者 岩本 進 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式 会社内 Of the front page Continued (72) inventor Yasuhiko Onishi, Kawasaki City, Kanagawa Prefecture Kawasaki-ku, Tanabeshinden No. 1 No. 1 Fuji Electric shares in the company (72) inventor Ueno, Katsunori, Kawasaki City, Kanagawa Prefecture Kawasaki-ku, Tanabeshinden No. 1 No. 1 Fuji electric shares in the company (72) inventor Susumu Iwamoto Kawasaki City, Kanagawa Prefecture Kawasaki-ku, Tanabeshinden No. 1 No. 1 Fuji electric shares in the company

Claims (10)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】第一と第二の主面と、主面に設けられた二つの主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列p And 1. A first and a second major surface, and two main electrode provided on the principal surface, between the main electrodes, the first conductivity type depletion in the off state with current flow in the on state parallel p arranged a drift region and a second conductivity-type partition regions alternately
    n層を備える超接合半導体素子において、第一導電型ドリフト領域の不純物量が第二導電型仕切り領域の不純物量の100〜150%の範囲内にあることを特徴とする超接合半導体素子。 In super junction semiconductor device comprising an n-layer, the superjunction semiconductor device characterized by the amount of impurities of the first conductivity type drift region is in the range from 100 to 150 percent of the amount of the impurity of the second conductivity type partition regions.
  2. 【請求項2】第一と第二の主面と、主面に設けられた二つの主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列p 2. A first and a second major surface, and two main electrode provided on the principal surface, between the main electrodes, the first conductivity type depletion in the off state with current flow in the on state parallel p arranged a drift region and a second conductivity-type partition regions alternately
    n層を備える超接合半導体素子において、第一導電型ドリフト領域の不純物量が第二導電型仕切り領域の不純物量の110〜150%の範囲内にあることを特徴とする超接合半導体素子。 In super junction semiconductor device comprising an n-layer, the superjunction semiconductor device characterized by the amount of impurities of the first conductivity type drift region is in the range of 110 to 150% of the amount of impurities of the second conductivity type partition regions.
  3. 【請求項3】第一と第二の主面と、主面に設けられた二つの主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列p 3. A first and a second major surface, and two main electrode provided on the principal surface, between the main electrodes, the first conductivity type depletion in the off state with current flow in the on state parallel p arranged a drift region and a second conductivity-type partition regions alternately
    n層を備える超接合半導体素子において、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の不純物量が、他方の領域の不純物量の92〜108% In super junction semiconductor device comprising an n-layer, impurity amount of one region of the first conductivity type drift region and a second conductivity-type partition regions, 92 to 108% of the amount of impurities in the other region
    の範囲内にあることを特徴とする超接合半導体素子。 Superjunction semiconductor device, characterized in that in the range of.
  4. 【請求項4】第一導電型ドリフト領域と第二導電型仕切り領域とがそれぞれストライプ状であることを特徴とする請求項1乃至請求項3のいずれか1項に記載の超接合半導体素子。 4. A super-junction semiconductor device according to any one of claims 1 to 3 and the first conductive type drift region and a second conductivity-type partition regions are characterized by a stripe shape respectively.
  5. 【請求項5】第一と第二の主面と、主面に設けられた二つの主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列p 5. A first and a second major surface, and two main electrode provided on the principal surface, between the main electrodes, the first conductivity type depletion in the off state with current flow in the on state parallel p arranged a drift region and a second conductivity-type partition regions alternately
    n層を備える超接合半導体素子において、第一導電型ドリフト領域と第二導電型仕切り領域とがそれぞれほぼ同じ幅であり、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の平均不純物濃度が、他方の領域の平均不純物濃度の92〜108%の範囲内にあることを特徴とする超接合半導体素子。 In super junction semiconductor device comprising an n-layer, a first conductive type drift region and a second conductivity-type partition regions is substantially the same width, respectively, one of a first conductive type drift region and a second conductivity-type partition regions superjunction semiconductor device is an average impurity concentration of the region, characterized in that in the range of 92 to 108% of the average impurity concentration in the other regions.
  6. 【請求項6】第一と第二の主面と、主面に設けられた二つの主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列p 6. first and a second major surface, and two main electrode provided on the principal surface, between the main electrodes, the first conductivity type depletion in the off state with current flow in the on state parallel p arranged a drift region and a second conductivity-type partition regions alternately
    n層を備える超接合半導体素子において、第一導電型ドリフト領域と第二導電型仕切り領域とがそれぞれほぼ同じ幅であり、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の不純物濃度が、他方の領域の不純物濃度の92〜108%の範囲内にあることを特徴とする超接合半導体素子。 In super junction semiconductor device comprising an n-layer, a first conductive type drift region and a second conductivity-type partition regions is substantially the same width, respectively, one of a first conductive type drift region and a second conductivity-type partition regions superjunction semiconductor device the impurity concentration of the region, characterized in that in the range of 92 to 108% of the impurity concentration in the other regions.
  7. 【請求項7】第一と第二の主面と、主面に設けられた二つの主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列p 7. first and a second major surface, and two main electrode provided on the principal surface, between the main electrodes, the first conductivity type depletion in the off state with current flow in the on state parallel p arranged a drift region and a second conductivity-type partition regions alternately
    n層を備える超接合半導体素子において、第一導電型ドリフト領域と第二導電型仕切り領域とがそれぞれほぼ同じ濃度であり、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の幅が、他方の領域の幅の94〜106%の範囲内にあることを特徴とする超接合半導体素子。 In super junction semiconductor device comprising an n-layer, a first conductive type drift region and a second conductivity-type partition regions is at a concentration substantially the same respective one of a first conductive type drift region and a second conductivity-type partition regions superjunction semiconductor device the width of the region, characterized in that in the range of 94 to 106% of the width of the other region.
  8. 【請求項8】二つの主電極が、それぞれ第一、第二の主面に設けられていることを特徴とする請求項1ないし請求項7のいずれか1項に記載の超接合半導体素子。 8. The two main electrodes, first each super-junction semiconductor device according to any one of claims 1 to 7, characterized in that provided on the second major surface.
  9. 【請求項9】第一と第二の主面と、主面に設けられた二つの主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列pn層とを備える超接合半導体素子の製造方法において、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域の不純物量の92〜108%の範囲内にある不純物量の他方の領域をエピタキシャル成長により形成することを特徴とする超接合半導体素子の製造方法。 9. first and a second major surface, and two main electrode provided on the principal surface, between the main electrodes, depleted in the off state with current flow in the on state, the first conductive in type drift region and a manufacturing method of super-junction semiconductor device and a parallel pn layer disposed alternately and a second conductivity-type partition regions, one of the first conductive type drift region and a second conductivity-type partition regions method of manufacturing a super-junction semiconductor device characterized by forming the other regions of the impurity content in the range of 92 to 108% of the amount of impurities in regions by epitaxial growth.
  10. 【請求項10】第一と第二の主面と、主面に設けられた二つの主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列pn層とを備える超接合半導体素子の製造方法において、第一導電型ドリフト領域と第二導電型仕切り領域との内の一方の領域を形成するための不純物量の92〜1 10. A first and a second major surface, and two main electrode provided on the principal surface, between the main electrodes, depleted in the off state with current flow in the on state, the first conductive in type drift region and a manufacturing method of super-junction semiconductor device and a parallel pn layer disposed alternately and a second conductivity-type partition regions, one of the first conductive type drift region and a second conductivity-type partition regions 92-1 in the amount of impurity for forming the region
    08%の範囲内にある不純物量を導入した後、熱拡散により他方の領域を形成することを特徴とする超接合半導体素子の製造方法。 After introduction of the amount of impurities that are within 08% of the range, the production method of the super junction semiconductor device characterized by forming the other regions by thermal diffusion.
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