JP2001111041A - Super-junction semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ease realization of mass production by clarifying the effect of parameters of a super-junction semiconductor device having a drift layer comprising parallel pn layers which depletes in OFF state while conducting current in ON state. SOLUTION: The impurity amount in an (n) drift region 12a is in the range of 100-150% or of 110-150% of the impurity amount in a (p) partitioning region. Or, the impurity concentration in either of the (n) drift region 12a or the (p) partitioning region 12b is in the range of 92-108% of the impurity concentration in the other region. Besides, width of the one is in the range of 94-106% of the width of the other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET (insulated gate type field effect transistor) and an IGBT (insulated gate bipolar transistor) each having a special structure including a parallel pn layer which is depleted in an off state while a current flows in an on state. Transistors), bipolar transistors, diodes and the like.

[0002]

2. Description of the Related Art In a vertical semiconductor device in which a current flows between electrodes provided on two opposing main surfaces, the thickness of a high resistance layer between the two electrodes is increased in order to increase the breakdown voltage. On the other hand, in an element having such a thick high-resistance layer, it is inevitable that the on-resistance between both electrodes is inevitably increased, and the loss is increased. That is, there is a trade-off relationship between the on-resistance (current capacity) and the withstand voltage. It is known that this trade-off relationship is similarly established in semiconductor devices such as IGBTs, bipolar transistors, and diodes. This problem is also common to a lateral semiconductor element in which the direction in which a drift current flows when turned on is different from the direction in which a depletion layer extends due to a reverse bias when turned off.

As a solution to this problem, the drift layer is constituted by a parallel pn layer in which an n-type region and a p-type region with an increased impurity concentration are alternately stacked. Semiconductor devices having a structure designed to bear the withstand voltage are disclosed in EP0053854, USP 5,216,275,
It is disclosed in US Pat. No. 5,438,215 and Japanese Patent Application Laid-Open No. 9-26631 by the inventors of the present invention.

[0004] The inventors of the present invention have called a semiconductor element having a drift layer composed of a parallel pn layer that is depleted in the off state while allowing current to flow in the on state, as a superjunction semiconductor element.

[0005]

However, none of the above-mentioned inventions has been considered for mass production at the trial stage. For example, the parallel pn layers have the same impurity concentration and the same width. However, variations always occur in the actual manufacturing process of the device.

[0006] Further, no specific numerical value relating to the L load avalanche breakdown current, which is important in mass production and commercialization, has not been specified so far. For commercialization, an L load avalanche breakdown current higher than the rated current is desired.

[0007] In view of such a situation, an object of the present invention is to clarify an allowable range of impurity concentration, width, and the like, thereby greatly improving a trade-off relationship between on-resistance and withstand voltage and improving high withstand voltage. It is an object of the present invention to provide a super-junction semiconductor device which is realized and suitable for mass production.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides first and second main surfaces, two main electrodes provided on the main surfaces, and an on-state between the main electrodes. In a super-junction semiconductor device including a parallel pn layer in which a first conductivity type drift region and a second conductivity type partition region that are depleted in an off state while flowing a current are provided, an impurity amount of the first conductivity type drift region Is within the range of 100 to 150% of the impurity amount of the second conductivity type partition region.

In particular, the amount of impurities in the drift region of the first conductivity type is 110 to 150% of the amount of impurities in the partition region of the second conductivity type.
Should be within the range.

[0010] It is effective that the first conductivity type drift region and the second conductivity type partition region are each in the form of stripes having substantially the same width.

[0011] Separately from this, the first and second main surfaces, two electrodes provided on the main surface, and between the main electrodes,
In a super-junction semiconductor device including a parallel pn layer in which a first conductivity type drift region and a second conductivity type partition region that flow current in an on state and are depleted in an off state are alternately arranged, the first conductivity type drift region It is assumed that the impurity amount of one of the partition region and the second conductive type partition region is in the range of 92 to 108% of the impurity amount of the other region.

In particular, the first conductivity type drift region and the second conductivity type partition region have substantially the same width, and the average impurity concentration in one of the regions is 92 to 108% of the average impurity concentration in the other region. And the impurity concentration of one of the first conductivity type drift region and the second conductivity type partition region is in the range of 92 to 108% of the impurity concentration of the other region. May be inside.

Further, the first conductivity type drift region and the second conductivity type partition region have substantially the same concentration, and the width of one of the regions is within the range of 94 to 106% of the width of the other region. There is.

In order to deplete the parallel pn layers in which the first conductivity type drift regions and the second conductivity type partition regions are alternately arranged in the off state, the impurity amounts in both regions must be substantially equal. is necessary. If one impurity concentration is half that of the other, the width must be doubled. Therefore, if both regions have the same impurity concentration,
Since the width is the same, it is the best in terms of the utilization efficiency of the semiconductor surface.

With the same impurity concentration and the same width, as described above, both regions are almost uniformly depleted, so that a decrease in breakdown voltage due to the remaining undepleted portion remains.
As described later, it is suppressed to about 10% of the ideal case.

As a manufacturing method, one of the first conductivity type drift region and the second conductivity type partition region has an impurity amount in the range of 92 to 108% of the impurity amount in the other region by epitaxial growth. Even if it is formed, the other region may be formed by thermal diffusion after introducing an impurity amount in the range of 92 to 108% of the impurity amount for forming one region.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The experiments performed for the present invention and the results thereof will be described below.

Embodiment 1 First, FIG. 3 is a partial cross-sectional view of a basic portion of a vertical n-channel super-junction MOSFET used in an experiment. In addition, a portion for maintaining the withstand voltage is provided mainly in the peripheral portion, and the portion is formed by a general method such as a guard ring structure. In the following, a layer or a region with an abbreviation of n or p means a layer or a region using electrons and holes as majority carriers, respectively. The suffix “ ^+” means a region with a relatively high impurity concentration, and the sign “−” means a region with a relatively low impurity concentration.

In FIG. 3, reference numeral 11 denotes a low-resistance n ⁺ drain layer, 12 denotes an n drift region 12a, and a p partition region 12.
b is a drift layer of a parallel pn layer composed of b. In the drift layer 12, the drift current flows in the n drift region 12a. Here, the parallel pn layer including the p partition region 12b is referred to as the drift layer 12. In the surface layer, an n-channel region 12d connected to the n-drift region 12a and a p-well region 13a connected to the p-partition region 12b are formed. p well region 13
An n ⁺ source region 14 and a high concentration p ⁺ contact region 13b are formed inside a. P well region 13a sandwiched between n ⁺ source region 14 and n drift region 12a
A gate electrode layer 16 of polycrystalline silicon via a gate insulating film 15 and a source electrode 17 which is in common contact with the surface of the n ⁺ source region 14 and the surface of the high concentration p ⁺ contact region 13b. Is provided. On the back surface of the n ⁺ drain layer 11, a drain electrode 18 is provided. 1
Reference numeral 9 denotes an insulating film for protecting and stabilizing the surface, and is made of, for example, a thermal oxide film and phosphor silica glass (PSG). The source electrode 17 is often extended on the gate electrode layer 16 via the insulating film 19 as shown in the figure. The alternate arrangement of the n-type divided region 1 and the p-type divided region 2 may be a stripe shape.
Another method in which one is in a lattice shape may be used. N drift region 12a is formed, for example, by epitaxial growth. The p partition region 12b is formed by filling a dug portion provided in the n drift region 12a by epitaxial growth. Regarding this manufacturing method, refer to Japanese Patent Application No. Hei 10-20
This is described in detail in No. 9267.

For example, as a 400V class MOSFET, the standard dimensions and impurity concentrations of the respective parts take the following values. The specific resistance of the n ⁺ drain layer 11 is 0.01
Ω · cm, thickness 350 μm, thickness 32 of drift layer 12
μm, n drift region 12a and p partition region 12b
8 μm (that is, 16 μm between centers of the same region)
m), the impurity concentration is 3.0 × 10 ¹⁵ cm ⁻³ , the diffusion depth of the p-well region 13 a is 3 μm, and the surface impurity concentration is 2 × 10 ¹⁷
cm ⁻³ , the diffusion depth of the n ⁺ source region 14 is 0.3 μm, and the surface impurity concentration is 3 × 10 ²⁰ cm ⁻³ .

For example, as an 800V class MOSFET, the standard dimensions and impurity concentrations of the respective parts take the following values. The specific resistance of the n ⁺ drain layer 11 is 0.01
Ω · cm, thickness 350 μm, thickness 48 of the drift layer 12
μm, n drift region 12a and p partition region 12b
5 μm (that is, 10 μm between centers of the same region)
m), an impurity concentration of 3.5 × 10 ¹⁵ cm ⁻³ , a diffusion depth of the p-well region 13 a of 1 μm, and a surface impurity concentration of 3 × 10 ¹⁸
cm ⁻³ , the diffusion depth of the n ⁺ source region 14 is 0.3 μm, and the surface impurity concentration is 1 × 10 ²⁰ cm ⁻³ .

The operation of the super-junction MOSFET shown in FIG. 3 is performed as follows. When a predetermined positive voltage is applied to gate electrode layer 16, an inversion layer is induced in the surface layer of p well region 13 a immediately below gate electrode layer 16, and is transferred from n ⁺ source region 14 to n channel region 13 d through the inversion layer. Electrons are injected. The injected electrons form the n drift region 12
a to reach the n ⁺ drain layer 11 and the drain electrode 1
8, conduction between the source electrodes 17 is established.

When the positive voltage is removed from the gate electrode layer 16, the inversion layer induced on the surface layer of the p-well region 13a disappears, and the drain electrode 18 and the source electrode 17 are cut off. When the reverse bias voltage is further increased, the p-partition regions 12b are connected to each other by the source electrode 17 via the p-well region 13a.
Depletion layers spread from the pn junction Ja between the N channel region 12d and the n drift region 12a and the p partition region 12b into the n drift region 12a and the p partition region 12b. Be transformed into

The depletion edge from the pn junction Jb extends in the width direction of the n drift region 12a, and the depletion layer extends from the p partition regions 12b on both sides, so that depletion is greatly accelerated. Therefore, the impurity concentration of n drift region 12a can be increased. The p partition region 12b is also depleted at the same time. Since the depletion layer also extends from the pn junctions on both sides of the p-partition region 12b, depletion is greatly accelerated. By forming the p-partition region 12b and the n-drift region 12a alternately, the depletion end enters both adjacent n-drift regions 12a, so that the p-partition region 12b for forming the depletion layer is formed. The total occupation width can be halved, and n
The cross-sectional area of drift region 12a can be increased. [Embodiment 2] The impurity amount (dose amount) of boron in the p partition region 12b is fixed at 1 × 10 ¹³ cm ^−2, and the impurity amount (dose amount) of phosphorus in the n drift region 12a is 80 to 150 with respect to this. % N-channel type MO
The SFET was simulated and prototyped and confirmed.

FIG. 5 is a characteristic diagram showing the dependence of the on-resistance (Ron · A) and the withstand voltage (V _DSS ) on the amount of impurities. The horizontal axis is the breakdown voltage (V _DSS ), and the vertical axis is the on-resistance (Ron · A).
It is. Impurity amount (dose amount) of p partition region 12b
Is fixed to 1 × 10 ¹³ cm ⁻² , the width is 8 μm,
The depth of the drift layer 12 was 32 μm.

For example, when the impurity amount of the n drift region 12a is 1.0 × 10 ¹³ cm ⁻² (100%), the generated breakdown voltage is 445 V and the on-resistance is 38 mΩ · cm ² .
If 1.3 × 10 ¹³ cm ^-2 (130%), the generated breakdown voltage is 3
At 65V, the ON resistance is 24 mΩ · cm ² , 1.5 × 10
^{If it is 13} cm ^-2 (150%), the generated breakdown voltage is 280 V, and the on-resistance drops to ²⁰ mΩ · cm ² .

From the figure, it can be seen that the impurity amount of the n drift region 12a is 100 to 1 with respect to the impurity amount of the p partition region 12b.
It can be seen that as the voltage increases to 50%, the on-resistance (Ron · A) decreases, although the withstand voltage (V _DSS ) decreases. Further, since the variation of the on-resistance (Ron · A) of each product in the range of 100 to 150% is small, it is only necessary to consider the variation of the generated withstand voltage in mass production, so that the production and the process management are easy. Becomes In this embodiment, the 400 V class is used, but the same can be said for any withstand voltage class.

[Embodiment 3] FIG. 6 is a characteristic diagram showing an impurity amount dependency of an L load avalanche breakdown current (A).
The horizontal axis represents the impurity amount (dose amount) of phosphorus in the n drift region 12a, and the vertical axis represents the L load avalanche breakdown current (A). The impurity amount (dose amount) of boron in the p partition region 12b is fixed at 1 × 10 ¹³ cm ^−2, and n
The impurity amount (dose amount) of phosphorus in drift region 12a is set to 8
It varied in the range of 0-150%. The setting conditions are the same as in the first embodiment.

For example, impurities in the n drift region 12a
1.0 × 10¹³cm^-2(100%) when Avalan
The shear breakdown current (A) is about 7 A, but 1.3 × 10¹³
cm^-2(130%), avalanche breakdown current (A)
Is about 63A, 1.5 × 10 ¹³cm^-2(150%)
And the avalanche breakdown current (A) is about 72A.

From the figure, when the L load avalanche breakdown current is required to be higher than the rated current, preferably more than twice,
The impurity amount (dose amount) of n drift region 12a is set to 11
It can be seen that the content should be set to 0% or more. Further, since the L load avalanche breakdown current at 140% or more tends to be saturated, it is preferable to be 150% or less in consideration of the decrease in the withstand voltage in FIG. The same can be said for the L load avalanche breakdown current in any withstand voltage class.

From the above experiment, the allowable range of the impurity amount of the n drift region 12a and the p partition region 12b of the parallel pn layer has been clarified. It is possible to easily mass-produce a high-breakdown-voltage super-junction semiconductor element that greatly guarantees the L-load avalanche destruction while significantly improving the trade-off relationship between the semiconductor device and the breakdown voltage. Simulating the n-channel type MOSFET by changing the impurity concentration C _P of Example 4] p partition regions 12b,
In addition, it was actually manufactured and confirmed.

[0032] Figure 1 is a characteristic diagram showing an impurity concentration C _P dependence of breakdown voltage (V _DSS). The horizontal axis is the p partition area 12b
Impurity concentration C _P of the vertical axis represents the breakdown voltage (V _DSS). The impurity concentration C _n of the n drift region 12a is 3.5 × 10 ¹⁵ cm
⁻³ , the width was 5 μm, and the depth of the drift layer 12 was 48 μm.

For example, C _n = C _P = 3.5 × 10 ¹⁵ cm ^-3
, The breakdown voltage reaches a maximum value of 960 V, but C _P = 3 × 1
With 0 ¹⁵ cm ^-3 , the withstand voltage is about 750 V and 2 × 10 ¹⁵ c
When it is set to m ^-3 , the voltage further decreases to about 380V.

This is because there is a portion in the n drift region 12a that cannot be sufficiently depleted. Conversely, when the impurity concentration of the p-partition region 12b is higher than that of the n-drift region 12a, a portion that cannot be sufficiently depleted is generated in the p-partition region 12b, and the breakdown voltage is also reduced.

[0035] From FIG., P impurity concentration C _P of the partition region 12b is, if with respect to the impurity concentration C _n of the n drift region 12a is within 8% above and below, a reduction in the breakdown voltage is found to live in 10% .

[0036] This embodiment is the case of changing the impurity concentration C _P of the p partition regions 12b, same is true of the case where naturally changed impurity concentration C _n of the n drift region 12a. The same can be said for the set withstand voltage in any withstand voltage class. [Example 5] Next, 5 width L _n in the n drift region 12a
and μm constant, n by changing the width L _P of p partition regions 12b
A channel-type MOSFET was simulated and actually manufactured and confirmed.

FIG. 1 is a characteristic diagram showing the dimensional dependence of the breakdown voltage (V _DSS ). The horizontal axis is the width L _P of the p partition region 12b, and the vertical axis is the breakdown voltage (V _DSS ). The impurity concentration is 3.5
X 10 ¹⁵ cm ^-3 and the drift layer 12 has a depth of 48
μm.

For example, when L _n = L _P = 5 μm, the withstand voltage reaches a maximum value of 960 V, but when L _P = 4 μm, the withstand voltage decreases to about 550 V.

This is because there is a portion in the n drift region 12a that cannot be sufficiently depleted. Conversely, when the p partition region 12b is made thicker than the n drift region 12a,
A portion that cannot be fully depleted is generated in the p partition region 12b, and the breakdown voltage is also reduced.

[0040] from the figure, the width L _P of the p partition regions 12b is,
If the width L _n in the n drift region 12a is within 6% above and below, a reduction in the breakdown voltage is found to be need about 10%.

In this embodiment, the width L of the p partition region 12b is
It is a case of changing the _P, same is true of the case where naturally changed width L _n in the n drift region 12a. The same can be said for the set withstand voltage in any withstand voltage class.

The above experiments have clarified the allowable ranges of the impurity concentration and dimensions of the n drift region 12a and the p partition region 12b of the parallel pn layer. Based on this, it is possible to design a super junction semiconductor device. In addition, it is possible to easily mass-produce a high-breakdown-voltage super junction semiconductor element while significantly improving the trade-off relationship between the on-resistance and the breakdown voltage. [Embodiment 6] As another manufacturing method, a step of epitaxially growing a high-resistance layer is repeated several times after partially forming a buried region of an impurity before epitaxial growth, and then diffused by heat treatment to form a parallel structure. A pn layer can also be formed.

FIG. 4 shows a vertical type n manufactured by such a method.
FIG. 3 is a partial cross-sectional view of a basic portion of a channel type super junction MOSFET.

Although not much different from the cross-sectional view of the super-junction MOSFET of FIG. 3, the n drift region 22a and the p partition region 2
The difference is that 2b is not a uniform impurity concentration but has an impurity concentration distribution inside. For the sake of simplicity, the dotted lines show lines with the same impurity concentration. Lines having the same impurity concentration are curves (three-dimensionally curved surfaces). This is because the step of epitaxially growing the high-resistance layer is repeated several times after forming the buried region of the impurity, and then buried by the heat treatment and diffused from the impurity source.
After a sufficient diffusion time, the boundary between the n drift region 22a and the p partition region 22b becomes a straight line (three-dimensionally flat) as shown.

In such a case, n drift region 22
In order to prevent the a and p partition regions 22b from having a portion that cannot be fully depleted, it is important that the impurity amounts buried in both regions are substantially equal.

In particular, as described above, when the widths of the n drift region 22a and the p partition region 22b are equal, the utilization rate of the semiconductor crystal plane increases, so that the average of the n drift region 22a and the p partition region 22b is increased. It is important that the impurity concentrations are approximately equal.

In this case, the impurity amount of one of the first conductivity type drift region and the second conductivity type partition region is the same as that of the third embodiment. If it is in the range of 92 to 108%, the decrease in withstand voltage can be suppressed to about 10%.

If the widths are equal, the average impurity concentration of one of the first conductivity type drift region and the second conductivity type partition region is 92 to 1 of the average impurity concentration of the other region.
It suffices to be within the range of 08%.

Further, the allowable range of the width of the n drift region 22a and the p partition region 22b may be within the range of 94 to 106%.

If the widths of the n drift region 12a and the p partition region 12b are reduced and the impurity concentration is increased,
It is possible to further reduce the on-resistance and improve the trade-off relationship between the on-resistance and the withstand voltage.

Although the embodiment has been described with reference to an example of a vertical MOSFET, this problem is caused by a lateral semiconductor element in which the direction in which a drift current flows during ON and the direction in which a depletion layer extends due to a reverse bias during OFF are different. Is also common. Further, the same effect can be obtained with IGBTs, pn diodes, Schottky barrier diodes, and bipolar transistors.

[0052]

As described above, the present invention relates to a parallel pn layer in which a first conductivity type drift region and a second conductivity type partition region, which flow a current in an on state and are depleted in an off state, are alternately arranged. In the super-junction semiconductor device comprising: the allowable range of the on-resistance and the withstand voltage is determined by clarifying the allowable range such as the impurity concentration and the size between the first conductivity type drift region and the second conductivity type partition region of the parallel pn layer. While significantly improving the trade-off relationship, the L load avalanche destruction is further guaranteed, and mass production of a high breakdown voltage super junction semiconductor device is facilitated.

[Brief description of the drawings]

FIG. 1 shows a breakdown voltage (V) of a super junction MOSFET of the present invention.
Characteristic diagram showing the L _P width dependence of _DSS)

[Figure 2] characteristic diagram showing an impurity concentration C _P dependence of breakdown voltage (V _DSS)

FIG. 3 is a partial cross-sectional view of a basic structure of the super junction MOSFET according to the first embodiment.

FIG. 4 is a partial cross-sectional view of a basic structure of a super-junction MOSFET according to a second embodiment.

FIG. 5 shows the on-resistance of the super-junction MOSFET of the present invention.
(Ron · A) and the withstand voltage (V_{DS S})
Characteristic diagram shown

FIG. 6 is a characteristic diagram showing an impurity amount dependency of an L-load avalanche breakdown current (A).

[Explanation of symbols]

11, 21 n ⁺ drain layer 12, 22 drift layer 12a, 22an n drift region 12b, 22b p partition region 13a, 23a p well region 13b, 23b p ⁺ contact region 14, 24 n ⁺ source region 15 gate insulating film 16 gate Electrode layer 17 Source electrode 18 Drain electrode 19 Insulating film

Continued on the front page (72) Inventor Yasuhiko Onishi 1-1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Katsunori Ueno 1-1-1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji Inside Electric Machinery Company (72) Inventor Susumu Iwamoto 1-1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture

Claims (10)

[Claims] 1. A first conductivity type in which current flows in an on state and depletes in an off state between a first and a second main surface, two main electrodes provided on the main surface, and the main electrodes. Parallel p in which drift regions and second conductivity type partition regions are alternately arranged
A super-junction semiconductor device comprising an n-layer, wherein the amount of impurities in the drift region of the first conductivity type is in the range of 100 to 150% of the amount of impurities in the partition region of the second conductivity type. 2. A first conductivity type in which current flows in an on state and depletes in an off state between a first and a second main surface, two main electrodes provided on the main surface, and the main electrodes. Parallel p in which drift regions and second conductivity type partition regions are alternately arranged
1. A super-junction semiconductor device comprising an n-layer, wherein the amount of impurities in the drift region of the first conductivity type is in the range of 110 to 150% of the amount of impurities in the partition region of the second conductivity type. 3. A first conductivity type in which current flows in an on state and depletes in an off state between a first and a second main surface, two main electrodes provided on the main surface, and the main electrodes. Parallel p in which drift regions and second conductivity type partition regions are alternately arranged
In a superjunction semiconductor device having an n-layer, the impurity amount in one of the first conductivity type drift region and the second conductivity type partition region is 92 to 108% of the impurity amount in the other region.
A super-junction semiconductor device, wherein 4. The super-junction semiconductor device according to claim 1, wherein each of the first conductivity type drift region and the second conductivity type partition region has a stripe shape. 5. A first conductivity type in which current flows in an on state and depletes in an off state between a first and a second main surface, two main electrodes provided on the main surface, and the main electrodes. Parallel p in which drift regions and second conductivity type partition regions are alternately arranged
In the super-junction semiconductor device having the n-layer, the first conductivity type drift region and the second conductivity type partition region are substantially the same width, and one of the first conductivity type drift region and the second conductivity type partition region Wherein the average impurity concentration of the region is in the range of 92 to 108% of the average impurity concentration of the other region. 6. A first conductivity type in which a current flows in an on state and depletes in an off state between a first and a second main surface, two main electrodes provided on the main surface, and the main electrode. Parallel p in which drift regions and second conductivity type partition regions are alternately arranged
In the super-junction semiconductor device having the n-layer, the first conductivity type drift region and the second conductivity type partition region are substantially the same width, and one of the first conductivity type drift region and the second conductivity type partition region Wherein the impurity concentration of the region is in the range of 92 to 108% of the impurity concentration of the other region. 7. A first conductivity type in which current flows in an on state and depletes in an off state between a first and second main surface, two main electrodes provided on the main surface, and the main electrode. Parallel p in which drift regions and second conductivity type partition regions are alternately arranged
In the super-junction semiconductor device including the n-layer, the first conductivity type drift region and the second conductivity type partition region have substantially the same concentration, respectively, and one of the first conductivity type drift region and the second conductivity type partition region Wherein the width of the region is in the range of 94 to 106% of the width of the other region. 8. A super-junction semiconductor device according to claim 1, wherein two main electrodes are provided on the first and second main surfaces, respectively. 9. A first conductive material, comprising: a first main surface, a second main electrode provided on the main surface, and a current flowing between the main electrodes in an on state and being depleted in an off state. A method of manufacturing a super junction semiconductor device including a parallel pn layer in which a mold drift region and a second conductivity type partition region are alternately arranged, wherein one of the first conductivity type drift region and the second conductivity type partition region is provided. A method for manufacturing a super-junction semiconductor device, characterized in that the other region having an impurity amount within the range of 92 to 108% of the impurity amount of the region is formed by epitaxial growth. 10. A first conductive material, comprising: a first main surface, a second main electrode provided on the main surface, and a current flowing between the main electrodes in an on state and depletion in an off state. A method of manufacturing a super junction semiconductor device including a parallel pn layer in which a mold drift region and a second conductivity type partition region are alternately arranged, wherein one of the first conductivity type drift region and the second conductivity type partition region is provided. 92 to 1 of an impurity amount for forming a region
A method for manufacturing a super junction semiconductor device, comprising: introducing an impurity amount in a range of 08%, and then forming the other region by thermal diffusion.