JP2015170698A - Semiconductor device and manufacturing method and inspection method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which stably and simply measures a charge imbalance amount during a manufacturing process to enable manufacturing of a semiconductor device having a super junction structure where charge balance is ensured; and provide a manufacturing method and an inspection method of the semiconductor device.SOLUTION: In a semiconductor device, by measuring capacitance-voltage characteristics of a column layer for inspection formed simultaneously with a column layer of the semiconductor device, quality is determined such that whether a charge imbalance amount is within an allowable range, or whether an impurity concentration of the semiconductor column is within an allowable range.

Description

  The present invention relates to a semiconductor device having a super junction structure, a manufacturing method thereof, and an inspection method, and more particularly to a semiconductor device capable of measuring a charge unbalance amount of a semiconductor device in the course of a manufacturing process, and a manufacturing method and an inspection method thereof. .

When manufacturing a semiconductor device having a general super junction structure, for example, a semiconductor substrate in which an n ⁻ type layer is epitaxially grown on the surface of an n ⁺ type silicon substrate is prepared, and a trench groove is formed in the n ⁻ type layer. The p ⁻ type layer is epitaxially grown in the trench, thereby forming an n type column layer made of an n ⁻ type layer and a p type column layer made of a p ⁻ type layer.

  Here, by matching the charge amount of the n-type column layer and the charge amount of the p-type column layer, the charge is canceled when the semiconductor device is turned off, the depletion layer expands as if it has no charge, and the withstand voltage is increased. Can be obtained.

  However, due to processing variations in forming the n-type column layer and the p-type column layer, a difference (hereinafter, charge imbalance amount) occurs between the charge amount of the n-type column layer and the charge amount of the p-type column layer. If this amount of charge imbalance is large, the electric charge that remains without being canceled will generate an electric field in the super junction structure, making it impossible to obtain a desired breakdown voltage.

As a method for solving such a problem, a current drop flowing in the n-type column layer and a voltage drop when a forward voltage is applied to a diode formed by the p-type column layer and the n ⁺ -type silicon substrate (hereinafter, p Type column layer / n-type substrate diode forward voltage) to determine the amount of charge imbalance and to compensate for the amount of charge imbalance in the n-type column layer and / or p-type column layer It has been proposed to add (Patent Document 1). According to this proposal, a semiconductor device having a super junction structure in which charge balance is ensured can be manufactured.

JP 2007-251023 A

However, in the method of manufacturing a semiconductor device disclosed in Patent Document 1, the n-type column layer is used to measure the current flowing in the n-type column layer and the forward voltage of the p-type column layer / n-type substrate diode. It is necessary to form ohmic contacts on the p-type column layer and the n ⁺ -type silicon substrate.

Usually, the back surface of the n ⁺ -type silicon substrate is covered with an oxide film to prevent autodoping. Therefore, in the method of manufacturing a semiconductor device disclosed in Patent Document 1, an n ⁺ type silicon substrate is used to measure the current flowing in the n type column layer and the forward voltage of the p type column layer / n type substrate diode. It is necessary to remove the oxide film on the back surface.

By the way, a wafer from which the back oxide film has been removed for the measurement as described above cannot prevent the impurities in the n ⁺ type silicon substrate from diffusing into the semiconductor manufacturing apparatus, and this wafer becomes a contamination source and adversely affects other wafers. In the semiconductor device manufacturing factory, the subsequent processes do not flow.

In addition, since the width of the n-type column layer and the p-type column layer is about several μm and the impurity concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ , an ohmic contact should be formed on each surface. However, since fine patterning is required and the impurity concentration is low, it is difficult to form an ohmic contact.

  Thus, measuring the amount of charge imbalance by measuring the current flowing in the n-type column layer and the forward voltage of the p-type column layer / n-type base layer diode is a manufacturing process for mass-producing semiconductor devices. However, it has been necessary to determine whether the product is good or defective by a characteristic test after the semiconductor device is completed.

  The present invention solves the above problems, and can stably and easily measure the amount of charge imbalance during the manufacturing process, and can manufacture a semiconductor device having a super junction structure in which charge balance is ensured. It aims at providing the manufacturing method and the inspection method.

  In order to achieve the above object, an invention according to claim 1 of the present application has a super junction structure in which first conductive type first semiconductor column layers and second conductive type second semiconductor column layers are alternately arranged. A semiconductor device forming region including the first semiconductor column layer and the second semiconductor column layer; a first conductivity type first test semiconductor column layer; and a second conductivity type second test semiconductor column. A test pattern region including a first semiconductor column layer formed simultaneously with the first semiconductor column layer and a second semiconductor column layer formed simultaneously with the first semiconductor column layer. A test pattern having a super junction structure in which the second test semiconductor column layers are alternately and repeatedly arranged; A test pattern comprising the first test semiconductor column layer having the same width as the first semiconductor column layer and the second test semiconductor column layer having the same width as the second semiconductor column layer, or the first semiconductor column layer And a plurality of test patterns comprising the first test semiconductor column layer and the second test semiconductor column layer having different widths at least one of the second semiconductor column layers, and each of the test patterns It is characterized in that a connection portion capable of measuring a capacitance value between the first test semiconductor column layer and the second test semiconductor column layer is provided.

  The invention according to claim 2 of the present application is a method of manufacturing a semiconductor device having a super junction structure in which a first semiconductor column layer of a first conductivity type and a second semiconductor column layer of a second conductivity type are alternately arranged. Forming a first conductivity type first test semiconductor column layer simultaneously with the first semiconductor column layer, and forming a second conductivity type second test semiconductor column layer simultaneously with the second semiconductor column layer; Forming a test pattern having a super junction structure in which the first test semiconductor column layer and the second test semiconductor column layer are alternately and repeatedly arranged; and the second semiconductor column layer and the second test After forming the test column layer, the space between the first test semiconductor column layer and the second test semiconductor column layer for each of the test patterns. Measuring the value, wherein the test pattern is the second test semiconductor having the same width as the first semiconductor column layer and the second semiconductor column layer having the same width as the first semiconductor column layer. A test pattern comprising a column layer, or the first test semiconductor column layer and the second test semiconductor column in which at least one of the first semiconductor column layer and the second semiconductor column layer has a different width. It is characterized in that it is formed so as to include a plurality of sets of test patterns composed of layers.

  The invention according to claim 3 of the present application is a semiconductor device having a super junction structure in which a first conductivity type first semiconductor column layer and a second conductivity type second semiconductor column layer are alternately and repeatedly arranged. The first conductivity type first test semiconductor column layer formed simultaneously with the first semiconductor column layer and the second conductivity type second test semiconductor column layer formed simultaneously with the second semiconductor column layer are alternately arranged. The test pattern having the same width as the first semiconductor column layer and the second semiconductor column layer having the same width as the first semiconductor column layer is provided. A test pattern comprising a second test semiconductor column layer, or at least one of the first semiconductor column layer and the second semiconductor column layer A plurality of test patterns each including a first test semiconductor column layer and a second test semiconductor column layer having a width different from a width; the first test semiconductor column layer and the second test pattern for each test pattern; In a method for inspecting a semiconductor device having a connection portion capable of measuring a capacitance value between two test semiconductor column layers, the first test semiconductor column layer and the second test are provided for each test pattern. It is characterized by determining whether or not the charge unbalance amount is within an allowable range by measuring capacitance-voltage characteristics between the semiconductor column layer and the semiconductor column layer, and determining whether the semiconductor device is good or bad.

  According to a fourth aspect of the present invention, in the semiconductor device inspection method according to the third aspect, at least one of the first semiconductor column layer and the second semiconductor column layer is measured by measuring the capacitance-voltage characteristic. It is characterized in that it is determined whether or not the impurity concentration of the semiconductor device is within an allowable range and the quality of the semiconductor device is determined.

  According to the semiconductor device and the manufacturing method thereof of the present invention, the first test semiconductor column layer and the second test of each of the plurality of sets of test patterns immediately after the manufacture of the second semiconductor column layer and the second test semiconductor column layer. It is possible to determine whether or not the charge imbalance amount is within an allowable range from the capacitance-voltage measurement between the semiconductor column layer and the semiconductor column layer. Therefore, if it is determined that the product is defective, it is not necessary to perform subsequent manufacturing. If it is determined that the product is a non-defective product, the oxide film formed on the back surface of the semiconductor substrate is not removed, so that the manufacturing process of the semiconductor device can be continued and the manufacturing cost of the semiconductor device can be reduced. Further, this capacitance-voltage measurement is a very simple method without requiring any special processing for measurement.

  According to the semiconductor device inspection method of the present invention, a plurality of test patterns having a super junction structure in which the widths of the first test semiconductor column layer and the second test semiconductor column layer are changed are formed, and the capacitance-voltage characteristics are improved. By measuring, it is possible to calculate the presence / absence of charge imbalance, the width of the semiconductor column layer for eliminating the charge imbalance, the impurity concentration, etc., which is very useful for improving the yield of the semiconductor device. .

  In particular, the sum of the width of the first semiconductor column layer and the width of the second semiconductor column layer, and the sum of the width of the first test semiconductor column layer and the width of the second test semiconductor column layer are configured to be constant. This is effective because the width of the first semiconductor column layer and the second semiconductor column layer at which the charge imbalance amount becomes zero can be easily specified.

It is a figure explaining the manufacturing method of MOSFET of the super junction structure of the Example of this invention. It is a figure explaining the manufacturing method of MOSFET of the super junction structure of the Example of this invention. It is explanatory drawing of MOSFET of a super junction structure. It is explanatory drawing of the wafer of the Example of this invention. It is sectional drawing which showed the expansion of the depletion layer at the time of applying a reverse bias. It is a figure which shows the capacity | capacitance-voltage characteristic of the Example of this invention. It is a figure explaining the expansion of a depletion layer when the electric charge amount of a p-type column layer is smaller than the electric charge amount of an n-type column layer. It is a figure explaining the expansion of a depletion layer when the electric charge amount of a p-type column layer is larger than the electric charge amount of an n-type column layer. It is a figure which shows the relationship between the width | variety of a p-type column layer, and the voltage Vdep. It is explanatory drawing of a test pattern. It is a figure which shows the relationship between n type column width and voltage Vdep in case the sum of n column width and p column width is constant.

  An embodiment of the present invention will be described in detail by taking a manufacturing process of a MOSFET having a super junction structure as an example.

FIG. 1 and FIG. 2 are diagrams for explaining a manufacturing process of one test pattern formed on the same wafer as a MOSFET having a super junction structure, a left figure shows a MOSFET and a right figure shows a manufacturing process of the test pattern. . First, a semiconductor substrate in which an n ⁻ type semiconductor layer 2 is epitaxially grown on an n ⁺ type silicon substrate 1 is prepared. An oxide film 3 is formed on the back side of the semiconductor substrate to suppress outward diffusion (FIG. 1a).

Next, an oxide film 4 is formed on the surface of the n ⁻ type semiconductor layer 2 by, for example, a wet oxidation method, a dry oxidation method, a CVD method, or the like. Thereafter, the photoresist 5 is patterned so that a region where a trench is to be formed is opened, and the oxide film 4 is etched away using the photoresist 5 as an etching mask to expose the surface of the n ⁻ type semiconductor layer 2 (FIG. 1b). . Here, when forming the test pattern, a plurality of test patterns having different opening widths are formed. As an example, a plurality of combinations of test patterns are prepared so that the sum of the opening width formed by etching and the width of the oxide film 4 remaining without etching is constant. In this case, the sum of the opening width of the MOSFET and the width of the oxide film 4 is preferably matched.

Thereafter, the n ⁻ type semiconductor layer 2 exposed using the oxide film 4 as an etching mask is subjected to anisotropic etching by the RIE method or the like to form a plurality of stripe-shaped trench grooves 6 (FIG. 1c). The n ⁻ type semiconductor layer 2 remaining in the stripe form constitutes an n type column layer 7 (corresponding to a first semiconductor column layer) of the MOSFET. Further, an n-type column layer 7T (corresponding to a first test semiconductor column layer) of a test pattern is formed.

A part of the oxide film 4 in the vicinity of the trench 6 is removed by etching (FIG. 2a). Thereafter, a p ⁻ type epitaxial layer is grown so as to fill the trench groove 6. The p ⁻ type epitaxial film embedded in the trench 6 constitutes the p type column layer 8 (corresponding to the second semiconductor column layer) of the MOSFET. In addition, a p-type column layer 8T (corresponding to a second test semiconductor column layer) of a test pattern is formed. When the p ⁻ type epitaxial film is grown, over-epitaxial growth is performed so that each trench groove 6 is completely filled. Therefore, as shown in FIG. 2B, 1 to 10 μm is formed on the main surface of the semiconductor substrate. the extent of p ^- would type epitaxial film is formed. In addition, when epitaxial growth is performed, by flowing a mixed gas of a silicon source gas and a halide, epitaxial growth of silicon on the oxide film 4 can be suppressed.

Next, in order to measure the charge imbalance amount, capacitance-voltage characteristics between the n-type column 7T and the p-type column 8T of a plurality of test patterns with different column widths are measured (FIG. 2b). Details of the capacitance-voltage measurement will be described later. Here, the over-epitaxially grown p ⁻ -type epitaxial film and the oxide film 3 serve as a connection portion when the capacitance is measured.

  According to this capacitance-voltage measurement, if the amount of charge imbalance of the MOSFET greatly exceeds the allowable value, it is determined as defective. In addition, the width of the column layer, the impurity concentration, etc. for making the charge imbalance amount within the allowable range can be calculated. When the charge imbalance amount is zero or within the allowable range, it can be determined that the manufacturing is continued, and the process proceeds to the next step.

By removing and planarizing the p ⁻ type epitaxial film 7 formed on the main surface of the semiconductor substrate, an n type column layer 7 and a p type column layer 8 constituting a super junction structure are formed (FIG. 2c). ). Thereafter, a p-type epitaxial film 10 is formed on the main surface of the semiconductor substrate, and after performing a normal semiconductor manufacturing process or the like, a trench gate type MOSFET semiconductor device having a super junction structure shown in FIG. 3 is formed. In FIG. 3, 11 is a p-type body region, 12 is an n-type source region, 13 is a gate oxide film, 14 is a gate electrode, 15 is a source electrode, and 16 is a drain electrode.

  Next, the test pattern will be described in detail. The test pattern is formed on a part of the wafer on which the MOSFET is formed. FIG. 4 shows an example. The test pattern is formed on a part of the wafer (a region surrounded by a broken circle in the center in FIG. 4). A region 17 is formed, and a semiconductor device forming region 18 is formed in other regions. A plurality of test patterns are formed in the test pattern region 17, and a combination of test patterns in which the width dimensions of the n-type column layer 7T and the p-type column layer 8T are changed is formed.

  Next, measurement of capacitance-voltage characteristics for measuring the charge imbalance amount will be described. In measuring the capacitance-voltage characteristics of the test pattern of the super junction structure, the capacitance formed by the oxide film 3 on the back side of the semiconductor substrate is sufficiently larger than the capacitance of the test pattern. Therefore, it is not necessary to remove the oxide film 3 in measuring the capacitance-voltage characteristics of the test pattern. The capacitance-voltage characteristic is measured using a prober having a general stage.

  When a reverse bias is applied between the n-type column layer 7T and the p-type column layer 8T of the test pattern shown in the right figure of FIG. 2 (b), as shown schematically in FIG. 5 (a), the n-type column layer A depletion layer spreads from the pn junction interface of 7T and p-type column layer 8T. The broken line represents the tip of the depletion layer extending into the p-type column layer 8T and the tip of the depletion layer extending into the n-type column layer 7T. When the reverse bias is further applied, the depletion layer is connected to the adjacent depletion layer, and the entire column layer is depleted. FIG. 5B shows that when the charge amount of the n-type column layer 7T and the charge amount of the p-type column layer 8T are the same, the depletion layer extending into the n-type column layer and the p-type column layer is simultaneously formed in the lateral direction. Is depleted.

  The capacity-voltage characteristic in this case is shown by a solid line in FIG. It can be seen that the capacitance value sharply decreases at the voltage Vdep at which the n-type column layer and the p-type column layer are depleted in the horizontal direction.

  On the other hand, when the charge amount Qn of the n-type column layer 7T and the charge amount Qp of the p-type column layer 8T are different, one of the column layers having the smaller charge amount is first depleted in the lateral direction first. FIG. 7 shows a case where the charge amount Qp of the p-type column layer 8T is smaller than the charge amount Qn of the n-type column layer 7T. FIG. 8 shows a case where the charge amount Qp of the p-type column layer is larger than the charge amount Qn of the n-type column layer. In any case, the voltage Vdep at which the capacitance value rapidly decreases depends on the charge amount of one of the columns having a small charge amount. As shown by the broken line in FIG. 6, the charge amount Qn of the n-type column layer is The charge amount Qp of the p-type column layer is reduced as compared with the case where the charge amount Qp is the same.

  Therefore, in the test pattern of the present invention, for example, the width of the n-type column layer 7T is constant (the same as the width of the n-type column layer of the MOSFET) and the width of the p-type column layer is changed (for example, the p-type of the MOSFET). A plurality of widths that are the same width as the column layer and narrower and wider than this are prepared, the capacitance-voltage characteristics of each test pattern are measured, and the voltage Vdep at which the capacitance value rapidly decreases is measured. As a result, as shown in FIG. 9, the voltage Vdep increases as the width of the p-type column layer increases, and the width of the p-type column where the charge amount of the p-type column layer and the charge amount of the n-type column layer are the same ( Saturates at Wpcb). When the width of the p-type column layer is larger than that, the charge amount of the n-type column layer is smaller than the charge amount of the p-type column layer, and the voltage Vdep at which the capacitance value rapidly decreases is the charge amount of the n-type column layer. That is, it is determined by the width of the n-type column layer.

  Similarly, in the test pattern, when the width of the p-type column layer is constant and the width of the n-type column layer is changed, the voltage Vdep at which the capacitance value rapidly decreases increases as the width of the n-type column layer increases. The n-type column layer is saturated with the width of the n-type column layer where the charge amount of the n-type column layer is the same as that of the p-type column layer.

  In addition, not only when the width of the n-type column layer or the width of the p-type column layer is fixed, even if the widths of both column layers are changed, A width in which the charge amount of the n-type column layer and the charge amount of the p-type column layer are equal can be detected.

  In a test pattern in which the charge amount of the p-type column and the charge amount of the n-type column are the same, the following equation holds.

  Wncb · Dn · Ln = Wpcb · Dp · Lp (1)

  Here, Wncb and Wpcb are the widths of the n-type column layer and the p-type column layer, Dn and Dp are the impurity concentrations of the n-type column layer and the p-type column layer, respectively, and Ln and Lp are the n-type column layer and the p-type, respectively. This is the depth of the column layer, and Ln = Lp = L.

  Once the width of the n-type column and the p-type column of the test pattern in which the charge amount of the p-type column layer and the charge amount of the n-type column layer are the same, that is, the charge unbalance amount is zero, the semiconductor device is obtained from the following equation The charge unbalance amount Q per unit length in the depth direction per column layer is obtained.

  Here, Wn and Wp are the widths of the n-type column layer and the p-type column layer of the semiconductor device, respectively, and ΔWn is the difference between the width of the n-type column layer of the test pattern and the width of the n-type column layer of the semiconductor device, and ΔWp Is the difference between the width of the p-type column layer of the test pattern and the width of the p-type column layer of the semiconductor device.

  In a semiconductor device, for example, in order to secure the charge balance by adjusting the impurity concentration of the p-type column layer, the impurity concentration of the p-type column layer is corrected to Dpa in the subsequent manufacturing process so that the formula (3) is satisfied. do it.

  That is, as shown in the equation (4), the p-type column layer manufacturing conditions may be adjusted so that the impurity concentration of the p-type column layer is (1 + ΔWn / Wp · Wpcb / Wncb + ΔWp / Wp) times Dp. I understand that.

  In a plurality of test patterns, as shown in FIG. 10, if the sum of the width of the n-type column layer and the width of the p-type column layer is constant, the test patterns other than the dimension to be charge-balanced are always n-type. The charge amount of one column of either the column layer or the p-type column layer is larger than the charge amount to be charge balanced, and the charge amount of the other column is smaller than the charge amount to be charge balanced. Therefore, as shown in FIG. 11, the voltage at which the capacitance value rapidly decreases is maximum when the charge unbalance amount is zero, and is low in other cases, and is n in the test pattern where the charge unbalance amount is zero. The width of the mold column layer and the width of the p-type column layer can be easily determined.

  In addition, although the example of the column width of five test patterns is described in FIG. 10, the plurality of test patterns is not limited to five, and is necessary for detecting a test pattern in which the charge unbalance amount is zero. The column width and number may be set as appropriate.

  The inspection method described above can be used not only for determining the design rules of a semiconductor device at the prototype stage of the semiconductor device, but also for process management at the mass production stage.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to the said Example. For example, although the first conductivity type has been described as n-type and the second conductivity type as p-type, the first conductivity type may be p-type and the second conductivity type may be n-type. Further, the present invention is not limited to MOSFETs, and can be applied to all devices having a super junction structure such as an IGBT having a super junction structure.

1: n ⁺ type silicon substrate, 2: n ⁻ type semiconductor layer, 3: oxide film, 4: oxide film, 5: photoresist, 6: trench groove, 7: n-type column layer, 8: p-type column layer, 9: capacitance meter, 10: p-type epitaxial layer, 11: p-type body region, 12: n-type source region, 13: gate oxide film, 14: gate electrode, 15: source electrode, 16: drain electrode, 17: test Pattern region, 18: Semiconductor device formation region

Claims (4)

In a semiconductor device having a super junction structure in which a first semiconductor column layer of a first conductivity type and a second semiconductor column layer of a second conductivity type are alternately arranged,
A semiconductor device forming region including the first semiconductor column layer and the second semiconductor column layer, a test including a first conductivity type first test semiconductor column layer and a second conductivity type second test semiconductor column layer. Pattern area,
In the test pattern region, the first test semiconductor column layer formed simultaneously with the first semiconductor column layer and the second test semiconductor column layer formed simultaneously with the second semiconductor column layer are alternately arranged. It has a test pattern with a super junction structure that is repeatedly arranged in
The test pattern includes a test pattern including the first test semiconductor column layer having the same width as the first semiconductor column layer and the second test semiconductor column layer having the same width as the second semiconductor column layer, or A plurality of sets of test patterns each including the first test semiconductor column layer and the second test semiconductor column layer having different widths of at least one of the first semiconductor column layer and the second semiconductor column layer; ,
A semiconductor device comprising a connection portion capable of measuring a capacitance value between the first test semiconductor column layer and the second test semiconductor column layer for each of the test patterns. In a method for manufacturing a semiconductor device having a super junction structure in which a first semiconductor column layer of a first conductivity type and a second semiconductor column layer of a second conductivity type are alternately and repeatedly arranged,
Forming a first conductivity type first test semiconductor column layer simultaneously with the first semiconductor column layer, and forming a second conductivity type second test semiconductor column layer simultaneously with the second semiconductor column layer; Forming a test pattern of a super junction structure in which the first test semiconductor column layer and the second test semiconductor column layer are alternately and repeatedly arranged;
After forming the second semiconductor column layer and the second test column layer, a capacitance value between the first test semiconductor column layer and the second test semiconductor column layer is measured for each test pattern. Including the steps of:
The test pattern includes a test pattern including the first test semiconductor column layer having the same width as the first semiconductor column layer and the second test semiconductor column layer having the same width as the second semiconductor column layer, or A plurality of sets of test patterns each including the first test semiconductor column layer and the second test semiconductor column layer having different widths at least one of the first semiconductor column layer and the second semiconductor column layer are included. A method for manufacturing a semiconductor device, characterized by comprising: A semiconductor device having a super junction structure in which a first semiconductor column layer of a first conductivity type and a second semiconductor column layer of a second conductivity type are alternately arranged,
A first conductivity type first test semiconductor column layer formed simultaneously with the first semiconductor column layer; and a second conductivity type second test semiconductor column layer formed simultaneously with the second semiconductor column layer. It has a super junction structure test pattern that is alternately and repeatedly arranged.
The test pattern includes a test pattern including the first test semiconductor column layer having the same width as the first semiconductor column layer and the second test semiconductor column layer having the same width as the second semiconductor column layer, or A plurality of sets of test patterns each including the first test semiconductor column layer and the second test semiconductor column layer having a width different from at least one of the first semiconductor column layer and the second semiconductor column layer; ,
In the method for inspecting a semiconductor device including a connection portion capable of measuring a capacitance value between the first test semiconductor column layer and the second test semiconductor column layer for each of the test patterns,
Whether or not the charge unbalance amount is within an allowable range by measuring the capacitance-voltage characteristic between the first test semiconductor column layer and the second test semiconductor column layer for each of the test patterns. And determining whether the semiconductor device is good or bad. In the inspection method of the semiconductor device according to claim 3,
By measuring the capacitance-voltage characteristic, it is determined whether or not the impurity concentration of at least one of the first semiconductor column layer or the second semiconductor column layer is within an allowable range. A method for inspecting a semiconductor device, comprising:

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