JP2006313892A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a high breakdown voltage and high avalanche resistance. <P>SOLUTION: An MOSFET is formed which has a trench gate type gate structure on a p-type base layer 3 formed on a superjunction structure comprising an n-type pillar layer 5 and a p-type pillar layer 2 arranged alternately. The superjunction structure is formed not only in a device region, but also in an end region surrounding it. The width Wn1 [um] of the n-type pillar layer 5 and the width Wp1 [um] of the p-type pillar layer 2 in the device region, and the width Wn2 [um] of the n-type pillar layer 5 and the width Wp2 [um] of the p-type pillar layer 2 in the end region meet the relationship of Wp1/Wn1<Wp2/Wn2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a structure called a super junction structure.

  The on-resistance of the vertical power MOSFET greatly depends on the electric resistance of the conductive layer (drift layer) portion. The electrical resistance of the drift layer is determined by the impurity concentration. If the impurity concentration is increased, the on-resistance can be lowered. However, since the breakdown voltage of the PN junction formed by the drift layer and the base layer decreases as the impurity concentration increases, the impurity concentration cannot be increased beyond the limit determined according to the breakdown voltage. Thus, there is a trade-off relationship between element breakdown voltage and on-resistance. Improving this trade-off is an important issue when trying to provide a power semiconductor device with low power consumption. This trade-off has a limit determined by the element material, and exceeding this limit is the way to realizing a low-on-resistance power semiconductor element.

  As an example of a MOSFET that solves this problem, there is known a structure in which a vertically elongated strip-shaped p-type pillar layer and an n-type pillar layer called a super junction structure are alternately arranged in a horizontal direction in a drift layer (for example, Patent Documents). 1). In the super junction structure, the same amount of impurities is contained in the p-type pillar layer and the n-type pillar layer, thereby creating a pseudo non-doped layer and maintaining a high breakdown voltage while passing a current through the highly doped n-type pillar layer. The low on-resistance exceeding the material limit is realized by flowing the current.

In the MOSFET having the super junction structure, variations in the impurity concentration of each semiconductor pillar layer greatly affect on-resistance and breakdown voltage characteristics. In addition, it is necessary to increase the breakdown voltage in the termination region surrounding the breakdown voltage in the element region where the MOSFET is formed. Otherwise, the breakdown voltage of the entire semiconductor element is determined by the breakdown voltage of the termination region, and a high avalanche resistance cannot be obtained.
JP 2001-135819 A

  An object of the present invention is to provide a semiconductor element having a high breakdown voltage and a high avalanche resistance in a semiconductor element having a super junction structure.

A semiconductor element according to a first aspect of the present invention includes a first conductive type first semiconductor layer, a first conductive type first semiconductor pillar layer, and a second conductive type second semiconductor on the first semiconductor layer. Pillar layers formed by alternately forming pillar layers in a direction along the surface of the first semiconductor layer, a first main electrode electrically connected to the first semiconductor layer, and a surface of the pillar layer A second conductive type semiconductor base layer formed on the semiconductor base layer; a first conductive type semiconductor diffusion layer selectively formed on a surface of the semiconductor base layer; and the semiconductor base layer and the semiconductor diffusion layer so as to be bonded to each other. In order to form a channel between the formed second main electrode and the semiconductor diffusion layer and the first semiconductor pillar layer, a region extending from the semiconductor diffusion layer to the first semiconductor pillar layer is interposed via an insulating film. A control electrode formed, and the pillar layer includes an element region Only it Not is also formed in the end region of the surrounding,
At the same depth position of the device region said termination region, the impurity concentration [cm ^-3] in the in the element region second semiconductor pillar layer, an impurity concentration of said at termination region second semiconductor pillar layer [cm ^-3] Is less than ± 5%, the width W11 [um] of the first semiconductor pillar layer and the width W21 [um] of the second semiconductor pillar layer in the element region, and the first semiconductor pillar in the termination region The width W12 [um] of the layer and the width W22 [um] of the second semiconductor pillar layer are represented by [Equation 3].
W21 / W11 <W22 / W12
It is formed so as to satisfy the relationship.

A semiconductor device according to a second aspect of the present invention includes a first conductive type first semiconductor layer, a first conductive type first semiconductor pillar layer, and a second conductive type second semiconductor on the first semiconductor layer. Pillar layers formed by alternately forming pillar layers in a direction along the surface of the first semiconductor layer, a first main electrode electrically connected to the first semiconductor layer, and a surface of the pillar layer A second conductive type semiconductor base layer formed on the semiconductor base layer; a first conductive type semiconductor diffusion layer selectively formed on a surface of the semiconductor base layer; and the semiconductor base layer and the semiconductor diffusion layer so as to be bonded to each other. In order to form a channel between the formed second main electrode, and the semiconductor diffusion layer and the first semiconductor pillar layer, an insulating film is interposed between the semiconductor diffusion layer and the first semiconductor pillar layer. A control electrode formed, and the pillar layer includes an element region Only Not being formed in the end region of the surrounding, at the same depth position in said device region wherein the termination region, the element impurity dose amount of the first semiconductor pillar layer in the region Q11 [cm ^-2] and The impurity dose Q21 [cm ⁻² ] of the second semiconductor pillar layer, the impurity dose Q12 [cm ⁻² ] of the first semiconductor pillar layer in the termination region, and the impurity dose Q22 of the second semiconductor pillar layer [Cm ^-2 ] is [Equation 4]
Q21 / Q11 <Q22 / Q12
It is characterized by satisfying this relationship.

  According to the present invention, it is possible to provide a semiconductor element having a high breakdown voltage and a high avalanche resistance in a semiconductor element having a super junction structure.

As described above, in the MOSFET having the super junction structure, the variation in the impurity concentration of each semiconductor pillar layer greatly affects the on-resistance and the breakdown voltage characteristics. FIG. 3 shows the relationship between the impurity dose amount (cm ⁻² ) Qp to the p-type semiconductor pillar layer and the on-resistance Ron or the breakdown voltage Vdsse. The impurity dose of the n-type pillar layer is Qn (cm ⁻² ), and the impurity dose of the p-type pillar layer is Qp (cm ⁻² ). When Qn = Qp, the charge balance of the p-type / n-type semiconductor pillar layers is balanced, and the withstand voltage Vdsse is maximized. In both cases of Qn> Qp and Qn <Qp, the breakdown voltage Vdsse is lower than that in the case of Qn = Qp. Further, the on-resistance Ron increases as the impurity dose Qp increases relative to Qn.

  The above description is about the breakdown voltage Vdsse in the element region, and the curve of the breakdown voltage Vdssp in the termination region on the outer periphery of the element region is different from the curve of the breakdown voltage vdsse in the element region. The breakdown voltage Vdssp in the termination region is set larger than the breakdown voltage Vdsse in the element region (Vdssp> Vdsse). Otherwise, the breakdown voltage of the entire semiconductor element is determined not by the breakdown voltage Vdsse of the element region but by the breakdown voltage Vdssp of the termination region, and the avalanche current is concentrated only on the termination portion, thereby obtaining a high avalanche resistance. It cannot be done, and it may cause element destruction.

  By the way, the maximum value of the withstand voltage Vdssp is obtained not in the case of Qn = Qp but in the region of Qp> Qn in the case of an n-channel MOSFET (see FIG. 3). In FIG. 3, the maximum value of the breakdown voltage Vdssp is obtained in the region of Qp = Qn × 1.1. That is, the change curve of the withstand voltage Vdssp has a relationship in which the peak position (maximum value position) is shifted with respect to the change curve of the withstand voltage Vdsse. However, in spite of this, it is normal in the prior art that the impurity dose is set so that Qn = Qp also in the termination region. Due to this shift, the region (margin) where the withstand voltage Vdssp in the termination region is larger than the withstand voltage Vdsse in the element region and the rated voltage of the MOSFET can be obtained becomes narrow. Referring to FIG. 3, when Qn = Qp is set as a set value, in the element region, a range of ± 20% from Qp = 0.8 × Qn to Qp = 1.2 × Qn. Even if the deviation of the impurity dose occurs, the withstand voltage Vdsse becomes equal to or higher than the rated voltage. However, in the minus direction (Qn> Qp), the withstand voltage Vdsse falls below the withstand voltage Vdssp at a point (point A) before Qp = 0.8 × Qn. As described above, when a variation from the set value of the impurity dose occurs in the pillar layer forming process or the like, there are many cases where the withstand voltage Vdssp in the termination region falls below the withstand voltage Vdsse in the element region, and a MOSFET that satisfies the required characteristics has a high yield. Can't get in.

  In the current semiconductor manufacturing technology, it is not always easy to accurately control the impurity dose, so it is desirable to increase this margin to some extent.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view schematically showing the configuration of a power MOSFET according to an embodiment of the present invention. In this MOSFET, an n-type pillar layer 5 and a p-type pillar layer 2 having a vertically long strip shape in cross section along the surface of the n + type substrate 1 (first direction) ) Alternately to form a super junction structure. The super junction structure is formed not only in the element region in which the MOSFET is formed, but also in the outer peripheral termination region.

  A drain electrode 6 common to a plurality of MOSFET cells is formed under the n + type substrate 1. In the example of FIG. 1, the bottom of the p-type pillar layer 2 is not in contact with the n + -type substrate 1, and one n-type pillar layer 5 is provided between the bottom of the p-type pillar layer 2 and the n + -type substrate 1. Department is supposed to exist. It is also possible to configure so that the bottom of the p-type pillar layer 2 is in contact with the n + -type substrate 1. A p-type base layer 3 is formed on the surface of the super junction structure, and an n-type source diffusion layer 4 is selectively formed in a stripe shape on the surface of the p-type base layer 3. The p-type base layer 3 is partially extended not only to the element region but also to the termination region in order to improve breakdown voltage characteristics.

  Further, from the side surface position of the n-type source diffusion layer 4, the vertical direction (Y direction) reaching the n-type pillar layer 5 through the p-type base layer 3 is defined as the longitudinal direction, and the gate electrode 9 is interposed through the gate insulating film 8. Is formed. The gate electrode 9 is applied with a gate voltage equal to or higher than a threshold voltage, thereby forming a channel extending in the vertical direction in the p-type base layer 3 to make the MOSFET conductive.

  A common source electrode 7 is connected to each MOSFET on the p-type base layer 3 and the n-type source diffusion layer 4. The source electrode 7 is insulated from the gate electrode 9 by the gate insulating film 8 or the like. A p-type contact layer 10 for reducing contact resistance is formed between the source electrode 7 and the p-type base layer 3. A field plate electrode 14 is formed on the n-type pillar layer 5 and the p-type pillar layer 2 in the termination region via an insulating film 13. The field plate electrode 14 is connected to the source electrode 7 or the gate electrode 9, and together with the p-type RESURF layer 15 having an impurity concentration lower than that of the p-type base layer 3, the depletion layer when the drain voltage rises when the MOSFET is not conducting. Is extended in the lateral direction, and the electric field applied to the end of the p-type base layer 3 is relaxed to increase the breakdown voltage. In addition, a p-type RESURF layer 15 is formed in the termination region on the surface of the super junction structure, and acts to increase the breakdown voltage by extending the depletion layer laterally when the MOSFET is not conducting.

  The width at the depth D of one n-type pillar layer 5 in the element region (the width with respect to the direction (x direction) in which the pn pillars appear alternately) is Wn1, and the width at the depth D of one p-type pillar layer 2 in the element region Wp1, the cell pitch at the depth D of the super junction structure in the element region is Wcell1 (= Wn1 + Wp1), the width at the depth D of one n-type pillar layer 5 in the termination region is Wn2, and one p-type pillar layer in the termination region When the width at the depth D of 2 is Wp2, and the cell pitch at the depth D of the super junction structure of the termination region is Wcell2 (= Wn2 + Wp2), the p-type pillar layer 2 and the n-type so that the following relational expression is satisfied. A pillar layer 5 is formed.

[Equation 5]
Wp1 / Wn1 <Wp2 / Wn2
Preferably, the following relational expression is further satisfied.

[Equation 6]
Wp2> Wp1 and Wcell1 = Wcell2
That is, while the cell pitch Wcell is substantially the same in the element region and the termination region at the same depth, the width Wp2 of the p-type pillar layer 2 in the termination region is the width Wp1 of the p-type pillar layer 2 in the device region at the same depth. By making it wider, it is also possible to satisfy the relationship of [Equation 5]. Here, when the difference between the cell pitches Wcell1 and Wcell2 is less than 5%, they are substantially the same, and it is considered that Wcell1 = Wcell2 holds.

  When the relationship of [Expression 5] and thus [Expression 6] is satisfied, as shown in FIG. 2, the peak of the change curve of the withstand voltage Vdssp in the termination region and the peak of the change curve of the withstand voltage Vdssp in the element region are Compared to the conventional case (FIG. 3). Note that the horizontal axis on the lower side of the graph in FIG. 2 indicates the magnitude relationship between the impurity doses of the p-type pillar layer 2 and the n-type pillar layer 5 in the element region, and the upper horizontal axis indicates the p-type pillar in the termination region. The magnitude relationship between the impurity doses of the layer 2 and the n-type pillar layer 5 is shown. That is, when the change curve of the breakdown voltage Vdsse in the element region reaches a peak at Qn = Qp, the breakdown voltage Vdssp of the termination region is satisfied by satisfying the relationship of [Expression 5] and thus [Expression 6]. Also, the set value of the impurity dose can be set so that the change curve also has a peak at a position closer to this than the conventional curve. By setting the widths Wp and Wn appropriately, it is possible to make them substantially the same position. For this reason, compared with the prior art, a region (margin) in which the withstand voltage Vdssp is higher than the rated voltage and the withstand voltage Vdssp of the termination region is higher than the withstand voltage Vdsse of the element region can be widened. Even if a certain degree of occurrence occurs, a MOSFET satisfying the required characteristics can be obtained with a high yield. In the example of FIG. 2, the peak position of the withstand voltage Vdssp in the termination region and the peak position of the withstand voltage Vdsse in the element region substantially match, and the graphs of both do not intersect. For this reason, the margin is not affected by the withstand voltage Vdssp, so that the margin can be widened.

In general, when the n-type pillar layer 5 or the p-type pillar layer 2 having a super junction structure is formed, changing the impurity concentration [cm ⁻³ ] between the element region and the termination region increases the number of processes. Cost increases. However, with the above method, the impurity concentration [cm ⁻³ ] of the p-type pillar layer 2 is substantially uniform in the element region and the termination region, and the element region is Qn in the termination region even when Qn = Qp. <The ideal state shown in FIG. 2 as Qp can be provided without increasing the number of steps. Here, when the difference between the impurity concentration of the p-type pillar layer 2 in the element region and the impurity concentration of the p-type pillar layer 2 in the termination region is within ± 5%, both are substantially uniform. To do.

  Specifically, when Wn1 = Wp1 = 6.0 μm and Wcell1 = Wcell2 = 12.0 μm, Wp2 is set to 1.05 times or more (for example, Wp2 = 6.3 μm, Wn2 = 5.7 μm) of Wn2. , [Equation 5] and [Equation 6] are obtained, and as shown in FIG. 2, the peak of the change curve of the withstand voltage Vdssp in the termination region and the peak of the change curve of the withstand voltage Vdssp in the element region are conventionally ( Compared to FIG. 3). The ion implantation process executed as a process for forming the pillar layers 2 and 5 can be performed with an error of about ± 0.1 μm, that is, an error of about ± 2% with respect to a width of 6.0 μm. Therefore, if the pillar width is set so that Wp2> Wn2 × 1.05, the relationship of [Equation 5] and [Equation 6] can be obtained reliably.

  In addition, the width | variety of each pillar layer 2 and 5 can be measured as follows, for example. For example, it can be measured by measuring the capacitance distribution between the probe and the sample using a scanning capacitance microscope and specifying the impurity distribution. Alternatively, the p-type dopant amount and the n-type dopant amount can be measured by a SIMS apparatus (Secondary Ion Mass Stereoscopy), and the position where both the dopant amounts are equal can be determined as a boundary position of the pn junction. In the case of this measurement method, it is also possible to measure the impurity concentration (cm −3) of the dopant contained in each pillar layer 2, 5. Further, by integrating this, the integration of each pillar layer 2, 5 The impurity dose (cm−2) can also be measured.

  When the widths Wp1, Wn1, Wp2, and Wn2 of the pillar layers 2 and 5 change in the depth direction (vertical direction), the average value should satisfy the above [Equation 5] and [Equation 6]. That's fine.

  Next, a power MOSFET according to a second embodiment of the present invention will be described. The power MOSFET of this embodiment is different from that of the first embodiment in the dimensions of the super junction structure and the other parts are the same, and will be described with reference to FIG.

In this embodiment, the widths of the n-type pillar layer 5 and the p-type pillar layer 2 may be substantially the same in the element region and the termination region. However, when the difference between the two is less than ± 5%, they are regarded as substantially the same. Instead, the impurity dose Qn1 [cm ⁻² ] to the n-type pillar layer 5 in the element region, the impurity dose Qp1 [cm ⁻² ] to the p-type pillar layer 2, and the n-type pillar layer 5 in the termination region When the impurity dose amount Qn2 [cm ⁻² ] and the impurity dose amount Qp2 [cm ⁻² ] to the p-type pillar layer 2 are set,
[Equation 7]
Qp1 / Qn1 <Qp2 / Qn2
The impurity dose is controlled so that the above holds. For example, the relationship of [Equation 7] can be obtained by controlling the impurity dose so that Qp2> Qn2 while Qp1 = Qn1. In this case, while considering Qp1 = Qn1 and taking into account errors in the impurity implantation process, the impurity dose is controlled so that Qp2> = 1.10 × Qn2, thereby ensuring the relationship of [Expression 7] above. Obtainable.

  In the termination region, it is possible to obtain a higher breakdown voltage by reducing the impurity dose as a whole as compared with the element region. As a result, the breakdown voltage Vdssp of the termination region is higher than the breakdown voltage Vdsse of the element region. A high region (margin) can be widened. For example, when the impurity dose amount is set to Qn1 = Qp1 = X in the element region, the impurity dose amounts Qp2 and Qn2 are smaller than the element region in the termination region, for example, Qn2 = X / 2, Qp2 = 1.1 × X By setting it to about / 2, the relationship of the above [Equation 7] is satisfied, and a wide margin can be obtained. As a result, the peak of the withstand voltage Vdssp curve in the termination region becomes higher than that in the case where the impurity dose amount is equal between the element region and the termination region, and the spread of the withstand voltage Vdssp curve becomes larger (the inclination becomes smaller). Accordingly, the margin is widened.

  In the present invention, an n-type pillar layer 5 and a p-type pillar layer 2 having a vertically long strip shape along the surface of the n + type substrate 1 on the n + type substrate 1 functioning as the drain layer shown in FIG. The case where they are alternately arranged in the horizontal direction (first direction) is mentioned. However, for example, there is a termination region in which the n-type pillar layer 5 and the p-type pillar layer 2 extend in parallel in the direction perpendicular to the paper surface (second direction). Is connected to the p-type base layer 3, the depletion layer is easy to spread as compared with the first direction, and a high breakdown voltage is obtained. For this reason, the effect of the present invention is greater in the first direction shown in FIG.

  Although the embodiments of the invention have been described above, the present invention is not limited to these embodiments, and various modifications and additions can be made without departing from the spirit of the invention. For example, in the above-described embodiment, the MOSFET having the trench gate structure has been described as an example. However, the present invention can also be applied to the MOSFET having the planar gate structure. In the above embodiment, a guard ring layer may be formed instead of providing the field plate electrode 14. Alternatively, the same effect can be obtained when the p-type RESURF layer 15 shown in FIG. 1 is not formed.

  Further, in the p-type pillar layer 2 and the n-type pillar layer 5, even when the impurity concentration is different in the depth direction, the impurity concentration is set so that the above formula is satisfied at the respective positions in the depth direction. It is possible to control.

It is sectional drawing which shows typically the structure of power MOSFET which concerns on embodiment of this invention. An example of a change curve of the withstand voltage Vdssp of the termination region and the withstand voltage Vdsse of the element region in the power MOSFET of the present embodiment is shown. An example of a change curve of the withstand voltage Vdssp of the termination region and the withstand voltage Vdsse of the element region in the conventional power MOSFET is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... n + type substrate, 2 ... p-type pillar layer, 3 ... p-type base layer, 4 ... n-type source diffusion layer, 5 ... n-type pillar layer, 6 ... Drain Electrode, 7 ... Source electrode, 8 ... Gate insulating film, 9 ... Gate electrode, 10 ... Contact layer, 12 ... Field stop layer, 13 ... Insulating film, 14 ... Field plate electrode, 15... P-type RESURF layer.

Claims (5)

A first semiconductor layer of a first conductivity type;
A pillar layer formed by alternately forming a first conductivity type first semiconductor pillar layer and a second conductivity type second semiconductor pillar layer on the first semiconductor layer in a direction along the surface of the first semiconductor layer. When,
A first main electrode electrically connected to the first semiconductor layer;
A second conductivity type semiconductor base layer formed on a surface of the pillar layer;
A semiconductor diffusion layer of a first conductivity type selectively formed on the surface of the semiconductor base layer;
A second main electrode formed to be bonded to the semiconductor base layer and the semiconductor diffusion layer;
A control electrode formed through an insulating film in a region extending from the semiconductor diffusion layer to the first semiconductor pillar layer to form a channel between the semiconductor diffusion layer and the first semiconductor pillar layer;
The pillar layer is formed not only in the element region but also in a terminal region around the element region,
At the same depth position of the device region said termination region, the impurity concentration [cm ^-3] in the in the element region second semiconductor pillar layer, an impurity concentration of said at termination region second semiconductor pillar layer [cm ^-3] The difference between is less than ± 5%,
The width W11 [um] of the first semiconductor pillar layer and the width W21 [um] of the second semiconductor pillar layer in the element region, and the width W12 [um] of the first semiconductor pillar layer and the second semiconductor pillar layer in the termination region Width W22 [um] is [Equation 1]
W21 / W11 <W22 / W12
A semiconductor element formed so as to satisfy the above relationship. 3. The semiconductor element according to claim 2, wherein the width W22 [um] of the second semiconductor pillar layer in the termination region is larger than the width W21 [um] of the second semiconductor pillar layer in the element region. . The total width in the first direction of the first semiconductor pillar layer and the second semiconductor pillar layer in the element region, and the first direction of the first semiconductor pillar layer and the second semiconductor pillar layer in the termination region. The difference between the width and the total width is less than 5%, the widths W11 and W21 are set to have a difference of less than 5%, and the width W22 is set to 1.05 or more times the width W12. 2. The semiconductor element according to claim 1, wherein the semiconductor element is formed. A pillar layer formed by alternately forming a first conductivity type first semiconductor pillar layer and a second conductivity type second semiconductor pillar layer on the first semiconductor layer in a direction along the surface of the first semiconductor layer. When,
A first main electrode electrically connected to the first semiconductor layer;
A second conductivity type semiconductor base layer formed on a surface of the pillar layer;
A semiconductor diffusion layer of a first conductivity type selectively formed on the surface of the semiconductor base layer;
A second main electrode formed to be bonded to the semiconductor base layer and the semiconductor diffusion layer;
A control electrode formed through an insulating film in a region extending from the semiconductor diffusion layer to the first semiconductor pillar layer to form a channel between the semiconductor diffusion layer and the first semiconductor pillar layer;
The pillar layer is formed not only in the element region but also in a terminal region around the element region,
At the same depth position in the element region and the termination region, the impurity dose amount Q11 [cm ⁻² ] of the first semiconductor pillar layer and the impurity dose amount Q21 [cm ⁻² ] of the second semiconductor pillar layer in the element region. , And the impurity dose Q12 [cm ⁻² ] of the first semiconductor pillar layer and the impurity dose Q22 [cm ⁻² ] of the second semiconductor pillar layer in the termination region are [Equation 2].
Q21 / Q11 <Q22 / Q12
A semiconductor element characterized by satisfying the relationship: The semiconductor element according to claim 4, wherein an impurity dose Q22 of the second semiconductor pillar layer in the termination region is larger than an impurity dose Q21 of the second semiconductor pillar layer in the element region.

Images