JP2022186274A - Semiconductor device manufacturing method - Google Patents

Abstract

Kind Code: A1 A method of manufacturing a semiconductor device capable of suppressing a change in characteristics or destruction of a gate insulating film is provided.
A target device is prepared in which a first electrode, a second electrode, and a gate electrode for controlling a current flowing between the first electrode and the second electrode are arranged on a gate insulating film on a semiconductor substrate. Then, the target device is subjected to a first characteristic test that depends on the state of the gate insulating film, a breakdown is generated in the target device to measure the breakdown voltage, and the breakdown voltage is measured. performing a second characteristic test dependent on the state of the insulating film, deriving a change between the first characteristic test and the second characteristic test, comparing the derived change result with a change threshold range, and determining the change result as a change threshold and performing quality judgment that the target device is determined to be non-defective when it is determined that it is within the range.
[Selection drawing] Fig. 2

Description

The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor element having a gate insulating film is formed.

2. Description of the Related Art Conventionally, a semiconductor device having a gate insulating film has been proposed (for example, see Patent Document 1). Specifically, this semiconductor device is configured by forming a MOSFET (abbreviation for Metal Oxide Semiconductor Field Effect Transistor) on a semiconductor substrate including a drift layer and a base layer. More specifically, in this semiconductor device, a p-type base layer is formed on an n ⁻ -type drift layer, and an n ⁺ -type source region is formed on the surface layer of the base layer. An n ⁺ -type drain region is formed on the side opposite to the base layer with the drift layer interposed therebetween. A plurality of trenches are formed to penetrate the base layer and the source region, and each trench is filled with a gate insulating film formed on the wall surface and a gate electrode formed on the gate insulating film.

An upper electrode is arranged so as to be electrically connected to the base layer and the source region, and a lower electrode is arranged so as to be electrically connected to the drain region in the semiconductor substrate.

JP 2019-140242 A

By the way, when manufacturing a semiconductor device as described above, a pass/fail judgment is made after performing a characteristic test such as leakage current measurement once. In quality determination, if the measurement result is within a predetermined range, the product is determined to be non-defective, and if the measurement result is outside the predetermined range, the product is determined to be defective.

Further, in the semiconductor device as described above, holes entering the gate insulating film during use may change the characteristics of the gate insulating film or destroy the gate insulating film. However, it is difficult to determine whether or not it is difficult for holes to enter the gate insulating film during use, etc., with only one characteristic inspection. Therefore, in the manufacturing method as described above, there is a possibility that a semiconductor device in which the characteristics of the gate insulating film may change or may be destroyed may be judged as non-defective.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device that can suppress changes in the characteristics of the gate insulating film or damage to the gate insulating film.

Claim 1 for achieving the above object is a method of manufacturing a semiconductor device in which a semiconductor element having a gate insulating film (17) is formed, comprising: a semiconductor substrate (10); preparing a target device in which two electrodes (21) and a gate electrode (18) for controlling a current flowing between the first electrode and the second electrode are arranged on a gate insulating film; performing a first characteristic inspection depending on the state of the gate insulating film; causing breakdown in the target device to measure the breakdown voltage; performing a second property test, deriving a change in the first property test and the second property test, comparing the derived change result to a change threshold range, and determining that the change result is within the change threshold range and determining whether the target device is a non-defective product.

According to this, a characteristic test depending on the state of the gate insulating film is performed before and after the withstand voltage measurement that caused the breakdown. Then, the change is derived from the result of the characteristic inspection before and after the breakdown voltage measurement, and the pass/fail determination is performed by determining whether the derived change result is within the change threshold range. Therefore, it is possible to preliminarily determine that a target device in which holes tend to enter the gate insulating film during use is defective. Therefore, it is possible to manufacture a semiconductor device that suppresses a change in the characteristics of the gate insulating film and a breakdown of the gate insulating film.

It should be noted that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and specific components etc. described in the embodiments described later.

1 is a cross-sectional view of a SiC semiconductor device according to a first embodiment; FIG. 2 is a flow chart showing a manufacturing process of the semiconductor device shown in FIG. 1; FIG. 4 is a diagram showing the relationship between drain-source voltage and current; FIG. 4 is a schematic diagram showing a state of the SiC semiconductor device when breakdown occurs; FIG. 4B is a schematic diagram showing the state of the SiC semiconductor device continued from FIG. 4A;

An embodiment of the present invention will be described below with reference to the drawings. In addition, in each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described with reference to the drawings. In this embodiment, as shown in FIG. 1, a SiC semiconductor device in which a MOSFET as a semiconductor element is formed on a semiconductor substrate 10 made of silicon carbide (hereinafter also simply referred to as SiC) is taken as an example. explain. Although FIG. 1 shows only the cell region of the SiC semiconductor device, the actual SiC semiconductor device is provided with a peripheral region having a breakdown voltage structure so as to surround the cell region.

A SiC semiconductor device is configured using a semiconductor substrate 10 . Specifically, the SiC semiconductor device is configured using a semiconductor substrate 10 including an n ⁺ -type substrate 11 made of SiC. In this embodiment, the substrate 11 has, for example, an off angle of 0 to 8° with respect to the (0001) Si plane, and the concentration of n-type impurities such as nitrogen and phosphorus is 1.0×10 ¹⁹ /cm ³ . and having a thickness of about 50 to 300 μm is used. The substrate 11 constitutes the drain region in this embodiment and corresponds to the first impurity region.

An n ⁻ -type drift layer 12, a p-type base layer 13, etc., which are made of SiC, are formed on the surface of the substrate 11 by epitaxial growth or the like. Hereinafter, the surface of the semiconductor substrate 10 on the side of the base layer 13 is referred to as one surface 10a of the semiconductor substrate 10, and the surface of the semiconductor substrate 10 on the side of the substrate 11 is referred to as the other surface 10b of the semiconductor substrate 10. FIG. Incidentally, in this embodiment, the source region 14 corresponds to the second impurity region.

The drift layer 12 has, for example, an n-type impurity concentration of about 1.0 to 50.0×10 ¹⁵ /cm ³ and a thickness of about 5 to 50 μm. The base layer 13 is formed on the drift layer 12 and has, for example, a p-type impurity concentration of approximately 2.0×10 ¹⁷ /cm ³ and a thickness of approximately 0.5 to 2 μm.

The source region 14 is formed in the surface layer portion of the base layer 13 and has a higher impurity concentration than the drift layer 12. For example, the n-type impurity concentration in the surface layer portion is 2.5×10 ¹⁸ to 2.0×10. It is about ¹⁹ /cm ³ and the thickness is about 0.2 to 1.5 μm. A p ⁺ -type contact region having a higher impurity concentration than the base layer 13 may be formed in the surface layer portion of the base layer 13 on the opposite side of the trench 16 to be described later with the source region 14 interposed therebetween. .

Further, in this embodiment, a p-type deep layer 15 is formed in the surface layer portion of the drift layer 12 . The deep layer 15 of the present embodiment has a p-type impurity concentration higher than that of the base layer 13, and a plurality of deep layers 15 are arranged at regular intervals and are spaced apart from each other without crossing points to form a striped upper surface layout. ing. For example, each deep layer 15 has a p-type impurity concentration of about 1.0×10 ¹⁷ to 1.0×10 ¹⁹ /cm ³ and a width of 0.7 μm. Each deep layer 15 has a depth of 0.4 μm or more, and is formed to a position deeper than the bottom surface of a trench 16 to be described later. It is designed to suppress the entry of

In this embodiment, a structure in which the deep layer 15 is formed only in the surface layer of the drift layer 12 will be described as an example. may be formed so as to reach In this case, the deep layer 15 may be arranged, for example, by forming a trench from the one surface 10a side of the semiconductor substrate 10 and burying the inside of the trench. Moreover, in this embodiment, the deep layer 15 corresponds to an electric field relaxation layer.

A trench 16 having a width of, for example, about 0.8 μm is formed in the semiconductor substrate 10 so as to penetrate the base layer 13 and the source region 14 and reach the drift layer 12 . The trench 16 is formed in a linear layout with the width direction in the horizontal direction of FIG. 1, the longitudinal direction in the normal direction to the paper surface, and the depth direction in the vertical direction on the paper surface. Although only one trench 16 is shown in FIG. 1 , a plurality of trenches 16 are actually arranged at equal intervals in the left-right direction of the paper, and each trench 16 is located between the deep layers 15 . They are arranged so as to be sandwiched in a stripe shape.

Each trench 16 is filled with a gate insulating film 17 formed to cover the wall surface of each trench 16 and a gate electrode 18 made of polysilicon or the like formed on the gate insulating film 17 . there is A trench gate structure is thus formed. In this embodiment, the wall surface of the trench 16 corresponds to the surface of the base layer interposed between the second impurity region and the drift layer. In addition, in the SiC semiconductor device of the present embodiment, the current flowing between the upper electrode 20 and the lower electrode 21 (to be described later) is controlled by the voltage applied to the gate electrode 18 .

An interlayer insulating film 19 made of BPSG (abbreviation for Borophosphosilicate Glass) or the like is formed on the base layer 13 (that is, one surface 10a of the semiconductor substrate 10). A contact hole 19 a is formed in the interlayer insulating film 19 to expose a part of the source region 14 and the base layer 13 .

An upper electrode 20 is formed on interlayer insulating film 19 to be electrically connected to source region 14 and base layer 13 through contact hole 19a. The upper electrode 20 of this embodiment is composed of, for example, a plurality of metals such as Ni/Al. A portion of the plurality of metals, which is in contact with the portion forming the n-type SiC (that is, the source region 14), is made of a metal capable of making ohmic contact with the n-type SiC. At least the portion of the plurality of metals that contacts p-type SiC (that is, base layer 13) is made of a metal capable of making ohmic contact with p-type SiC. In addition, in this embodiment, the upper electrode 20 corresponds to the first electrode. Note that the deep layer 15 is electrically connected to the upper electrode 20 through the base layer 13 .

A lower electrode 21 electrically connected to the substrate 11 is formed on the other surface 10 b side of the semiconductor substrate 10 . In addition, in this embodiment, the lower electrode 21 corresponds to the second electrode. In the SiC semiconductor device of the present embodiment, such a structure constitutes a MOSFET having a trench gate structure, which is an n-channel type inversion type.

The above is the configuration of the SiC semiconductor device according to the present embodiment. In this embodiment, the n ⁺ -type and n ^- -type correspond to the first conductivity type, and the p-type corresponds to the second conductivity type. The SiC semiconductor device is configured as described above, and the semiconductor substrate 10 includes the substrate 11, the drift layer 12, the deep layer 15, the base layer 13, the source region 14, and the like. Next, the operation of the SiC semiconductor device will be described.

In the SiC semiconductor device as described above, when a voltage lower than that of the lower electrode 21 is applied to the upper electrode 20 and a voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode 18, the trench 16 in the base layer 13 is opened. An n-type inversion layer (that is, a channel) is formed in the portion in contact with the . Then, electrons are supplied from the source region 14 to the drift layer 12 through the inversion layer, so that an ON state in which a current flows between the upper electrode 20 and the lower electrode 21 is established.

In addition, in the off state in which no current flows between the upper electrode 20 and the lower electrode 21, even if a high voltage is applied, the deep layer 15 formed to a position deeper than the trench gate structure allows the current to flow to the bottom of the trench 16. entry of the electric field is suppressed. Therefore, electric field concentration at the bottom of the trench is relieved, and breakdown of the gate insulating film 17 is prevented.

Next, a method for manufacturing the above SiC semiconductor device including quality determination will be described with reference to FIGS. 2, 3, 4A and 4B.

As shown in FIG. 2, when manufacturing a SiC semiconductor device, first, in step S100, predetermined semiconductor manufacturing processes such as epitaxial growth, etching, and ion implantation are performed to obtain the SiC semiconductor device shown in FIG. Prepare the target device. Note that the target device may be a wafer having a plurality of chip forming regions, in which the SiC semiconductor device of FIG. 1 is formed in each chip forming region, or may be divided into chip units and may be in a chip state in which the SiC semiconductor device is formed.

Next, in steps S101 to S103, a first characteristic inspection depending on the state of the gate insulating film 17 is performed on the target device. In this embodiment, in step S101, a first leakage current measurement between the gate and source of the target device is performed. In step S102, a first leakage current measurement between the drain and gate of the target device is performed. In step S103, a first threshold voltage measurement is performed in the target device.

Although not particularly limited, each measurement in steps S101 to S103 is performed, for example, as follows. That is, in the first leakage current measurement between the gate and the source in step S101, the drain and the source are connected, and a predetermined voltage is applied between the gate and the source, whereby the gate and the source are connected through the gate insulating film 17. Measure the flowing leakage current. In the first leak current measurement between the drain and the gate in step S102, the gate and the source are connected and set to the ground potential, and a predetermined voltage is applied to the lower electrode 21, so that the drain-gate Measure the leakage current flowing through In the first threshold voltage measurement in step S103, the gate voltage when the current flows while applying the gate voltage is measured as the threshold voltage.

Subsequently, in step S104, withstand voltage measurement of the target device is performed. In this embodiment, as shown in FIG. 3, a breakdown is generated by applying a predetermined voltage between the drain and the source, and the voltage at which the breakdown occurs is measured as the breakdown voltage. In the example of FIG. 3, breakdown occurs when the drain-source voltage is about 1650V.

After that, in the present embodiment, a first pass/fail judgment is performed in step S105. Specifically, based on the measurement results of steps S101 to S104, it is determined whether each measurement result is within the threshold range. If each measurement result is within each threshold range, the product is determined to be non-defective, and if at least part of each measurement result is outside the threshold range, the product is determined to be defective. After that, in the present embodiment, the processes after step S106, which will be described later, are performed on the target device determined to be non-defective.

Here, the state of the target device (that is, the SiC semiconductor device) when the breakdown voltage measurement in step S104 is performed will be described. As shown in FIG. 4A, holes h are generated in the drift layer 12 when breakdown occurs in the target device. Then, as shown in FIG. 4B, the holes h may partly enter the gate insulating film 17 as the holes h are accelerated by the electric field.

In this case, in the target device like this embodiment, the easiness (that is, the probability of entry) of the hole h entering the gate insulating film 17 depends on the n-type drift layer 12, the p-type base layer 13, and the deep It depends on the depletion layer formed between the layer 15 and the layer 15 . That is, the ease with which the holes h enter the gate insulating film 17 depends on the quality of the drift layer 12 , the base layer 13 , and the deep layer 15 . Then, when the hole h enters the inside of the gate insulating film 17, the characteristics depending on the state of the gate insulating film 17 change. When the holes h enter the gate insulating film 17, the more the holes h enter the gate insulating film 17, the more the leakage current and the higher the threshold voltage.

For this reason, in the present embodiment, in steps S106 and S108, the target device is again subjected to the second characteristic inspection depending on the state of the gate insulating film 17. FIG. In this embodiment, in step S106, a second leakage current measurement between the gate and source of the target device is performed. In step S107, a second leakage current measurement between the drain and gate of the target device is performed. In step S108, a second threshold voltage measurement is performed on the target device.

The second gate-source leakage current measurement in step S106 is performed under the same conditions as the first gate-source leakage current measurement in step S101. The second drain-gate leakage current measurement in step S107 is performed under the same conditions as the first drain-gate leakage current measurement in step S102. The second threshold voltage measurement in step S108 is performed under the same conditions as the first threshold voltage measurement in step S103.

Next, in step S109, changes in the measurement result of the gate-source leakage current measurement in steps S101 and S106 are derived. In step S110, changes in the measurement results of drain-gate leak current measurements in steps S102 and S107 are derived. In step S111, changes in the measurement results of the threshold voltage measurements in steps S103 and S108 are derived. Note that the change results derived in steps S109 to S111 may be the rate of change between the measurement results or the difference between the measurement results.

After that, in step S112, a second pass/fail judgment is performed. Specifically, based on the change results derived in steps S109 to S111, it is determined whether each change result is within the respective change threshold range. The target device is determined to be non-defective when each change result is within each change threshold range, and is determined to be defective when at least part of each change result is outside the change threshold range.

Note that each change threshold range may be different from each other, may be the same, and may be changed as appropriate. For example, when the rate of change is derived as the change result in steps S109 to S111, the change threshold range is set to 100% for the gate-source leakage current measurement, and the drain-gate leakage current measurement is set to 100%. may be set to 10%.

According to the present embodiment described above, when manufacturing a SiC semiconductor device, a characteristic test depending on the state of the gate insulating film 17 is performed before and after the breakdown voltage measurement. Then, the change is derived from the result of the characteristic inspection before and after the breakdown voltage measurement, and the pass/fail determination is performed by determining whether the derived change result is within the change threshold range. Therefore, it is possible to preliminarily determine that the target device in which the hole h is likely to enter the gate insulating film 17 during use or the like is defective. Therefore, it is possible to manufacture a SiC semiconductor device that suppresses a change in the characteristics of the gate insulating film 17 and a breakdown of the gate insulating film 17 .

Further, in the present embodiment, the second pass/fail judgment is performed using the hole h generated when the breakdown voltage is measured. Therefore, there is no need to perform a process for the sole purpose of intruding the holes h into the gate insulating film 17, and an unnecessary increase in the number of manufacturing processes can be suppressed.

(1) In the present embodiment, three types of measurements, ie, gate-source leakage current measurement, drain-gate leakage current measurement, and threshold voltage measurement, are performed as characteristic inspections that depend on the state of the gate insulating film 17. ing. Therefore, compared with the case where only one of the measurements is performed, the accuracy of quality determination can be improved.

(Other embodiments)
Although the present disclosure has been described with reference to embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

For example, in the above-described first embodiment, a method for manufacturing a SiC semiconductor device having an n-channel type trench gate structure MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described. However, this is only an example, and the manufacturing method of the first embodiment can also be applied to a method of manufacturing a SiC semiconductor device in which semiconductor elements having other structures are formed. For example, the present invention can also be applied to a method of manufacturing a SiC semiconductor device in which a p-channel type trench gate structure MOSFET is formed in which the conductivity type of each component is inverted with respect to the n-channel type. In addition to the MOSFET, the present invention can also be applied to a method of manufacturing a SiC semiconductor device in which an IGBT (abbreviation for Insulated Gate Bipolar Transistor) having a similar structure is formed. In the case of an IGBT, the same as the vertical MOSFET described in the first embodiment, except that the n ⁺ -type substrate 11 (that is, the drain region) in the first embodiment is changed to a P ⁺ -type collector layer. is.

Further, in the first embodiment, the semiconductor substrate 10 may be made of silicon or the like instead of SiC. Furthermore, in the above-described first embodiment, the SiC semiconductor device may have a configuration in which a planar gate structure is formed instead of a configuration in which a trench gate structure is formed. That is, the manufacturing method of the first embodiment can be applied to a manufacturing method of a semiconductor device in which a semiconductor element having a gate insulating film 17 is formed.

Further, in the first embodiment, the electric field relaxation layer such as the deep layer 15 may not be formed. Even with such a configuration, when the withstand voltage is measured in step S104 and holes h are generated due to breakdown, the amount of holes h entering the gate insulating film 17 depends on the quality of the drift layer 12 and the base layer 13. Change. Therefore, even if the manufacturing method of the first embodiment is applied to a semiconductor device in which no electrolytic relaxation layer is formed, it is possible to perform effective quality determination.

Furthermore, in the above-described first embodiment, the measurements in steps S101 to S103 and the measurements in steps S106 to S108 may be performed by at least one of the corresponding measurements. For example, as the measurement, only the leakage current measurement between the gate and the source in steps S101 and S106 may be performed. Also, the measurements in steps S101 to S103 and the measurements in steps S106 to S108 may be performed by performing only at least two of the corresponding measurements. For example, as the measurement, the leakage current between the gate and the source in steps S101 and S106 may be measured, and only the leakage current between the drain and gate in steps S102 and S107 may be measured.

Reference Signs List 10 semiconductor substrate 17 gate insulating film 18 gate electrode 20 upper electrode (first electrode)
21 lower electrode (second electrode)

Claims (3)

A method for manufacturing a semiconductor device in which a semiconductor element having a gate insulating film (17) is formed,
A first electrode (20), a second electrode (21), and a gate electrode (18) for controlling a current flowing between the first electrode and the second electrode are formed on the semiconductor substrate (10) by the gate insulating film. providing a target device disposed thereon;
performing a first characteristic test, which depends on the state of the gate insulating film, on the target device;
causing a breakdown in the target device to measure a breakdown voltage;
After measuring the breakdown voltage, performing a second characteristic inspection again depending on the state of the gate insulating film;
deriving a change in the first characteristic test and the second characteristic test;
Comparing the derived change result with a change threshold range, and performing quality determination for determining that the target device is non-defective when it is determined that the change result is within the change threshold range. Production method. Preparing the target device comprises a drift layer (12) of a first conductivity type, a base layer (13) of a second conductivity type formed on the drift layer, and the base layer of the drift layer. a first-conductivity-type or second-conductivity-type first impurity region (11) formed on the opposite side of the base layer; and a first-conductivity-type second impurity region (14) formed in the surface layer portion of the base layer. The gate insulating film is disposed on the surface of the base layer sandwiched between the second impurity region and the drift layer, and electrically connected to the base layer and the second impurity region. preparing the target device in which the first electrode is arranged so as to be connected to and the second electrode is arranged so as to be electrically connected to the first impurity region;
In the first characteristic inspection, leakage current flowing between the second impurity region and the gate electrode through the gate insulating film is measured; measuring a leakage current flowing between the electrode and measuring a threshold voltage of the gate electrode at which current flows between the first electrode and the second electrode;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the same measurement as that performed in the first characteristic inspection is performed in the second characteristic inspection. By preparing the target device, the semiconductor substrate is made of silicon carbide, and the gate insulating film is formed on the wall surface of a trench (16) that penetrates the base layer and the second impurity region and reaches the drift layer. and, in the drift layer, a second conductivity type electric field relaxation layer (15) having a portion positioned closer to the first impurity region than the bottom surface of the trench and electrically connected to the first electrode. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the formed target device is prepared.

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