JP4580886B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device, and is particularly used for a semiconductor device for low loss power.

  A conventional low-loss power semiconductor device has a junction structure composed of vertical junction groups (hereinafter referred to as super junctions) in which first conductivity type regions and second conductivity type regions are alternately arranged perpendicular to the wafer surface. There is something with.

Conventionally, in order to realize such a structure, a method of forming a super junction by repeatedly applying an N ^- epitaxial growth method and an ion implantation method is known. The outline of the manufacturing process will be described with reference to FIG. In FIG. 7, the flow of the manufacturing process is shown on the right side, and the process cross-sectional view is shown on the left side.

As shown in FIGS. 7A and 7B, an N ⁺ silicon wafer 101 is prepared, and an N ⁻ epitaxial layer 102 is grown on the N ⁺ silicon wafer 101. Next, as shown in FIGS. 7C and 7D, boron ions are implanted using an ion implantation mask to form a P + region 103 in the N ⁻ epitaxial layer 102. Subsequently, using a reverse mask of the ion implantation mask, phosphorus ions are implanted into a region adjacent to the P ⁺ region 103 to form an N ⁺ region 104.

  These ion implantation regions are activated by annealing (not shown). In addition, you may perform these annealing after complete | finishing all the ion implantation processes. In this way, a part of super junctions are formed in which the joint surfaces are perpendicular to the surface of the epitaxial layer and are alternately arranged.

Next, as shown in FIG. 7 (e), again N ^- grown epitaxial layer 102, FIG. 7 (c), the repeating the step shown in FIG. 7 (d), as shown in FIG. 7 (f) Vertical super junctions alternately arranged perpendicular to the wafer surface can be formed.

  Since a method for forming a low-loss power semiconductor device having a super junction as shown in FIG. 7F will be described later in FIG. 5D, detailed description thereof will be omitted here.

If a semiconductor device for low loss power to which a high voltage is applied is formed using such a super junction, the drain junction surface is composed of a P ⁺ region and an N ⁺ region extending in a direction perpendicular to the wafer surface. Since an N ⁺ layer current path is formed in the bulk portion, an NMOS type low-loss power semiconductor device having a low on-resistance and a high drain withstand voltage can be provided.

  However, as described above, the conventional method of manufacturing a low-loss power semiconductor device that repeatedly uses the epitaxial crystal growth method is costly and difficult to manufacture and is not suitable for mass production. .

  As described above, the method of manufacturing a semiconductor device having a super junction using the conventional selective crystal growth method has a problem that it is expensive and difficult to manufacture.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method of manufacturing a low-loss power semiconductor device including a super junction that is easy to manufacture and suitable for mass production.

According to another aspect of the present invention, there is provided a semiconductor device manufacturing method that selectively irradiates a semiconductor with impurity ions, thereby forming first conductivity type regions and second conductivity type regions alternately arranged with respect to a wafer surface. In the manufacturing method of the semiconductor device formed therein, the area of the irradiation region of the impurity ions is such that the first conductivity type region and the second conductivity type region are alternately arranged with junctions formed. It is controlled by electrical or magnetic scanning of impurity ions, and the control of the acceleration energy of the impurity ions and the area of the irradiation region reduces the area of the irradiation region according to the increase of the acceleration energy. .

According to another method of manufacturing a semiconductor device according to the present invention, by selectively irradiating a semiconductor with impurity ions, regions of a first conductivity type and regions of a second conductivity type that are alternately arranged on a wafer surface are formed. In the method of manufacturing a semiconductor device formed in the semiconductor, the area of the impurity ion irradiation region is such that the first conductivity type region and the second conductivity type region are alternately arranged with junctions formed. Is controlled by a mask that shields the impurity ions, and the control of the acceleration energy of the impurity ions and the area of the irradiation region changes the opening area of the mask in accordance with the change of the acceleration energy. .

According to another method of manufacturing a semiconductor device according to the present invention, by selectively irradiating a semiconductor with impurity ions, regions of a first conductivity type and regions of a second conductivity type that are alternately arranged on a wafer surface are formed. In the method of manufacturing a semiconductor device formed in the semiconductor, a positive resist having an inversion relationship with each other so that the first conductivity type region and the second conductivity type region are alternately arranged with junctions formed. The impurity ion shielding mask is formed by baking the same mask pattern on the semiconductor using a negative resist, and the irradiation region of the impurity ions is determined using the shielding mask.

  According to the present invention, it is possible to form a super junction having an arbitrary cross-sectional shape that is uniform in the depth direction without using a complicated and difficult process such as selective crystal growth and trench etching that has been conventionally used. it can. Specifically, ion implantation has the following effects.

  (1) Since selective irradiation of ions can be performed by electrical or magnetic scanning, the width of the irradiation pattern can be continuously controlled in accordance with the change in acceleration energy, and the longitudinal distribution of ions can be controlled. Uniformity is improved.

  (2) If a stripe-shaped resist shielding mask having a certain opening width is formed on the first conductivity type silicon wafer and the second conductivity type region is formed by changing only the acceleration energy, the longitudinal direction of ions Although the distribution uniformity is somewhat inferior, a super junction can be formed using only a general ion implantation apparatus and a PEP process without scanning an ion beam.

  (3) The first and second conductivity type regions are formed by irradiating the intrinsic silicon wafer with ions using a striped resist shielding mask having a certain opening width and a resist shielding mask obtained by inverting the resist mask. Then, since the lateral spread of ions due to scattering compensates each other, a uniform super junction can be formed in the depth direction.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. An example of a super junction forming method using an ion implantation method according to the first embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 1, by irradiating the boron ion beam 2 of low energy from the surface of the N ⁺ silicon wafer 1, lose energy in about N ⁺ inside the implanted boron in silicon wafer 1 short flight, near surface The boron stop region 3 is formed.

At this time, the boron distribution in the horizontal direction along the surface of the N ⁺ silicon wafer 1 and in the vertical direction along the depth direction is as shown at the bottom and right of FIG. Here, the X axis is the position coordinate in the width direction (horizontal direction) in the irradiation region of the boron ion beam 2, the Z axis is the position coordinate in the depth direction (vertical direction) with respect to the surface of the N ⁺ silicon wafer 1, and the Y axis. Is the boron concentration distribution.

  The irradiation region of the boron ion beam is set to have a stripe shape that is long in the direction perpendicular to the paper surface, and the boron ion irradiation region is controlled by electrically scanning the boron ion beam. Magnetic scanning can also be used as the scanning method.

  In addition, the boron ion beam is expanded in a flux shape, a striped shielding mask is provided between the boron ion source and the silicon wafer, and the boron ion irradiation area is controlled using the width of the opening of the shielding mask. May be.

  In the case of low energy irradiation, since the range from the surface of boron is short, the cross-sectional shape of the boron stop region 3 parallel to a plane perpendicular to the irradiation direction (a plane parallel to the surface in normal incidence) is approximately It becomes equal to the shape of the boron ion irradiation region.

The boron distribution in the N ⁺ silicon wafer 1 will be described in more detail. As shown in the lower part of FIG. 1, the boron distribution is substantially flat in the horizontal direction over the width of the boron ion irradiation region, and on both sides thereof. This produces a lateral spread of the implanted boron.

Further, as shown on the right side of FIG. 1, a boron concentration peak corresponding to the range of boron ions is generated at a shallow position from the surface in the vertical direction. In the annealing step, if boron activation heat treatment is performed on the boron implanted into the N ⁺ silicon wafer 1, the boron stop region 3 is changed to the P ⁺ type as shown by the right-downward hatching in FIG.

Next, the case where the high energy boron ion beam 2 is irradiated from the surface of the N ⁺ silicon wafer 1 will be described with reference to FIG. Since high if energy irradiation boron ion beam 2 in the projected range of the N ⁺ inside implanted boron silicon wafer 1 is long, it is possible to form a boron-stop region 3 on the back near the N ⁺ silicon wafer 1. 2 and 3, the same reference numerals are assigned to the portions corresponding to those in FIG.

As described above, since the boron distribution implanted into the N ⁺ silicon wafer 1 has a lateral spread, in order for the width of the boron stop region formed near the back surface to be equal to that in FIG. As shown by the broken line, the boron ion irradiation region width must be narrower than that in FIG.

When the boron stop region 3 is formed in the vicinity of the back surface of the N ⁺ silicon wafer 1 by performing high energy irradiation, a peak of the boron concentration is generated in the vicinity of the back surface as shown on the right in FIG. For this reason, boron ions accelerated to high energy simply pass through regions other than the boron stop region 3 enclosed between the broken lines in FIG. 2, and boron is hardly added. Therefore, if the boron activation heat treatment is subsequently performed, only the boron stop region 3 changes to P ⁺ as shown by the right-downward hatching in FIG.

Thus, if high energy irradiation is performed, a P ⁺ region can be formed at a deep position of the N ⁺ silicon wafer 1, but boron is not added in the middle from the surface to the P ⁺ boron stop region 3. The area in the middle cannot be set to P ⁺ .

As shown in FIG. 3 and the right side thereof, in order to form a striped P ⁺ boron implantation region 3a having a uniform width from the front surface to the back surface of the N ⁺ silicon wafer 1, acceleration energy of boron ions to be implanted is set. By changing continuously, the boron range inside the N ⁺ silicon wafer 1 must be changed to form a uniform boron distribution in the vertical direction.

  That is, since the lateral spread of the implanted boron becomes larger as the range becomes longer, the width of the boron ion irradiation region is controlled so that the acceleration energy is higher and the boron range is longer as shown in FIG. Thus, the concentration and width of the boron implantation region 3a are made uniform with respect to the vertical direction.

At this time, the boron range may be changed by continuously increasing the acceleration energy so that the boron implantation region 3a reaches the back surface from the front surface of the N ⁺ silicon wafer 1, or conversely, the acceleration energy is continuously increased. Alternatively, the boron implantation region 3 may reach the front surface from the back surface of the N ⁺ silicon wafer 1. By performing the activation heat treatment in this way, the boron implantation region 3 changes to P ⁺ and a super junction that crosses the N ⁺ silicon wafer 1 can be formed.

  In the first embodiment, the case where the boron ion irradiation region is formed in a slit shape and the width thereof is controlled has been described. However, the shape of the irradiation region is not necessarily a slit shape.

If the irradiation region has an arbitrary shape and the irradiation area is controlled in accordance with the acceleration energy of boron ions, the impurity boron concentration in the P ⁺ boron implantation region 3a is constant along the irradiation direction in FIG. In addition, the cross-sectional shape and cross-sectional area of the P ⁺ boron implantation region 3a in a plane perpendicular to the irradiation direction can be made constant along the irradiation direction.

Thus, by making the cross-sectional shape of the P ⁺ boron implantation region 3a arbitrary, the application range of the super junction to the device can be expanded. This also applies to each embodiment described below.

Next, a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, a method of forming a super junction by implanting boron ions using a resist mask will be described. In FIG. 4, 1 is an N ⁺ silicon wafer, 2 is a boron ion beam, 3a is a P ⁺ boron implantation region, and 4 is a photoresist.

  First, using PEP (Photo-Engraving-Process), a boron ion beam shielding mask made of photoresist 4 with the boron ion irradiation region as an opening is formed, and acceleration energy is continuously applied. The boron ion beam 2 is irradiated while being changed. At this time, boron ions may be irradiated in a lump using a wide variety of flux-like boron ions, or a boron ion beam may be scanned electrically or magnetically.

As described in the first embodiment, the boron energy within the N ⁺ silicon wafer 1 is controlled by controlling the acceleration energy, so that the P ⁺ boron implantation region 3a has a constant boron concentration in the vertical direction. As shown. At this time, the injection amount may be controlled simultaneously by controlling not only the acceleration energy but also the beam current.

Control of the acceleration energy and implantation amount of boron is selected so that the boron ion range distributions overlap with each other in the direction perpendicular to the irradiation surface to form a uniform distribution. Since the lateral extent of the poured boron increases as the range becomes longer due to the scattering of boron, the thickness of the N ⁺ silicon wafer 1 is such that the striped P ⁺ boron implantation region 3a overlaps in the vicinity of the back surface. Is selected.

If the boron activation heat treatment is subsequently performed, the boron implantation region 3a indicated by the right-downward hatching in FIG. 4 is changed to the P ⁺ type, and a super junction across the N ⁺ silicon wafer 1 can be formed.

Thus, if the N ⁺ drain region described above with reference to FIG. 7 is formed on the back surface of the N ⁺ silicon wafer 1 by diffusion or ion implantation, the width of the P ⁺ boron implantation region is not necessarily as shown in FIG. Even if it is not constant in the depth direction, a good low-loss power semiconductor device can be formed.

Incidentally, in the annealing step after the boron ion implantation, to produce a horizontal spread by diffusion of boron, but the overlap is further increased at the rear surface near the P ⁺ boron implanted region 3a, the rear surface of the N ⁺ drain of the N ⁺ silicon wafer 1 If the region and the N ⁺ region of FIG. 4 left in the triangle in the wafer are sufficiently connected, the characteristics of the low-loss power semiconductor device will not be greatly impaired. (See description of FIG. 5D).

Next, a third embodiment of the present invention will be described with reference to FIG. In the third embodiment, a method for forming a super junction by ion implantation of boron and phosphorus using an inversion mask will be described. In FIG. 5A, 1a is a silicon wafer, 2 is a boron ion beam, 3a is a P ⁺ boron implantation region, and 4 is a photoresist.

As shown in FIG. 5A, the silicon wafer 1a is irradiated with the boron ion beam 2 while continuously changing the acceleration energy using the shielding mask made of the photoresist 4 as in the second embodiment. In this manner, a P ⁺ boron implantation region 3a indicated by a right-down hatch is formed inside the silicon wafer 1a.

  Next, as shown in FIG. 5B, a shielding mask made of a photoresist 4a having an opening portion and a shielding portion that are opposite to each other with respect to the photoresist 4 is formed on the silicon wafer 1a using PEP. As this shielding mask, a photomask having a positive / negative inverted structure is prepared in advance, and may be formed on the silicon wafer 1a using the same photoresist, or the photoresist positive using the same photomask. Alternatively, it may be formed by inverting the negative.

Subsequently, the phosphorous ion beam 2a is irradiated from the opening of the shielding mask made of the inverted photoresist 4a while continuously changing the acceleration energy, and the N ⁺ phosphorus implantation region shown by the left-downward hatching in FIG. 3b is formed. Here, in both the previous P ⁺ boron implantation region 3a and the subsequent N ⁺ phosphorus implantation region 3b, the lateral spread of the implanted ions becomes larger as the range becomes longer. Compensation regions 3c are formed which overlap with each other as shown by the solid and broken cross hatches in FIG.

Here, if an activation heat treatment of the implanted boron and phosphorus is performed, the boron implantation region changes to P ⁺ , the phosphorus implantation region changes to N ^+, and the compensation region 3c in which both lateral spreads overlap the P ^{A +} / N ⁺ junction surface is formed, and the boron implantation region side is a P ⁺ region compensated with phosphorus, and the phosphorus implantation region side is an N ⁺ region compensated with boron.

The shape of the super junction thus formed is shown in FIG. The compensated P ⁺ region 3a ′ and the compensated N ⁺ region 3b ′ that have completed the activation heat treatment are regions each having a constant width and a substantially uniform concentration in the depth direction.

Subsequently, phosphorus or the like is diffused or ion-implanted to form the N ⁺ drain region 5 and the N ⁺ source region 6 as shown in FIG. 5D, and further, the compensated N connected to the N ⁺ drain region 5 is formed. ^A gate electrode 7 is formed through a gate insulating film (not shown) so as to cover the compensated P ⁺ region 3a ′ exposed on the substrate surface between the ⁺ region 3b ′ and the N ⁺ source region 6. Next, when the source electrode S and the drain electrode D are formed, the intended device structure is completed.

In this way, if the surface of the compensated P ⁺ region 3a ′ exposed on the substrate surface is inverted to the N channel, it can be operated as an NMOS type device. That is, in the device shown in FIG. 5D, the drain junction surface to which a high voltage is applied is composed of a super junction composed of a P ⁺ region 3a ′ and an N ⁺ region 3b ′ extending perpendicularly to the wafer surface. Therefore, the on-resistance is small.

Further, since the drain depletion layer extends along the super junction through the inside of the N ⁺ region 3b ′ and reaches the N ⁺ drain region 5, the drain depletion layer operates as an NMOS type low loss power semiconductor device having a high breakdown voltage. There are features. In the above description, if the P-type and N-type are inverted, a PMOS-type low-loss power semiconductor device can be formed in the same manner.

Next, a fourth embodiment of the present invention will be described with reference to FIG. In the fourth embodiment, a method of forming a super junction by irradiating a P ⁺ silicon ingot with a neutron beam through a lead mask and changing silicon atoms to phosphorus atoms by a nuclear reaction will be described.

In FIG. 6, 10 is a nuclear reactor, 11 is a fast neutron beam generated from the reactor, 12 is a moderator (water) of the fast neutron beam, 13 is a thermal neutron beam that has passed through the moderator, and 14 is a neutron beam made of a lead mask. , 15 is a collimated neutron beam, and 16 is a P ⁺ silicon ingot.

In the apparatus configuration shown in FIG. 6, a P ⁺ silicon ingot 16 is placed so that the growth axis direction of the ingot and the irradiation direction of the neutron beam are parallel, and the collimated neutron beam 15 is irradiated through the lead mask 14. Then, silicon atoms are changed to phosphorus atoms by the nuclear reaction, and N ⁺ regions 18 are alternately formed in the P ⁺ regions 17 (part of the P ⁺ silicon ingot).

  The neutron beam passes the fast neutron beam 11 generated by nuclear fission through the moderator 12 (water) to form a low-energy thermal neutron beam 13 and increases the cross-sectional area of the nuclear reaction.

The striped N ⁺ region 18 is formed by disposing a striped lead mask 14 that completely absorbs neutrons on the surface of a P ⁺ silicon ingot 16 and making the thermal neutron beam 13 into a collimated neutron beam 15. Is done. At this time, the thickness of the lead sufficiently absorbs neutrons, the passing neutron rays are sufficiently parallel inside the P ⁺ silicon ingot 16, and the width of the formed N ⁺ type region 18 is uniform. Selected.

Since the transmittance of the neutron beam is high, an N ⁺ region 18 having a uniform width can be formed in the entire P ⁺ silicon ingot 16. Then, if the wafer is cut out at a right angle to the irradiation direction of the neutron beam (the growth axis direction of the ingot), a wafer having a number of super junctions in the direction perpendicular to the wafer surface can be formed in a lump.

The present invention is not limited to the above embodiment. For example, in the first and second embodiments, the case where boron is implanted as a P ⁺ type impurity into an N ⁺ silicon wafer has been described. However, if a silicon wafer having an N ⁺ region is used, silicon having a super junction region is similarly provided. A wafer can be obtained.

  It goes without saying that a similar super junction can be formed by injecting impurities of the second and first conductivity types into the first and second conductivity type silicon wafers, respectively.

In the fourth embodiment, if the P ⁺ silicon ingot is a silicon ingot having a P ⁺ region, a silicon ingot having a super junction region can be obtained.

The direction of neutron irradiation is parallel to the growth axis of the silicon ingot. However, a super junction is formed by irradiating a collimated neutron beam from any direction to a silicon ingot having a P ⁺ region. Can be formed.

In the fourth embodiment, the case where P ⁺ silicon is irradiated with a neutron beam has been described. However, the present invention is not necessarily limited to silicon. A similar method can be used for a semiconductor material made of a group 4 element such as germanium or silicon carbide. Various other modifications can be made without departing from the scope of the present invention.

The figure which shows the boron distribution of the low energy ion irradiation which concerns on the 1st Embodiment of this invention. The figure which shows the boron distribution of the high energy ion irradiation which concerns on the 1st Embodiment of this invention. The figure which shows the manufacturing method of the super junction using the ion irradiation which concerns on the 1st Embodiment of this invention. The figure which shows the manufacturing method of the super junction using the shielding mask which concerns on the 2nd Embodiment of this invention. The figure which shows the manufacturing method of the super junction using the inversion shielding mask which concerns on the 3rd Embodiment of this invention. The figure which shows the manufacturing method of the super junction using the neutron beam irradiation which concerns on the 4th Embodiment of this invention. The figure which shows an example of the manufacturing method of the conventional super junction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... N ⁺ silicon wafer, 1a ... Silicon wafer, 2 ... Boron ion beam, 2a ... Phosphorus ion beam, 3 ... P ⁺ boron stop area | region, 3a ... P ⁺ boron implantation area | region, 3a '... Compensated P ⁺ area ^| region, 3b ... N ⁺ phosphorus implantation region, 3b '... compensated N ⁺ region, 3c ... compensation region, 4 ... photoresist, 4a ... inverted photoresist, 5 ... N ⁺ drain region, 6 ... N ⁺ source region, 7 ... gate electrode, 10 ... nuclear reactor, 11 ... fast neutron beam, 12 ... moderator, 13 ... thermal neutron beam, 14 ... lead mask, 15 ... collimated neutron beam, 16 ... P ⁺ silicon ingot, 17 ... P ⁺ Region, 18 ... N ⁺ region, 101 ... N ⁺ drain region, 102 ... N-type silicon wafer, 103 ... trench, 104 ... P ⁺ ion implantation, 105 ... N ⁺ silicon selective crystal growth, 106 ... cut surface, 107 ... P ⁺ Region 108... N ⁺ source region 109 109 gate electrode.

Claims (10)

In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The area of the irradiation region of the impurity ions is controlled by electrical or magnetic scanning of the impurity ions so that the first conductivity type regions and the second conductivity type regions are alternately arranged with junctions formed. And controlling the acceleration energy of the impurity ions and the area of the irradiation region to reduce the area of the irradiation region in accordance with an increase in the acceleration energy. In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The area of the irradiation region of the impurity ions is controlled by electrical or magnetic scanning of the impurity ions so that the first conductivity type regions and the second conductivity type regions are alternately arranged with junctions formed. And controlling the acceleration energy of the impurity ions and the area of the irradiation region to increase the area of the irradiation region according to a decrease in the acceleration energy. In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The area of the irradiation region of the impurity ions is controlled by electrical or magnetic scanning of the impurity ions so that the first conductivity type regions and the second conductivity type regions are alternately arranged with junctions formed. The method for manufacturing a semiconductor device is characterized in that the acceleration energy of the impurity ions and the area of the irradiation region are controlled by increasing the opening area of the mask in accordance with a decrease in the acceleration energy. In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The area of the irradiation region of the impurity ions is controlled by electrical or magnetic scanning of the impurity ions so that the first conductivity type regions and the second conductivity type regions are alternately arranged with junctions formed. The method for manufacturing a semiconductor device is characterized in that the acceleration energy of the impurity ions and the area of the irradiation region are controlled by decreasing the opening area of the mask in accordance with the increase of the acceleration energy. In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The area of the irradiation region of the impurity ions forms an ion beam made of impurity ions so that the first conductivity type region and the second conductivity type region are alternately arranged with junctions formed, The irradiation region is controlled by scanning the ion beam in the vertical direction and the horizontal direction, and the acceleration energy of the impurity ions and the area of the irradiation region are controlled according to the increase of the acceleration energy. A method of manufacturing a semiconductor device, wherein In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The area of the irradiation region of the impurity ions forms an ion beam made of impurity ions so that the first conductivity type region and the second conductivity type region are alternately arranged with junctions formed, The irradiation region is controlled by scanning the ion beam in the vertical direction and the horizontal direction, and the acceleration energy of the impurity ions and the area of the irradiation region are controlled according to the decrease of the acceleration energy. A method of manufacturing a semiconductor device, wherein In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The area of the irradiation region of the impurity ions forms an ion beam made of impurity ions so that the first conductivity type region and the second conductivity type region are alternately arranged with junctions formed, The irradiation area is controlled by scanning the ion beam in the vertical direction and the horizontal direction, and the acceleration energy of the impurity ions and the area of the irradiation area are controlled according to the decrease in the acceleration energy. A method of manufacturing a semiconductor device, wherein In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The area of the irradiation region of the impurity ions forms an ion beam made of impurity ions so that the first conductivity type region and the second conductivity type region are alternately arranged with junctions formed, The irradiation area is controlled by scanning in the vertical and horizontal directions with the ion beam, and the acceleration energy of the impurity ions and the area of the irradiation area are controlled according to the increase of the acceleration energy. A method of manufacturing a semiconductor device, wherein In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The area of the irradiation region of the impurity ions is controlled by a mask that shields the impurity ions so that the first conductivity type regions and the second conductivity type regions are alternately arranged with junctions formed , The method for manufacturing a semiconductor device, wherein the acceleration energy of the impurity ions and the area of the irradiation region are controlled by changing an opening area of the mask in accordance with a change in the acceleration energy. In the method of manufacturing a semiconductor device, by selectively irradiating a semiconductor with impurity ions, a first conductivity type region and a second conductivity type region alternately arranged with respect to a wafer surface are formed in the semiconductor.
The same mask is formed on the semiconductor using a positive resist and a negative resist that are in an inversion relationship with each other so that the first conductivity type region and the second conductivity type region are alternately arranged with junctions. A method of manufacturing a semiconductor device, wherein a pattern mask is formed to form a masking mask for the impurity ions, and an irradiation region of the impurity ions is determined using the masking mask.

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