JPS5669823A - Impurity-adding method for semiconductor - Google Patents

Impurity-adding method for semiconductor

Info

Publication number
JPS5669823A
JPS5669823A JP14509179A JP14509179A JPS5669823A JP S5669823 A JPS5669823 A JP S5669823A JP 14509179 A JP14509179 A JP 14509179A JP 14509179 A JP14509179 A JP 14509179A JP S5669823 A JPS5669823 A JP S5669823A
Authority
JP
Japan
Prior art keywords
substrate
density
semiconductor
density distribution
ray
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14509179A
Other languages
Japanese (ja)
Inventor
Masashi Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14509179A priority Critical patent/JPS5669823A/en
Publication of JPS5669823A publication Critical patent/JPS5669823A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To obtain the impurities having an optional density distribution in a semiconductor by a method wherein the surface of the semiconductor is covered by an absorbing material such as metal and the like, an aperture is made and a nuclear reaction is generated by irradiating a radiant ray. CONSTITUTION:The whole exposed surface of the semiconductor substrate 1, made of P type GaAs and the like, is covered by an absorbing material 2 consists of a Gd metal layer by performing a sputtering evaporation, and a pattern of slit-type 3 is made corresponding to the prescribed region. Then the substrate is placed in a nuclear reactor, a radiant ray 4 is irradiated by having a thermal neutron density of approximately 4X10<13> piece/cm<2>-second and the exposed region in the slit 3 of the substrate 1 is converted to an N type layer 5 having a carrier density of 1X10<17>/cm<2>. Thus a layer 5 having a steep carrier density distribution can be obtained without changing too much of the resistance value of the substrate 1. In this constitution, when a more steep density distribution is reguired, the radial ray 4 is formed into a beam-typed radial ray flux using a hollow collimator 6. Also an optional density can be obtained by selecting a desired thermal neutron density.
JP14509179A 1979-11-09 1979-11-09 Impurity-adding method for semiconductor Pending JPS5669823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14509179A JPS5669823A (en) 1979-11-09 1979-11-09 Impurity-adding method for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14509179A JPS5669823A (en) 1979-11-09 1979-11-09 Impurity-adding method for semiconductor

Publications (1)

Publication Number Publication Date
JPS5669823A true JPS5669823A (en) 1981-06-11

Family

ID=15377164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14509179A Pending JPS5669823A (en) 1979-11-09 1979-11-09 Impurity-adding method for semiconductor

Country Status (1)

Country Link
JP (1) JPS5669823A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006222444A (en) * 2006-03-27 2006-08-24 Toshiba Corp Manufacturing method of semiconductor device
JP2008277657A (en) * 2007-05-02 2008-11-13 Sumitomo Electric Ind Ltd Semiconductor substrate and its manufacturing method
USRE41181E1 (en) 1999-06-28 2010-03-30 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE41181E1 (en) 1999-06-28 2010-03-30 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
JP2006222444A (en) * 2006-03-27 2006-08-24 Toshiba Corp Manufacturing method of semiconductor device
JP4580886B2 (en) * 2006-03-27 2010-11-17 株式会社東芝 Manufacturing method of semiconductor device
JP2008277657A (en) * 2007-05-02 2008-11-13 Sumitomo Electric Ind Ltd Semiconductor substrate and its manufacturing method

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