JPS5669825A - Impurity-adding method for compound semiconductor - Google Patents

Impurity-adding method for compound semiconductor

Info

Publication number
JPS5669825A
JPS5669825A JP14509379A JP14509379A JPS5669825A JP S5669825 A JPS5669825 A JP S5669825A JP 14509379 A JP14509379 A JP 14509379A JP 14509379 A JP14509379 A JP 14509379A JP S5669825 A JPS5669825 A JP S5669825A
Authority
JP
Japan
Prior art keywords
compound semiconductor
generated
neuclear
elements
impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14509379A
Other languages
Japanese (ja)
Inventor
Masashi Yamaguchi
Kiyoshi Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14509379A priority Critical patent/JPS5669825A/en
Publication of JPS5669825A publication Critical patent/JPS5669825A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/261—Bombardment with radiation to produce a nuclear reaction transmuting chemical elements

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

PURPOSE:To obtain the impurity region without fluctuations in impurity distribution for the subject compound semiconductor by a method wherein radiant rays such as a thermal neutron, gamma rays and the like are irradiated on the compound semiconductor, portion of the semiconductor consisting elements is converted into a heterologous element which functions as donor impurities by a neuclear reaction and then an annealing is performed. CONSTITUTION:The compound semiconductor is consisted of two elements of mass numbers M1 and M2, and atomic numbers A and B, and therefore, the neuclear reactions shown by formulas I are generated by irradiating a thermal neutron and the neuclear reactions shown by formulas II are generated by irradiating gamma rays. Thus a portion of the semiconductors A and B is converted into heterologous elements A+1 and B+1, and the donor impurities having a uniform density are generated on the whole surface of an ingot. Also a density of 10<12>-10<20>cm<3> is obtained by adjusting the dose of radioactivity of the radiant rays, and the lattice defect, which is generated at the same time, is eliminated by performing an annealing.
JP14509379A 1979-11-09 1979-11-09 Impurity-adding method for compound semiconductor Pending JPS5669825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14509379A JPS5669825A (en) 1979-11-09 1979-11-09 Impurity-adding method for compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14509379A JPS5669825A (en) 1979-11-09 1979-11-09 Impurity-adding method for compound semiconductor

Publications (1)

Publication Number Publication Date
JPS5669825A true JPS5669825A (en) 1981-06-11

Family

ID=15377207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14509379A Pending JPS5669825A (en) 1979-11-09 1979-11-09 Impurity-adding method for compound semiconductor

Country Status (1)

Country Link
JP (1) JPS5669825A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5678499A (en) * 1979-11-27 1981-06-27 Mitsubishi Monsanto Chem Co Compound semiconductor ingot and its preparation
JP2013058626A (en) * 2011-09-08 2013-03-28 Advanced Power Device Research Association Manufacturing method of semiconductor substrate and semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CHEM SOL1DS *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5678499A (en) * 1979-11-27 1981-06-27 Mitsubishi Monsanto Chem Co Compound semiconductor ingot and its preparation
JP2013058626A (en) * 2011-09-08 2013-03-28 Advanced Power Device Research Association Manufacturing method of semiconductor substrate and semiconductor device

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