USRE41181E1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- USRE41181E1 USRE41181E1 US10/817,623 US81762304A USRE41181E US RE41181 E1 USRE41181 E1 US RE41181E1 US 81762304 A US81762304 A US 81762304A US RE41181 E USRE41181 E US RE41181E
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 68
- 239000010703 silicon Substances 0.000 claims abstract description 68
- 150000002500 ions Chemical class 0.000 claims abstract description 51
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- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 69
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 69
- 229910052796 boron Inorganic materials 0.000 description 69
- 238000000034 method Methods 0.000 description 18
- 238000005468 ion implantation Methods 0.000 description 11
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 7
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- 230000004913 activation Effects 0.000 description 6
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- 238000002513 implantation Methods 0.000 description 3
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/261—Bombardment with radiation to produce a nuclear reaction transmuting chemical elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Definitions
- a shield mask 4 intercepting boron-ion beam is formed which has opening portions allowing boron-ion irradiation. Onto its opening portions, the boron-ion beam 2 is irradiated with its acceleration energy being varied continuously. Then the boron-ion beam can be irradiated as a whole by the use of a wide flux beam. The boron-ion beam can either be swept electrically or magnetically. Also the sweeping can be performed by moving the N + silicon substrate 1 .
- PEP Photo Engraving Process
Abstract
A method of manufacturing a low power dissipation semiconductor power device is provided which is easy to perform and suitable for mass production. When a first and second conductivity-type regions are formed on a semiconductor substrate which is selectively irradiated by impurity ions, an excellent super junction is formed by controlling the ion acceleration energy and the width of each irradiated region so that the first and second conductivity-type regions may have a uniform impurity distribution and a uniform width along the direction of irradiation. Another method of manufacturing a low power dissipation semiconductor power device having an excellent super junction is provided which selectively irradiates a collimated neutron beam onto a P+ silicon ingot and forms an N+ region that has a uniform impurity distribution and a uniform width along the direction of irradiation in the P+ silicon ingot.
Description
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-181687, filed Jun. 28, 1999, the entire contents of which are incorporated herein by reference.
The present invention generally relates to a method of manufacturing semiconductor devices, and more particularly relates to a method of manufacturing low power dissipation semiconductor power devices.
Some of the low power dissipation semiconductor power devices of the prior art have a junction structure (hereafter referred to as “super junction”) consisting of a vertical junction group where a first conductivity-type region and a second conductivity-type region are alternatively arranged vertically to the surface of a silicon substrate.
There is a prior method of creating such super junction structure by repeating N− epitaxial growth and ion implantation. FIG. 1 provides a brief explanation of this manufacturing process. In FIG. 1 , a flow of the manufacturing process is shown in the right-hand part and cross sections of the silicon substrate at each step in the left-hand part.
As shown in FIG. 1 , an N+ silicon substrate 101 is prepared and on that an N− epitaxial layer 102 is grown. Then boron-ions are implanted by the use of an ion implantation mask (not shown) to form P+ regions 103 in the N− epitaxial layer 102. Subsequently, by the use of an inverted mask of the ion implantation mask, phosphorous ions are implanted in a region adjacent to the P+ regions 103 to form N+ regions 104.
These ion-implanted regions are activated by annealing (not shown) to provide the P+ regions 103 and N+ regions 104. Annealing can be performed either after each ion implantation or after all the implantations have been completed. In this way, a PN junction plane is formed as part of a super junction consisting of PN junctions vertically arranged to the surface of an epitaxial layer.
Next, another N− epitaxial layer 102 is grown and, as shown in the right-hand part of FIG. 1 , the steps from boron implantation to N− epitaxial growth are repeated. Then a vertical super junction is formed where PN-junction planes are alternatively created in the vertical direction to the wafer surface.
The N+ silicon substrate 101, which was used at an early step, will be a drain region of the low power dissipation semiconductor power device. Since the manufacturing method to be employed in the processes after the formation of a super junction is described later in FIG. 6D , detail explanation is not given here.
If a low power dissipation semiconductor power device having this super junction structure is manufactured to which high voltages are applied, since drain junction planes are formed by P+ and N+ regions that extend vertically to the wafer surface and a current path is created in the N+ layer in the inner bulk region of the silicon substrate, the low power dissipation semiconductor power device of NMOS-type shows a low ON resistance and a high drain withstand voltage.
A shortcoming in the above prior art is that such manufacturing method of repeating the epitaxial growth process to create low power dissipation semiconductor power devices is costly, difficult to implement and not suitable for mass production.
The present invention has been made to solve the above problem and its principal object is to provide a method of manufacturing low power dissipation semiconductor power devices having the super junction structure.
The present invention employs not the low-yield epitaxial growth process but a method suitable for mass production by irradiating particle beams such as an ion beam and a neutron beam onto semiconductor substrates to provide low power dissipation semiconductor power devices having the super junction structure at low cost and with ease.
To be more specific, the present invention is a semiconductor device manufacturing method of forming a second conductivity-type region by irradiating impurity ions selectively onto a first conductivity-type semiconductor substrate, wherein the above impurity ion irradiated region is restricted by a shield mask that intercepts the impurity ions and the acceleration energy of impurity ions is controlled so that the impurity concentration in the second conductivity-type region may be uniform along the direction of irradiation.
The present invention is a semiconductor device manufacturing method of forming at least one of a first conductivity-type region and a second conductivity-type region in the semiconductor substrate by irradiating impurity ions selectively onto the semiconductor substrate, wherein the impurity concentration is uniform along the direction of irradiation in the first and second conductivity-type regions and the impurity ion acceleration energy and the area of irradiated region are controlled to make the cross-sectional shape and the cross-section area of each of the first and second conductivity-type regions on planes vertical to the irradiation direction uniform along the direction of irradiation.
In a preferred embodiment of the present invention, the area of irradiated region is controlled by an electric sweeping or magnetic sweeping of the impurity ion beam, or by movement of the semiconductor substrate. In the control of the ion acceleration energy and the area of the irradiated region, the area of the irradiated region is changed according to changes in the ion acceleration energy.
Further, in another preferred embodiment of the present invention, the area of the irradiated region is controlled with a shield mask intercepting the impurity ions, and the acceleration energy and the area of the irradiated region are controlled by changing the aperture area of the mask according to changes in the acceleration energy.
The present invention is a semiconductor device manufacturing method of forming a first and second conductivity-type regions by irradiating impurity ions selectively onto a semiconductor substrate; wherein two shielding masks in a reversed imaging relation to each other are used to restrict the impurity ion irradiated regions so that the cross-sectional shape and the cross-section area of the first and second conductivity-type regions on planes vertical to the irradiation direction may be uniform in the direction of irradiation; and the impurity ion acceleration energy is controlled to make the impurity concentration in the first and second conductivity-type regions uniform in the direction of irradiation.
The present invention is a semiconductor device manufacturing method of forming an N+ region by selectively irradiating a neutron beam onto a P+ semiconductor ingot, wherein the incident angle of the neutron beam is collimated so that the cross-sectional shape and the cross-section area of the N+ region may be uniform in the direction of irradiation and so that the impurity concentration in the N+ region may be uniform in the direction of irradiation.
In a preferred embodiment of the present invention, the P+ ingot is made of one of silicon, germanium and silicon carbide, and the incident angle of the neutron beam is parallel to the direction of a growth axis of the P+ semiconductor ingot.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of the present invention which proceeds with reference to the accompanying drawings.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
Now referring in detail to the drawings, the embodiments of the present invention are explained. Referring to FIGS. 2A , 2B, 2C and FIGS. 3A , 3B, 3C, and FIGS. 4A , 4B, 4C, an example of the method forming a super junction by an ion implantation according to a first embodiment of the invention is explained.
As shown in FIG. 2A , when a low energy boron-ion beam 2 is irradiated onto an N+ silicon substrate 1, the implanted boron-ions lose energy within a short projection range in the N+ silicon substrate 1 and then form a boron stopped region 3 near the surface.
The boron distributions in a horizontal direction along the surface of the N+ silicon substrate 1 and in a vertical direction along its thickness become like those shown in FIGS. 2B and 2C , where the horizontal coordinate of the region irradiated by the ion beam 2 is shown along the X-axis, the vertical coordinate toward the bottom of the N+ silicon substrate along the Z-axis and the boron distribution along the Y-axis.
The region irradiated by a boron-ion beam is set to present a striped shape that has a width W on the substrate surface and normal to the page surface. The irradiation of the boron beam is performed to electrically sweeping the beam in the vertical and horizontal directions on the irradiated region.
The sweeping can also be performed by a magnetic sweep and movement of the N+ silicon substrate 1.
The control of the boron beam irradiation can also be performed by using a boron-ion beam which is broadened to a flux beam and a striped shape shield mask which is inserted between the boron-ion source and the silicon substrate, with the aperture width W of this shield mask being varied.
Since the projection range of the boron-ion beam 2, ranging from the surface of the N+ silicon substrate, is short in the case of irradiation with low energy, the cross-sectional shape of the boron stopped region 3, which is parallel to planes vertical to the ion incident direction (planes parallel to the surface, if the irradiation is made normal to the surface), becomes almost equal to the shape of the boron-ion irradiated region.
The distribution of boron in the N+ silicon substrate 1 is explained in further detail. As shown in FIG. 2B , the boron distribution shows an almost flat profile along the horizontal direction over the boron-ion irradiated region, accompanied by lateral broadening at the both ends of the irradiated region.
Also as shown in FIG. 2C , a peak in boron concentration appears at a shallow position from the surface of the N+ silicon substrate 1, of which depth is equal to the projection range of boron-ions. The implanted boron receives a heat treatment for activation in the subsequent annealing step, and the boron stopped region 3 turns into a P+ region, as shown by a right-down crossbatch in FIG. 2A.
In FIGS. 3A , 3B, 3C and FIGS. 4A , 4B, 4C, a boron-ion beam of high energy 2 is irradiated onto the surface of the N+ silicon substrate 1. As shown in FIG. 3A , since the projection range of the boron implanted into the N+ silicon substrate 1 is long in the case of a high energy irradiation of boron-ion beam 2, a boron stopped region 3 can be formed near the back surface of the N+ silicon substrate 1. In FIGS. 3A , 3B, 3C and 4A, 4B 4C, like numbers refer to like components as in FIGS. 2A , 2B and 2C.
As mentioned before, the boron distribution in the N+ silicon substrate 1 has lateral broadening. In order to make the width W of the boron stopped region 3 formed near the back surface in FIG. 3A equal to the width W of the boron stopped region 3 of FIG. 2A , the width W′ of the boron irradiation region should be narrower than that of FIG. 2A (W′<W), as indicated by the dashed lines in FIG. 3A.
When a boron stopped region 3 is formed near the back surface of the N+ silicon substrate 1 by a high energy irradiation, a peak in boron concentration appears near the back surface, as shown in FIG. 3C. In the regions other than the boron stopped region 3 between the dashed lines in FIG. 3C , accelerated high energy boron-ions simply pass through and almost no boron is doped there. Only the boron stopped region 3, therefore, turns into a P+ region, as shown by a right-down crossbatch in FIG. 3A , in the subsequent heat treatment for activation of implanted boron.
While a high energy irradiation, thus, can form a P+ region deep in the N+ silicon substrate 1, it cannot form a P+ region between the surface and the P+ boron stopped region 3, because boron is not doped there.
As shown in FIGS. 4A and 4C , in order to form a striped-shape P+ boron implanted region 3a having a uniform width W extending from the surface of the N+ silicon substrate 1 through its back surface, the acceleration energy of implanted boron-ions should be varied continuously to adjust the projection range of boron-ions in the N+ silicon substrate 1 so that a uniform boron distribution may be obtained in the vertical direction.
Namely, since the lateral broadening becomes larger as the projection range becomes larger, the width W′ of the boron irradiated region is controlled to be smaller (W′<W) as the acceleration energy is higher and the projection range is deeper, so that the boron concentration and the width W of the boron implanted region 3a may be uniform in a vertical direction, as shown in FIG. 4A.
The boron projection range may be controlled by gradually increasing the acceleration energy to extend from the surface of the N+ silicon substrate 1 through its back surface or may be controlled by gradually decreasing the acceleration energy to extend from its back surface to surface. In the subsequent heat treatment for activation of implanted boron, the boron implanted region 3a turns into a P+ region, and then a super junction can be formed across the N+ silicon substrate 1.
In the above first embodiment of the invention, the boron irradiated region has been formed to present a slit-like shape and its width W′ has been controlled. The shape of the irradiated region, however, is not necessary slit-like.
Whatever shape the irradiated area may present, by controlling the irradiated region according to the boron-ion acceleration energy, it is possible to make the boron concentration in the P+ boron implanted region 3a uniform along the direction of irradiation and make the cross-sectional shape and the cross-section area of the P+ boron implanted area 3a on planes perpendicular to the direction of irradiation uniform along the direction of irradiation.
In this way, any arbitrary shape can be taken as the cross-section of the P+ boron implanted region 3a, and thus the application range of super junction to devices can be widened. This is also true for the following embodiments of the invention.
Now referring to FIG. 5 , a second embodiment is explained, where a super junction is formed by a boron-ion implantation using a resist mask. In FIG. 5 , what denoted as 1 is an N+ silicon substrate, 2 a boron-ion beam, 3a a P+ boron implanted region and 4 a shield mask made of a photoresist.
First, using a Photo Engraving Process (PEP), a shield mask 4 intercepting boron-ion beam is formed which has opening portions allowing boron-ion irradiation. Onto its opening portions, the boron-ion beam 2 is irradiated with its acceleration energy being varied continuously. Then the boron-ion beam can be irradiated as a whole by the use of a wide flux beam. The boron-ion beam can either be swept electrically or magnetically. Also the sweeping can be performed by moving the N+ silicon substrate 1.
As described in the first embodiment, the boron projection range in the N+ silicon substrate 1 is controlled to provide a uniform concentration of boron vertically in the P+ boron implanted region 3a. Then not only the acceleration energy but also the beam current can be controlled to adjust the dose amount.
The boron acceleration energy and its dose amount are controlled so that the boron-ion projection ranges may overlap each other to provide a uniform boron distribution in the vertical direction in the N+ silicon substrate 1. Since the lateral broadening become larger by boron scattering as the projection range becomes deeper, the thickness of the N+ silicon substrate 1 should be chosen so that the striped-shape P+ boron implanted regions 3a may not overlap each other near the back surface of the substrate.
In the subsequent heat treatment for activation of implanted boron, the boron implanted region 3a, shown by a right-down hatch in FIG. 5 , turns into a P+ region, and then a super junction is formed across the N+ silicon substrate 1.
If an N+ region (corresponding to 101 in FIG. 1), which will be a drain region of the low power dissipation semiconductor power device described in FIG. 1 , is formed in the back surface of the N+ silicon substrate 1 by diffusion or ion implantation, a low power dissipation semiconductor power device with an excellent performance can be yielded, even if the width W of its P+ boron implanted region is not uniform in the vertical direction as shown in FIG. 4A.
In the subsequent annealing process conducted after boron-ion implantation, boron presents lateral broadening due to diffusion and as a result P+ boron implanted regions 3a further approach each other near the back surface. However, if the N+ drain region and the N+ region, which is left as a triangle area in the silicon wafer in FIG. 5 , are well connected, the performance of the low power dissipation semiconductor power device will not be significantly affected (see the explanation for FIG. 6D).
Now referring to FIGS. 6A to 6D, a third embodiment of the invention is described, which is a method of forming a super junction by boron and phosphorous implantation using a reversed mask. In FIG. 6A , denoted as 1a is a silicon substrate, 2 a boron-ion beam, 3a a P+ boron implanted region, and 4 a shield mask made of a photoresist.
As is the case with the second embodiment of the invention, using a shield mask 4 made of a photoresist, the boron-ion beam 2 is irradiated onto the silicon substrate 1a, with its acceleration energy being continuously varied, as sown in FIG. 6A. A P+ boron implanted region 3a shown by a right-down hatch, is thereby formed inside the silicon substrate 1a.
Next, another shield mask 4a made of a photoresist is formed by PEP on the silicon substrate 1a, of which opening portion and shielding portion are reversed each other of the mask 4, as shown in FIG. 6B. This shield mask 4a can be formed on the silicon substrate 1a by preparing a positive and negative image photomasks using the same photoresist or by using positive and negative types of photoresists using the same photomask.
As a next step, a phosphorous-ion beam 2a is irradiated through the opening portion of the inverted shield mask 4a made of the above photoresist, with its acceleration energy being varied continuously, and an N+ phosphorous implanted region 3b is formed as shown by a left-down hatch in FIG. 6B. As the ion projection range becomes deeper, the P+ boron implanted region 3a and the N+ phosphorous implanted region 3b becomes broader. Then toward the back surface, they come to overlap each other and a compensated region 3c is formed as shown by a crosshatch in FIG. 6B.
By a heat treatment for activation of implanted boron and phosphorous, the boron implanted region 3a and the phosphorous implanted region 3b turn into P+ and N+, respectively. In the compensated region 3c, where the above two regions overlap each other, a P+/N+ junction plane is formed along the ridge. The boron implanted region becomes a P+ region compensated by phosphorous and the phosphorous region becomes an N+ region compensated by boron.
As a next step, phosphorous is diffused or implanted, and an N+ drain region 5 and an N+ source region 6 are formed as shown in FIG. 6D. Further, a gate electrode 7 is formed via a gate insulating film (not shown) so that it may cover the compensated N+ region 3b′ connected to the N+ drain region 5 and the compensated P+ region 3a′ exposed on the substrate surface. Finally, when the source electrode S and the drain electrode D are formed, the desired low power dissipation semiconductor power device is completed.
In this way, if the surface of compensated P+ region 3a′, which is exposed on the surface of silicon substrate 1a, is inverted to a N-type channel, the semiconductor device operates as an NMOS-type device. In other words, the low power dissipation semiconductor power device in FIG. 6D has a small ON resistance because it has a drain junction plane, to which high voltages are applied, made of a super junction consisting of the P+ region 3a′ and N+ region 3b′ which extend in a direction perpendicular to the wafer surface.
Further, since the drain depletion region extends to N+ drain region 5 through N+ region 3b′ along the super junction, this NMOS-type low power dissipation semiconductor power device has a large withstand voltage. It is also obvious that if the above N+ regions are replaced by P+ regions a PMOS-type low power dissipation semiconductor power device is obtained.
Now referring to FIG. 7 , a forth embodiment of the invention is explained. The forth embodiment describes a method of forming a super junction in which a P+ silicon ingot is irradiated by a neutron beam through a collimator made of lead to transmute silicon atoms into phosphorous atoms by a nuclear reaction.
In FIG. 7 , denoted as 10 is a nuclear reactor, 11 a high-speed neutron beam, 12 a moderator (water) for the high-speed neutron beam, 13 a thermal neutron beam after passing through the moderator, 14 a lead collimator, 15 a collimated neutron beam, and 16 a P+ silicon ingot.
By the neutron beam irradiation shown in FIG. 7 , a super junction structure is formed in which a P+ region 17 (part of the P+ silicon ingot) and an N+ region 18 are alternatively piled up. The P+ silicon ingot 16 is placed as its direction of growth axis becomes parallel with the neutron beam irradiation direction. The collimated neutron beam 15, which has been collimated via the collimator 14, is irradiated to transmute part of silicon atoms into phosphorous atoms by a nuclear reaction.
The high-speed neutron beam 11 turns into the low energy thermal neutron beam 13, passing through the moderator 12 (water) to raise the collision cross section during nuclear reaction.
Stripes of N+ regions 18 are formed by the collimated neutron beam 15, which is made by passing the thermal neutron beam 13 through the collimator 14 where stripes of lead layers are mounted that completely absorb neutrons. Then the thickness of each lead layer is determined, so that neutrons are absorbed sufficiently, the neutron beams become parallel to each other in the P+ silicon ingot 16, and the widths of formed N+ regions 18 become uniform.
Since neutron beams have a high transmission coefficient and a small broadening, they are capable of forming N+ regions 18 of a uniform width over the P+ silicon ingot 16. If this wafer is sliced in the direction vertical to the irradiation direction (namely, the growth axis of ingot), many silicon substrates each having a super junction formed to the direction vertical to surface are provided at a time.
Having described the principles of the invention in preferred embodiments, it is appreciated that the invention can be modified in arrangement and detail without departing from such principles. For example, although boron has been implanted as a P+ impurity in an N+ silicon substrate in the first and second embodiments of the invention, a silicon substrate is also obtained that has an N+ region as super junction if a silicon substrate having an N+ region is employed.
It is obvious that a similar super junction can be formed by implanting a second and first conductivity-type impurities into a first and second conductivity-type silicon substrates, respectively.
Likewise, in the forth embodiment of the invention, if the P+ silicon ingot is replaced by a silicon ingot having a P+ region, a silicon ingot is obtained that has the P+ region as a super junction.
Although the direction of neutron beam irradiation has been parallel to the growth axis of the silicon ingot, a super junction can be formed in any silicon ingot having a P+ region by irradiating a collimated neutron beam from any direction.
In the forth embodiment of the invention, a neutron beam has been irradiated onto a P+ silicon ingot. However, the ingot is not necessarily made of silicon. The present invention allows the use of semiconductor ingots made of group IV elements such as germanium and silicon carbide. The present invention can be modified in arrangement and detail without departing from its principles.
As described above, by the method of forming a super junction according to the present invention, which does not use conventional complex processes like the epitaxial growth but use only efficient processes such as ion implantation and neutron beam irradiation, a super junction can be formed that has an arbitrary and uniform cross-section in the vertical direction. Specifically, the ion implantation and the neutron beam irradiation have the following advantages:
(1) Since a selective irradiation can be performed by an electric or magnetic sweep or movement of silicon substrate, the width of irradiation pattern can be continuously controlled according to changes in ion acceleration energy, and the vertical distribution of implanted ions shows an excellent uniformity.
(2) A second conductivity-type region is formed by changing only the acceleration energy after a first conductivity-type region is formed on a silicon substrate using a shield mask made of a photoresist having stripes of openings with a predetermined aperture width. Then although the vertical distribution of ions becomes relatively less uniform, a super junction can be formed using only the common ion implantation equipment and PEP without conducting ion beam sweep.
(3) If a first and second conductivity-type regions are formed by ion irradiation onto an intrinsic silicon substrate by the use of a shield mask made of a photoresist with striped shape openings of a specific width and another shield mask made of a photoresist in the reversed relation to the above photoresist, a uniform super junction is formed in the vertical direction because the lateral broadenings of ions compensate each other due to scattering.
(4) If a collimated neutron beam is irradiated onto a P+ silicon ingot, a uniform super junction is formed there, because the transmission coefficient of neutron beam is high enough to precisely transmute the irradiated region into an N+ region with less broadening. If the neutron beam is irradiated in parallel with the growth axis of the silicon ingot and silicon wafers are sliced out in the direction vertical to the growth axis as is the case with common silicon wafers, many silicon substrates each having a precision super junction over its surface can be produced at a time.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims (21)
1. A semiconductor device manufacturing method of forming a second conductivity-type region by irradiating impurity ions onto a first conductivity-type semiconductor substrate;
wherein the irradiating impurity ions is performed to form a junction structure comprising a vertical junction group where a first conductivity-type region and the second conductivity-type region are alternatively arranged vertically to a surface of the semiconductor substrate; and
wherein the impurity ion irradiated region is restricted by a shield mask intercepting said impurity ions and the impurity ion acceleration energy is controlled to provide a uniform impurity distribution in the direction of irradiation in said second conductivity-type region.
2. A semiconductor device manufacturing method of forming at least one of a first and second conductivity-type regions in a semiconductor substrate by selectively irradiating impurity ions onto said semiconductor substrate;
wherein the selectively irradiating impurity ions is performed to form a junction structure comprising a vertical junction group where the first conductivity-type region and the second conductivity-type region are alternatively arranged vertically to a surface of the semiconductor substrate; and
wherein the impurity distributions in said first and second conductivity-type regions are uniform in the direction of irradiation, and the impurity ion acceleration energy and the area of each region irradiated by said impurity ions are controlled so that the cross-sectional shape and cross-section area of said first and second conductivity-type regions on planes perpendicular to the direction of irradiation may be are uniform in the direction of irradiation.
3. The semiconductor device manufacturing method according to claim 2 , wherein the control of the area of said irradiated region comprises the steps of forming an ion beam made of impurity ions and sweeping the ion beam in the vertical and horizontal directions on the irradiated region, and the acceleration energy and the area of the irradiated region are controlled by changing the area of said irradiated region according to changes in said acceleration energy.
4. The semiconductor device manufacturing method according to claim 3 , wherein said impurity ion beam is electrically swept on the irradiated region.
5. The semiconductor device manufacturing method according to claim 3 , wherein said impurity ion beam is magnetically swept on the irradiated region.
6. The semiconductor device manufacturing method according to claim 3 , wherein said impurity ion beam is swept on the irradiated region by moving the semiconductor substrate.
7. The semiconductor device manufacturing method according to claim 3 , wherein the acceleration energy and the area of the irradiated region are controlled by decreasing the area of the irradiated region according to increase in the acceleration energy.
8. The semiconductor device manufacturing method according to claim 3 , wherein the acceleration energy and the area of the irradiated region are controlled by increasing the area of the irradiated region according to decrease in the acceleration energy.
9. The semiconductor device manufacturing method according to claim 2 , wherein the area of the irradiated region is restricted by a shield mask intercepting said impurity ions, and the acceleration energy and the area of the irradiated region are controlled by changing the area of each opening of said shield mask intercepting impurity ions according to changes in the acceleration energy.
10. The semiconductor device manufacturing method according to claim 9 , wherein the acceleration energy and the area of the irradiated region are controlled by decreasing the area of each opening of said shield mask intercepting impurity ions according to increase in the acceleration energy.
11. The semiconductor device manufacturing method according to claim 9 , wherein the acceleration energy and the area of the irradiated region are controlled by increasing the area of each opening of said shield mask intercepting impurity ions according to decrease in the acceleration energy.
12. The semiconductor device manufacturing method of forming a first conductivity-type region and a second conductivity-type region on a semiconductor substrate by irradiating impurity ions onto said semiconductor substrate;
wherein the irradiating impurity ions is performed to form a junction structure comprising a vertical junction group where the first conductivity-type region and the second conductivity-type region are alternatively arranged vertically to a surface of the semiconductor substrate; and
wherein the regions irradiated by impurity ions are restricted by impurity ion intercepting shield masks which are in an inverted imaging relation to each other so that the cross-sectional shape and the cross-section area of the first and second conductivity-type regions on planes perpendicular to the direction of irradiation may be are uniform along the direction of irradiation, and the impurity ion acceleration energy is controlled to make the impurity ion distributions in the first and second conductivity-type regions uniform along the direction of irradiation.
13. The semiconductor device manufacturing method according to claim 12 , wherein said impurity ion intercepting shield masks which are in an inverted imaging relation to each other are formed by printing the same mask patterns on the semiconductor substrate by the use of a positive resist and a negative resist.
14. A semiconductor device manufacturing method of forming an N+ region by irradiating a neutron beam onto a semiconductor ingot having a P+ region;
wherein the incident direction of said neutron beam is collimated to make the cross-sectional shape and the cross-section area of said N+ region on planes perpendicular to the direction of irradiation uniform along the direction of irradiation, and the impurity distribution in said N+ region is controlled to be uniform along the direction of irradiation.
15. The semiconductor device manufacturing method according to claim 14 , wherein the semiconductor having the P+ region is an P+ type semiconductor ingot and the incident direction of said neutron beam is parallel to the growth axis of said P+ type semiconductor ingot.
16. The semiconductor device manufacturing method according to claim 14 , wherein said semiconductor ingot is made of silicon.
17. The semiconductor device manufacturing method according to claim 14 , wherein said semiconductor ingot is made of germanium.
18. The semiconductor device manufacturing method according to claim 14 , wherein said semiconductor ingot is made of silicon carbide.
19. The semiconductor device manufacturing method according to claim 1 , wherein the first conductivity-type region includes plural portions, the second conductivity-type region includes plural portions, and the plural portions of the first conductivity-type region are alternatively arranged with the plural portions of the second conductivity-type region and vertically to the surface of the semiconductor substrate.
20. The semiconductor device manufacturing method according to claim 2 , wherein the first conductivity-type region includes plural portions, the second conductivity-type region includes plural portions, and the plural portions of the first conductivity-type region are alternatively arranged with the plural portions of the second conductivity-type region and vertically to the surface of the semiconductor substrate.
21. The semiconductor device manufacturing method according to claim 12 , wherein the first conductivity-type region includes plural portions, the second conductivity-type region includes plural portions, and the plural portions of the first conductivity-type region are alternatively arranged with the plural portions of the second conductivity-type region and vertically to the surface of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/817,623 USRE41181E1 (en) | 1999-06-28 | 2004-04-05 | Manufacturing method of semiconductor device |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18168799A JP3851744B2 (en) | 1999-06-28 | 1999-06-28 | Manufacturing method of semiconductor device |
| JP11-181687 | 1999-06-28 | ||
| US09/604,100 US6346464B1 (en) | 1999-06-28 | 2000-06-27 | Manufacturing method of semiconductor device |
| US10/817,623 USRE41181E1 (en) | 1999-06-28 | 2004-04-05 | Manufacturing method of semiconductor device |
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| Application Number | Title | Priority Date | Filing Date |
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| US09/604,100 Reissue US6346464B1 (en) | 1999-06-28 | 2000-06-27 | Manufacturing method of semiconductor device |
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| USRE41181E1 true USRE41181E1 (en) | 2010-03-30 |
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| US09/604,100 Ceased US6346464B1 (en) | 1999-06-28 | 2000-06-27 | Manufacturing method of semiconductor device |
| US10/817,623 Expired - Lifetime USRE41181E1 (en) | 1999-06-28 | 2004-04-05 | Manufacturing method of semiconductor device |
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| US09/604,100 Ceased US6346464B1 (en) | 1999-06-28 | 2000-06-27 | Manufacturing method of semiconductor device |
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| JP (1) | JP3851744B2 (en) |
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4033788A (en) * | 1973-12-10 | 1977-07-05 | Hughes Aircraft Company | Ion implanted gallium arsenide semiconductor devices fabricated in semi-insulating gallium arsenide substrates |
| JPS5669823A (en) | 1979-11-09 | 1981-06-11 | Nippon Telegr & Teleph Corp <Ntt> | Impurity-adding method for semiconductor |
| US4411708A (en) * | 1980-08-25 | 1983-10-25 | Trw Inc. | Method of making precision doped polysilicon vertical ballast resistors by multiple implantations |
| US4472871A (en) * | 1978-09-21 | 1984-09-25 | Mostek Corporation | Method of making a plurality of MOSFETs having different threshold voltages |
| US5141882A (en) * | 1989-04-05 | 1992-08-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor |
| US5438215A (en) * | 1993-03-25 | 1995-08-01 | Siemens Aktiengesellschaft | Power MOSFET |
| JPH10223896A (en) | 1997-02-10 | 1998-08-21 | Mitsubishi Electric Corp | Semiconductor device of high withstand voltage and its manufacture |
| US6028329A (en) * | 1997-01-28 | 2000-02-22 | Industrial Technology Research Institute | Bipolar junction transistor device and a method of fabricating the same |
| US6027953A (en) * | 1998-02-25 | 2000-02-22 | Industrial Technology Research Institute | Lateral PN arrayed digital X-ray image sensor |
| EP1003272A2 (en) * | 1998-11-17 | 2000-05-24 | Fuji Electric Co. Ltd. | Switching circuit |
| JP2000208527A (en) | 1999-01-11 | 2000-07-28 | Fuji Electric Co Ltd | Manufacture of super-joint semiconductor element and the super-joint semiconductor element |
| US6200883B1 (en) * | 1996-06-14 | 2001-03-13 | Applied Materials, Inc. | Ion implantation method |
-
1999
- 1999-06-28 JP JP18168799A patent/JP3851744B2/en not_active Expired - Fee Related
-
2000
- 2000-06-27 US US09/604,100 patent/US6346464B1/en not_active Ceased
-
2004
- 2004-04-05 US US10/817,623 patent/USRE41181E1/en not_active Expired - Lifetime
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4033788A (en) * | 1973-12-10 | 1977-07-05 | Hughes Aircraft Company | Ion implanted gallium arsenide semiconductor devices fabricated in semi-insulating gallium arsenide substrates |
| US4472871A (en) * | 1978-09-21 | 1984-09-25 | Mostek Corporation | Method of making a plurality of MOSFETs having different threshold voltages |
| JPS5669823A (en) | 1979-11-09 | 1981-06-11 | Nippon Telegr & Teleph Corp <Ntt> | Impurity-adding method for semiconductor |
| US4411708A (en) * | 1980-08-25 | 1983-10-25 | Trw Inc. | Method of making precision doped polysilicon vertical ballast resistors by multiple implantations |
| US5141882A (en) * | 1989-04-05 | 1992-08-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor |
| US5438215A (en) * | 1993-03-25 | 1995-08-01 | Siemens Aktiengesellschaft | Power MOSFET |
| US6200883B1 (en) * | 1996-06-14 | 2001-03-13 | Applied Materials, Inc. | Ion implantation method |
| US6028329A (en) * | 1997-01-28 | 2000-02-22 | Industrial Technology Research Institute | Bipolar junction transistor device and a method of fabricating the same |
| JPH10223896A (en) | 1997-02-10 | 1998-08-21 | Mitsubishi Electric Corp | Semiconductor device of high withstand voltage and its manufacture |
| US6103578A (en) * | 1997-02-10 | 2000-08-15 | Mitsubishi Denki Kabushiki Kaisha | Method for forming high breakdown semiconductor device |
| US6027953A (en) * | 1998-02-25 | 2000-02-22 | Industrial Technology Research Institute | Lateral PN arrayed digital X-ray image sensor |
| EP1003272A2 (en) * | 1998-11-17 | 2000-05-24 | Fuji Electric Co. Ltd. | Switching circuit |
| JP2000208527A (en) | 1999-01-11 | 2000-07-28 | Fuji Electric Co Ltd | Manufacture of super-joint semiconductor element and the super-joint semiconductor element |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080303114A1 (en) * | 2007-06-06 | 2008-12-11 | Denso Corporation | Semiconductor device having P-N column layer and method for manufacturing the same |
| US8097511B2 (en) * | 2007-06-06 | 2012-01-17 | Denso Corporation | Semiconductor device having P-N column layer and method for manufacturing the same |
| US20120329233A1 (en) * | 2011-06-27 | 2012-12-27 | Ruei-Hao Huang | Wafer treatment method and fabricating method of mos transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3851744B2 (en) | 2006-11-29 |
| JP2001015448A (en) | 2001-01-19 |
| US6346464B1 (en) | 2002-02-12 |
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