JP7384106B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present disclosure relates to a method for manufacturing a semiconductor device.

In addition to stress inherent in the semiconductor wafer, compressive stress induced by ion implantation applied to the wafer during the manufacturing process of semiconductor devices causes large warpage in the semiconductor wafer. If the wafer is greatly warped, it will cause problems in transporting the wafer inside and outside the process equipment or between the equipment, fixing it within the equipment, and handling it. Furthermore, it causes non-uniformity in the resist shape in the photolithography process and non-uniformity in the thickness and quality of the oxide film or metal film formed on the wafer. In recent years, as wafers have become larger in diameter, it has become important to suppress wafer warpage.

In order to suppress this warping of the wafer, for example, as shown in Patent Document 1, it has been proposed to perform ion implantation through an implantation mask so that the back surface of the wafer has a geometric shape in plan view ( For example, see Patent Document 1). It has also been proposed to irradiate the wafer surface with laser light depending on the amount of warpage that occurs in the wafer.

International Publication No. 2016/017215

Local warpage may occur on the wafer, such as a steep warpage in a part of the wafer or a warp that protrudes on both sides of the wafer. In the conventional method, stress is uniformly induced on the front or back surface of the wafer, so that local warpage of the wafer cannot be sufficiently suppressed.

The present disclosure has been made to solve the above-mentioned problems, and its purpose is to obtain a method for manufacturing a semiconductor device that can suppress local warping of a SiC epitaxial substrate.

A method for manufacturing a semiconductor device according to the present disclosure includes a step of implanting impurity ions into a part of a first main surface or a second main surface of a SiC epitaxial substrate to form an impurity region; a step of measuring the warped shape of the epitaxial substrate; a step of deriving a region locally warped in the direction of the first main surface in the SiC epitaxial substrate as a warp suppressing ion implantation region; The method is characterized by comprising a step of selectively implanting warp suppressing ions into the warp suppressing ion implantation region.

In the present disclosure, a region locally warped in the direction of one main surface in a SiC epitaxial substrate is derived as a warp suppressing ion implantation region. In a region of the SiC epitaxial substrate that is locally warped in the direction of one main surface, tensile stress is generated on the other main surface side. Therefore, warp suppressing ions are selectively implanted into the warp suppressing ion implantation region on the other main surface of the SiC epitaxial substrate. When warp suppressing ions are implanted into a SiC epitaxial substrate, the volume of the implanted layer expands due to the packing effect of impurity atoms and generation of irradiation defects. As a result, compressive stress is induced parallel to the ion implantation plane. By offsetting this compressive stress and the tensile stress existing in the SiC epitaxial substrate, local warpage of the SiC epitaxial substrate can be suppressed and flattened.

1 is a cross-sectional view showing a semiconductor device according to Embodiment 1. FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1. FIG. 3 is a flowchart of a method for manufacturing a semiconductor device according to Embodiment 1. FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment; FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment; FIG. FIG. 2 is a cross-sectional view showing a backside warpage suppressing ion implantation region and a front surface warping suppressing ion implantation region of a SiC epitaxial substrate. FIG. 3 is a plan view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 3 is a plan view showing a manufacturing process of the semiconductor device according to the first embodiment. 7 is a plan view showing a manufacturing process of a semiconductor device according to a second embodiment. FIG. FIG. 7 is a plan view showing a manufacturing process of a semiconductor device according to a third embodiment. FIG. 7 is a plan view showing a manufacturing process of a semiconductor device according to a fourth embodiment. FIG. 3 is an enlarged plan view showing a second metal mask. FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 12 is a plan view showing a backside warpage suppressing laser beam irradiation area according to Embodiment 6; FIG. 3 is a plan view showing a surface warpage suppressing laser beam irradiation area divided into three parts.

A method for manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings. Identical or corresponding components may be given the same reference numerals and repeated descriptions may be omitted.

Embodiment 1.
FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. The semiconductor device according to this embodiment is a SiC-MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

The SiC epitaxial substrate 1 has an n-type SiC epitaxial growth layer 3 formed on the Si atomic plane or the C atomic plane of an n-type SiC support substrate 2. In the SiC epitaxial substrate 1, the surface on which the SiC epitaxial growth layer 3 is formed is defined as the front surface of the substrate, and the surface opposite to the front surface is defined as the back surface of the substrate.

A plurality of p-type well regions 4 are selectively formed in the surface layer of the SiC epitaxial growth layer 3 . A p-type well contact region 5 is formed in the surface layer of each well region 4 . An n-type source region 6 is formed in the surface layer of the well region 4 so as to surround the well contact region 5 . Note that the conductivity types of the impurities in each structure may be reversed: n-type and p-type. A surface warpage suppressing ion implantation region 7 is present on a portion of the front surface of the SiC epitaxial substrate 1, and a back surface warpage suppressing ion implantation region 8 is present on a portion of the back surface.

FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. FIG. 2 is a plan view of the semiconductor device viewed from the well region 4 side. FIG. 1 corresponds to a cross section taken along line AA in FIG. A source region 6 surrounds a well contact region 5 having a substantially rectangular outer shape. A well region 4 surrounds the outer periphery of the source region 6 .

Although not shown, a gate insulating film is formed on a portion of the source region 6, the well region 4, and the SiC epitaxial growth layer 3 between adjacent well regions 4. A gate electrode is formed on the gate insulating film. A drain electrode is formed on the back surface of the SiC support substrate 2.

Next, a method for manufacturing a semiconductor device according to this embodiment will be described. FIG. 3 is a flowchart of a method for manufacturing a semiconductor device according to the first embodiment. 4 and 5 are cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view showing the backside warpage suppressing ion implantation region and the front surface warpage suppressing ion implantation region of the SiC epitaxial substrate. 7 and 8 are plan views showing the manufacturing process of the semiconductor device according to the first embodiment.

First, as shown in FIG. 4, the SiC epitaxial substrate 1 is formed by epitaxially growing the n-type SiC epitaxial growth layer 3 on the Si atomic plane or the C atomic plane of the n-type SiC support substrate 2 (step S1). The impurity concentration of the SiC epitaxial growth layer 3 is lower than the impurity concentration of the SiC support substrate 2. For example, when the impurity concentration of the SiC support substrate 2 is 1×10 ¹⁹ cm ⁻³ , the impurity concentration of the SiC epitaxial growth layer 3 is 1×10 ¹⁶ cm ⁻³ . As a dopant for the SiC support substrate 2 and the SiC epitaxial growth layer 3, nitrogen is used when the conductivity type is controlled to be n-type, and aluminum is used when the conductivity type is controlled to be p-type.

Next, by implanting p-type impurity ions into a part of the surface of the SiC epitaxial substrate 1 using an implantation mask patterned in a predetermined shape, as shown in FIG. A plurality of well regions 4 are selectively formed (step S2).

Next, the shape of warpage over the entire surface of the SiC epitaxial substrate 1 on which the well region 4 is formed is measured (step S3). As the warp shape measuring device, for example, a warp shape measuring device using oblique incidence interferometry can be used.

Next, as shown in FIG. 6, based on the measurement results, the back surface warpage suppressing ion implantation region 8 and the front surface warping suppressing ion implantation region 7 of the SiC epitaxial substrate 1 are derived (step S4). Specifically, in the SiC epitaxial substrate 1, a region that is locally warped by 5 μm or more in the front direction from the three-point reference plane is treated as a backside warpage suppressing ion implantation region 8, and a region that is locally warped by 5 μm or more in the backside direction from the three-point reference plane. This region is derived as the surface warpage suppressing ion implantation region 7.

Next, as shown in FIG. 7, a backside implantation mask 9 having an opening in the backside warpage suppressing ion implantation region 8 is formed on the backside of the SiC epitaxial substrate 1 (step S5). The backside injection mask 9 is a photoresist, a silicon oxide film, or the like.

The backside injection mask 9 is patterned by exposure and development to form an opening. At this time, the entire wafer is divided into a plurality of regions, and each region is exposed to light using a projection exposure device (stepper). Each area is an exposure area that the stepper can expose at one time. One area is a rectangle with a side length of 10 mm or more and 30 mm or less. The number of region divisions varies depending on the chip size and wafer size, and is, for example, 30 or more and 60 or less when using a 6-inch diameter wafer. Here, if one exposure area is divided into exposed parts and non-exposed parts, problems such as defocusing occur due to local changes in warpage within one exposure area. In addition, it is necessary to prepare a reticle corresponding to this in advance, which reduces processing efficiency. Therefore, among the plurality of regions, only the region in which the proportion of the back surface warpage suppressing ion implantation region 8 is 50% or more is subjected to full exposure, and the other regions are not exposed. For example, when the ratio of the back surface warpage suppressing ion implantation region 8 in one exposure region is 50%, the entire exposure region is opened.

Next, warp suppressing ions are implanted into the back surface of the SiC epitaxial substrate 1 using the back side implantation mask 9 (step S6). The ion implantation may be performed using a single implantation energy, or may be performed by changing the implantation energy stepwise, for example from high energy to low energy.

Note that the warp suppressing ion is an element such as carbon, silicon, hydrogen, helium, argon, etc. that is inactive and non-dopant with respect to SiC. However, as the warp suppressing ion, an element serving as a dopant such as aluminum, boron, phosphorus, or nitrogen may be used. Further, the warp suppressing ion may be a combination of the above elements. It is also possible to use an element that has the same conductivity type as the n-type SiC support substrate 2, for example, an n-type dopant such as phosphorus or nitrogen. Thereby, contact resistance when forming a drain electrode on the back surface of SiC epitaxial substrate 1 can be reduced. After that, the backside injection mask 9 formed on the backside of the SiC epitaxial substrate 1 is removed (step S7).

Next, as shown in FIG. 8, a surface implantation mask 10 having an opening in the surface warpage suppressing ion implantation region 7 is formed on the surface of the SiC epitaxial substrate 1 (step S8). Next, warp suppressing ions are implanted into the surface of the SiC epitaxial substrate 1 using the surface implantation mask 10 (step S9). The steps from the formation of the front-side implantation mask 10 to the warp-suppressing ion implantation are the same as the warp-suppressing ion implantation into the back surface of the substrate, so detailed descriptions of the steps will be omitted. However, since a p-type well region 4 exists in the surface layer of the SiC epitaxial growth layer 3, elements such as carbon, silicon, hydrogen, helium, and argon, which are inactive and non-dopants for SiC, are used as warpage suppressing ions. Use. Thereafter, the surface implantation mask 10 formed on the surface of the SiC epitaxial substrate 1 is removed (step S10).

In addition, as a result of measuring the warpage shape of the SiC epitaxial substrate 1, if the height of the warp protruding toward the front or back surface is low, for example, less than 5 μm at the maximum from the three-point reference plane, the warpage toward the corresponding main surface is determined. Mask formation for suppressing ion implantation and warpage suppressing ion implantation may be omitted.

Next, by implanting n-type impurity ions into a part of the surface of the SiC epitaxial substrate 1 using an implantation mask patterned in a predetermined shape, a plurality of n-type source regions are formed in the surface layer of the SiC epitaxial growth layer 3. 6 is selectively formed (step S11). After that, measurement of the warpage shape of the SiC epitaxial substrate 1, derivation of the front surface warpage suppressing ion implantation region 7 and the back surface warpage suppressing ion implantation region 8, warpage suppressing ion implantation via the back surface implantation mask 9 and the front surface implantation mask 10, and the back surface implantation mask Removal of 9 and surface implantation mask 10 is performed as described above. These steps are similar to the steps after forming the well region 4, and detailed descriptions of the steps will be omitted.

Next, a p-type well contact region 5 is formed in the surface layer of the SiC epitaxial growth layer 3. After that, measurement of the warpage shape of the SiC epitaxial substrate 1, derivation of the front surface warpage suppressing ion implantation region 7 and the back surface warpage suppressing ion implantation region 8, warpage suppressing ion implantation via the back surface implantation mask 9 and the front surface implantation mask 10, and the back surface implantation mask Removal of 9 and surface implantation mask 10 is performed as described above. These steps are similar to the steps after forming the well region 4, and detailed descriptions of the steps will be omitted.

Note that the order in which the well region 4, source region 6, and well contact region 5 are formed is not limited to the above. Further, in the above procedure, the warpage suppressing ion implantation was performed after forming each of the well region 4, the source region 6, and the well contact region 5, but the warping suppressing ion implantation does not necessarily need to be performed after each formation. Through the above steps, the semiconductor device according to this embodiment is manufactured.

As explained above, in this embodiment, a region locally warped in the direction of one main surface of SiC epitaxial substrate 1 is derived as a warp suppressing ion implantation region. In a region of SiC epitaxial substrate 1 that is locally warped in the direction of one main surface, tensile stress is generated on the other main surface side. Therefore, warp suppressing ions are selectively implanted into the warp suppressing ion implantation region on the other main surface of the SiC epitaxial substrate 1. When warp suppressing ions are implanted into the SiC epitaxial substrate 1, the volume of the implanted layer expands due to the packing effect of impurity atoms and generation of irradiation defects. As a result, compressive stress is induced parallel to the ion implantation plane. By offsetting this compressive stress and the tensile stress existing in the SiC epitaxial substrate 1, local warpage of the SiC epitaxial substrate 1 can be suppressed and flattened.

Embodiment 2.
FIG. 9 is a plan view showing the manufacturing process of the semiconductor device according to the second embodiment. In the first embodiment, warp suppressing ions were implanted using a surface implantation mask 10 in which the surface warp suppressing ion implantation region 7 was completely opened. In contrast, in this embodiment, a surface implantation mask 10 having an opening only in an ineffective region 11 around an effective region of a semiconductor element in which a well region 4 and the like are formed is formed on a SiC epitaxial substrate 1. Using this surface implantation mask 10, warp suppressing ions are implanted into the surface of the SiC epitaxial substrate 1.

As a result, warp suppressing ions are implanted only into the invalid region 11 in the surface warp suppressing ion implantation region 7 . Since the invalid region 11 is a region that does not affect the electrical characteristics of the semiconductor element, it is possible to suppress changes in the electrical characteristics of the semiconductor element due to the warpage suppressing ion implantation. For this reason, dopants active with SiC, such as aluminum, boron, phosphorus, and nitrogen, can also be used as warpage suppressing ions.

Embodiment 3.
FIG. 10 is a plan view showing the manufacturing process of the semiconductor device according to the third embodiment. A first metal mask 13 having an opening formed in the surface warpage suppressing ion implantation region 7 by changing the relative positions of the four metal plates 12 is placed on the surface of the SiC epitaxial substrate 1. Using this first metal mask 13, warp suppressing ions are implanted into the surface of the SiC epitaxial substrate 1. The same applies to the ion implantation to suppress warpage on the back surface of the SiC epitaxial substrate 1. This eliminates the need for the formation and removal steps of the backside injection mask 9 and the frontside injection mask 10, so that the time required for the wafer process can be reduced compared to the first embodiment. Although the first metal mask 13 is made up of four metal plates 12 in this embodiment, the number of metal plates 12 may be five or more. This allows for more fine control of the warpage suppressing ion implantation region.

Embodiment 4.
FIG. 11 is a plan view showing the manufacturing process of the semiconductor device according to the fourth embodiment. In the third embodiment, warp suppressing ions were implanted using the first metal mask 13 in which the warp suppressing ion implantation region was completely opened, but in the present embodiment, the second metal mask 14 was used as the second metal mask 14 in the third embodiment. Warp suppressing ions are implanted into the surface overlapping the opening of the metal mask 13 of No. 1. FIG. 12 is an enlarged plan view showing the second metal mask. The second metal mask 14 has an opening only in the invalid region 11. As a result, warp suppressing ions are selectively implanted only into the invalid region 11 in the surface warp suppressing ion implantation region 7 . Therefore, it is possible to suppress changes in the electrical characteristics of the semiconductor element due to warpage suppressing ion implantation. Note that in the second metal mask 14, in order to support the metal mask covering the effective area, it is necessary to leave a part of the metal mask in the area corresponding to the ineffective area 11 without opening.

Embodiment 5.
FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment. In this embodiment, similarly to Embodiment 1, well region 4, well contact region 5, and source region 6 are formed, and the warped shape of SiC epitaxial substrate 1 is measured. Next, as shown in FIG. 13, based on the measurement results, a backside warpage suppression laser beam irradiation area 15 and a front side warpage suppression laser beam irradiation area 16 of the SiC epitaxial substrate 1 are derived. Specifically, in the SiC epitaxial substrate 1, a region that is locally warped by 5 μm or more in the front direction from the three-point reference plane is treated as a backside warpage suppression laser beam irradiation region 15, which is locally warped by 5 μm or more in the backside direction from the three-point reference plane. The warped region is derived as a surface warp suppression laser beam irradiation region 16.

Next, laser light is selectively irradiated only to the back surface warpage suppression laser light irradiation region 15 on the back surface of the SiC epitaxial substrate 1, and only the surface warpage suppression laser light irradiation region 16 on the front surface is selectively irradiated with laser light. By irradiating this laser light, a laser-processed damaged layer is formed inside the SiC epitaxial substrate 1. For example, a KrF, XeCl excimer laser, or YAG laser is used.

When SiC epitaxial substrate 1 is irradiated with laser light, defects are generated and the volume of the laser-processed altered layer expands. As a result, compressive stress is induced parallel to the laser beam irradiated surface. By offsetting this compressive stress and the tensile stress existing in the SiC epitaxial substrate 1, local warpage of the SiC epitaxial substrate 1 can be suppressed and flattened. Since the steps of forming and removing the backside injection mask 9 and the front side injection mask 10 are not necessary, the time required for the wafer process can be reduced compared to the first embodiment.

Embodiment 6.
In this embodiment, similarly to Embodiment 5, well region 4, well contact region 5, and source region 6 are formed, and the warped shape of SiC epitaxial substrate 1 is measured. Next, the intensity distribution of tensile stress in the SiC epitaxial substrate 1 is derived from the measured warped shape. Then, the back surface warpage suppression laser light irradiation region 15 and the front surface warpage suppression laser light irradiation region 16 are each divided into a plurality of regions according to the strength of the tensile stress.

FIG. 14 is a plan view showing a backside warpage suppressing laser beam irradiation area according to the sixth embodiment. The back surface warpage suppression laser beam irradiation region 15 is divided into three regions 15a, 15b, and 15c depending on the strength of tensile stress. FIG. 15 is a plan view showing a surface warpage suppressing laser beam irradiation area divided into three parts. The surface warpage suppressing laser beam irradiation region 16 is divided into three regions 16a, 16b, and 16c depending on the strength of tensile stress.

Next, laser light is selectively irradiated only to the back surface warpage suppression laser light irradiation region 15 on the back surface of the SiC epitaxial substrate 1, and only the surface warpage suppression laser light irradiation region 16 on the front surface is selectively irradiated with laser light. At this time, the amount of laser light irradiation is increased in areas where the tensile stress intensity is higher. Specifically, the irradiation amount is adjusted by adjusting at least one of irradiation power [W], irradiation time, and irradiation density [%]. Note that the irradiation density is the ratio of the area actually irradiated with the laser to the area of the laser irradiation target region.

In this embodiment, the magnitude of the compressive stress introduced into the substrate plane by the laser beam can be changed depending on the intensity of the tensile stress within the substrate plane. Therefore, local warping of the SiC epitaxial substrate 1 can be suppressed more precisely than in the fifth embodiment, and the flatness can be further improved.

1 SiC epitaxial substrate, 4 well region (impurity region), 7 surface warpage suppression ion implantation region (warpage suppression ion implantation region), 8 back surface warpage suppression ion implantation region (warpage suppression ion implantation region), 9 back surface implantation mask (implantation mask ), 10 front surface injection mask (injection mask), 11 invalid area, 12 metal plate, 13 first metal mask, 14 second metal mask, 15 back surface warpage suppression laser light irradiation area (warpage suppression laser light irradiation area), 16 Surface warpage suppression laser light irradiation area (warp suppression laser light irradiation area), 15a, 15b, 15c, 16a, 16b, 16c area

Claims (9)

a step of implanting impurity ions into a part of the first main surface or the second main surface of the SiC epitaxial substrate to form an impurity region;
a step of measuring a warped shape of the SiC epitaxial substrate on which the impurity region is formed;
Deriving a region locally warped in the direction of the first main surface in the SiC epitaxial substrate as a warp suppressing ion implantation region;
A method for manufacturing a semiconductor device, comprising the step of selectively implanting warp suppressing ions into the warp suppressing ion implantation region of the second main surface. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the warpage suppressing ion is an element that is inactive and non-dopant with respect to SiC. The semiconductor according to claim 1 or 2, characterized in that a region locally warped by 5 μm or more in the direction of the first main surface from the three-point reference plane of the SiC epitaxial substrate is defined as the warp suppressing ion implantation region. Method of manufacturing the device. forming an implantation mask on the second main surface having an opening in the derived warpage suppressing ion implantation region;
implanting the warpage suppressing ions into the second main surface using the implantation mask;
4. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of removing the implantation mask after implanting the warpage suppressing ions. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the warpage suppressing ions are implanted only into an ineffective region around an effective region in which the impurity region is formed. arranging a first metal mask on the second main surface, the first metal mask having an opening in the warpage suppressing ion implantation region by changing the relative positions of the plurality of metal plates;
4. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of implanting the warpage suppressing ions into the second main surface using the first metal mask. implanting the warpage suppressing ions into the second main surface by overlapping the opening of the first metal mask with a second metal mask having an opening only in an ineffective region around the effective region in which the impurity region is formed; 7. The method for manufacturing a semiconductor device according to claim 6. a step of implanting impurity ions into a part of the first main surface or the second main surface of the SiC epitaxial substrate to form an impurity region;
a step of measuring a warped shape of the SiC epitaxial substrate on which the impurity region is formed;
Deriving a region locally warped in the direction of the first main surface in the SiC epitaxial substrate as a warp suppressing laser beam irradiation region;
A method for manufacturing a semiconductor device, comprising the step of selectively irradiating the warpage suppressing laser beam irradiation region of the second principal surface with a laser beam. 9. The semiconductor according to claim 8, wherein an intensity distribution of tensile stress of the SiC epitaxial substrate is derived from the measured warped shape, and the irradiation amount of the laser beam is increased in a region where the intensity of the tensile stress is higher. Method of manufacturing the device.

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