CN111564370A - Groove type power device and manufacturing method thereof - Google Patents
Groove type power device and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention relates to a groove type power device and a manufacturing method thereof. In the manufacturing method, the reference direction of the substrate is parallel to the second crystal direction, a first strip-shaped groove and a gate structure positioned in the first strip-shaped groove are manufactured in at least part of chip areas on the substrate, and the first strip-shaped groove extends in the direction parallel to the first crystal direction in the upper surface of the substrate. By fabricating the gate structure in a crystal direction different from the reference direction, the requirements for the substrate specification can be reduced. In the manufacturing process, in the coverage range of each exposure field, the included angle between the extending direction of the first strip-shaped groove in at least one chip area in the upper surface of the substrate and the extending direction of the first strip-shaped groove in another chip area in the upper surface of the substrate can be set to be a right angle, so that stress concentration can be relieved, and the risk of substrate warping can be reduced. The groove type power device is obtained by the method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a trench type power device and a manufacturing method thereof.
Background
With the development of semiconductor technology, the size of power devices is gradually reduced, and lateral devices are gradually replaced by vertical devices, which is an important development direction. Representative deep trench power devices include trench MOS transistors and Insulated Gate Bipolar Transistors (IGBTs). The grid of the deep groove power device is arranged in a groove in an epitaxial layer on a substrate, namely a groove grid structure is formed, and when the device is conducted, a conducting channel is formed in the epitaxial layer close to the grid.
In the prior art, when a deep trench power device is manufactured, a substrate with a proper specification is usually selected according to the design of the device. Taking a silicon substrate as an example, in order to obtain higher electron mobility, a device design is to make the extending direction of the groove in the chip unit cell in the upper surface of the substrate parallel to the crystal direction <100>, correspondingly, the substrate with the upper surface belonging to the crystal plane (100) and the direction from the center of the substrate to the positioning groove (notch) being the crystal direction <100> is selected, and meanwhile, when the groove is made, the mask plate for defining the groove is arranged to be the same as the notch in the groove pattern.
In addition, due to the application requirements, in practice, devices with different designs need to be manufactured, for example, another device design needs to make the extending direction of the groove in the chip unit cell in the upper surface of the base parallel to the crystal direction <110>, at this time, the specification of the substrate needs to be changed, for example, the upper surface belongs to a crystal plane (100), the direction from the center of the substrate to the positioning groove (notch) is the base of the crystal direction <110>, and during manufacturing, the mask used for defining the groove is set to be the orientation of the groove pattern consistent with the notch.
Different substrate specifications are selected according to device design, so that although the required trenches can be made, only one device design can be realized on one substrate specification, which is costly.
Disclosure of Invention
The invention provides a groove type power device and a manufacturing method thereof, aiming at saving the cost of a tape out and adjusting the groove design.
In one aspect, the present invention provides a method for manufacturing a trench type power device, including the steps of:
providing a substrate, wherein a positioning groove is formed in the edge of the substrate, a connecting line between the center of the substrate and the positioning groove is a reference direction, a first crystal orientation and a second crystal orientation which belong to different crystal orientation groups are periodically distributed around the center in the upper surface of the substrate, the reference direction is parallel to the second crystal orientation, and the substrate comprises a plurality of chip areas; and the number of the first and second groups,
and forming a first strip-shaped groove and a gate structure positioned in the first strip-shaped groove in the substrate of at least part of the chip area, wherein the first strip-shaped groove extends in a direction parallel to the first crystal direction in the upper surface of the substrate.
Optionally, the manufacturing method further includes: dicing the substrate to separate the respective chip regions to obtain a plurality of chips.
Optionally, the chip is a trench MOSFET or a trench IGBT.
Optionally, the upper surface of the substrate is a (100) crystal plane, and the first crystal orientation and the second crystal orientation are a <110> crystal orientation or a <100> crystal orientation, respectively.
Optionally, the first bar-shaped trench extends in the same direction parallel to the first crystal direction in the upper surface of the substrate, so as to form a straight trench; or, the first strip-shaped groove is bent and extended in different directions parallel to the first crystal direction in the upper surface of the substrate, so as to form a bent groove.
Optionally, the step of manufacturing the first power device includes:
sequentially forming a hard mask layer and a photoresist layer on the substrate;
exposing and developing the photoresist layer by using a step exposure mode, and etching the hard mask layer by using the patterned photoresist layer as a mask to pattern the hard mask layer; and the number of the first and second groups,
and etching the substrate by using the patterned hard mask layer as a mask, wherein at least part of the chip area forms the first strip-shaped groove within the coverage range of each exposure field.
Optionally, within the coverage of each exposure field, an included angle between the extending direction of the first bar-shaped groove in at least one chip region in the upper surface of the substrate and the extending direction of the first bar-shaped groove in another chip region in the upper surface of the substrate is a right angle.
Optionally, in the step of etching the substrate, second stripe-shaped trenches are formed in at least a part of the chip regions within the coverage of each exposure field, where the second stripe-shaped trenches extend in a direction parallel to the second crystal direction in the upper surface of the substrate.
Optionally, the second stripe-shaped trench extends in the same direction parallel to the second crystal direction in the upper surface of the substrate, so as to form a straight trench; or the second strip-shaped groove is bent and extended in different directions parallel to the second crystal direction in the upper surface of the substrate, so that a bent groove is formed.
In one aspect, the invention provides a trench type power device formed by the method.
The invention provides a method for manufacturing a groove type power device, wherein the reference direction of a substrate is parallel to a second crystal direction, first power devices are manufactured in at least partial chip areas on the substrate, the devices are provided with first strip-shaped grooves formed in the substrate and gate structures located in the first strip-shaped grooves, and the first strip-shaped grooves extend in the direction parallel to the first crystal direction in the upper surface of the substrate. By fabricating the trench gate structure in a crystal direction different from the reference direction, the requirements on the substrate specification can be reduced.
Furthermore, in the manufacturing method, the exposure field can be covered, and an included angle between the extending direction of the first strip-shaped groove manufactured in at least one chip area and the extending direction of the first strip-shaped groove in another chip area is a right angle, so that stress concentration generated in the manufacturing process is relieved, and the risk of substrate warping is reduced.
The groove type power device provided by the invention is formed by the method provided by the invention, and the requirement on the specification of the substrate can be reduced by manufacturing the groove gate structure in the direction different from the reference direction.
Drawings
Fig. 1 and 2 are schematic views of silicon wafers of two specifications, respectively.
Fig. 3 is a schematic plan view of a trench power device fabricated on a wafer using a conventional process.
Fig. 4 is a schematic flow chart of a method for manufacturing a trench type power device according to an embodiment of the present invention.
Fig. 5 is a schematic plan view of a trench type power device manufactured by the method for manufacturing a trench type power device according to the embodiment of the invention.
Fig. 6 to 10 are schematic groove layouts within an exposure field range according to a method for manufacturing a trench type power device in an embodiment of the present invention.
Fig. 11 to fig. 13 are schematic cross-sectional views of a manufacturing method of a trench type power device in the manufacturing process according to an embodiment of the present invention.
Description of reference numerals:
100-a substrate; 10-strip-shaped grooves; 20-a first stripe trench; 30-a second strip-shaped groove; 101-a gate oxide layer; 102-a gate; 103-a body region; 104-source region.
Detailed Description
The trench power device and the method for fabricating the same according to the present invention are further described in detail with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be understood that the drawings in the specification are in simplified form and are not to be taken in a precise scale, for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
For ease of description, some embodiments of the present application may use spatially relative terms such as "above …," "below …," "top," "below," and the like, to describe the relationship of one element or component to another (or other) element or component as illustrated in the various figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like in the following description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances.
Trench-type power devices are typically fabricated on the basis of silicon wafers, and useful substrate materials may also include germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other group iii, v compounds, and the like. The base may also be a silicon-on-insulator (SOI) substrate, etc., and certain doping ions may be implanted into the base according to design requirements to change electrical parameters, for example, to have N-type doping. The substrate may be formed with an epitaxial layer, and in this case, the upper surface of the substrate refers to an upper surface of the epitaxial layer.
The surface of the substrate usually belongs to a certain crystal plane family (such as the (100) crystal plane of a silicon wafer), and in the prior art, when a trench type power device is manufactured, the opening direction of a trench on the wafer is determined according to the device and the channel design, and the wafer with the corresponding specification is selected according to the device and the channel design for manufacturing. Common silicon wafers are specified by a crystal plane index of the upper surface of the wafer and a crystal orientation index of a reference direction defined by a notch (hereinafter, referred to as notch). During device fabrication, notch is also used to orient the pattern.
Fig. 1 and 2 are schematic views of silicon wafers of two specifications, respectively. The wafers of the specification lot shown in fig. 1 all have (100) crystal planes on their upper surfaces, and the reference direction corresponding to notch is the <100> crystal direction within the (100) crystal plane. For the wafers of the specification lot shown in fig. 2, the upper surfaces thereof are all (100) crystal planes, and the reference direction corresponding to notch is the <110> crystal direction within the (100) crystal plane. Herein, the (100) crystal plane represents one crystal plane of the {100} crystal plane family, and the <110> crystal orientation (here, represents one of the <110> crystal orientation family) occurs every 90 degrees along the circumference according to the radial direction of the wafer, and the <110> crystal orientation is rotated by 45 degrees (45 °) clockwise or counterclockwise, and is the <100> crystal orientation (here, represents one of the <100> crystal orientation family).
In general, in the manufacture of a deep trench power device, a mask for defining a trench is configured to make a trench pattern consistent with a notch orientation, for example, when a wafer with the specification as shown in fig. 1 is used for manufacturing, an extending direction of the trench is set to be parallel to a reference direction corresponding to the notch, and then a trench arrangement as shown in fig. 3 is formed in a substrate through a photolithography and etching process. Fig. 3 is a schematic plan view of a trench power device fabricated on a wafer using a conventional process. Referring to fig. 3, a wafer is provided with a plurality of chip regions arranged horizontally and vertically, each chip region is used for manufacturing a trench-type power device, and the trench-type power device has a trench 10 formed in a substrate and a gate structure formed in the trench 10. With the prior art, stripe-shaped trenches 10 extending in a direction parallel to the <100> crystal direction are formed in each chip region on the wafer (the number of chip regions and stripe-shaped trenches is shown as an example).
However, if a trench power device with a trench extending in a direction different from that of the trench power device shown in fig. 3 is to be manufactured, the conventional technology needs to replace the wafer specification for manufacturing. Therefore, only the device with the groove corresponding to the reference direction and the same crystal direction can be obtained on the substrate with one specification, and when a power device with a crystal direction design changed needs to be manufactured, the specification of the wafer needs to be changed, so that the cost is high.
Therefore, the method adjusts the arrangement direction of the grooves on the substrate by adjusting the arrangement of the groove patterns on the mask from the angle of adjusting the groove design, so that the arrangement of the grooves in the reference direction can be obtained on the substrate with the current specification, and the corresponding power device can be manufactured.
Fig. 4 is a schematic flow chart of a method for manufacturing a trench type power device according to an embodiment of the present invention. Referring to fig. 4, the method for manufacturing a trench power device according to the embodiment of the present invention includes the following first step S1 and second step S2:
a first step S1 of providing a substrate, where a positioning groove (notch) is disposed at an edge of the substrate, a connection line between a center of the substrate and the positioning groove is a reference direction, a first crystal orientation and a second crystal orientation belonging to different crystal orientation groups are periodically distributed around the center in an upper surface of the substrate, the reference direction is parallel to the second crystal orientation, and the substrate includes a plurality of chip regions;
a second step S2 is to form a first stripe-shaped trench and a gate structure in the first stripe-shaped trench in the substrate of at least a portion of the chip region, wherein the first stripe-shaped trench extends in a direction parallel to the first crystal direction in the upper surface of the substrate.
In the first step, the base is, for example, a single crystal silicon epitaxial substrate or a float-zone silicon substrate, and the upper surface of the base is, for example, the upper surface of the silicon epitaxial layer. The chip areas arranged on the substrate are respectively used for manufacturing the groove-type power device (or chip) in the corresponding range. The trench type power device is, for example, a trench type MOSFET or a trench type IGBT.
In the embodiment of the present invention, a silicon substrate is taken as an example, the upper surface of the substrate is, for example, a (100) crystal plane, the first crystal orientation is, for example, a <110> crystal orientation, and the second crystal orientation is, for example, a <100> crystal orientation, and as an example of a specification of the substrate, a reference direction corresponding to notch disposed at an edge of the substrate is, for example, parallel to the <100> crystal orientation (i.e., the second crystal orientation). The trench power device to be fabricated is, for example, an N-type power device, and the substrate has N-type doping.
In the second step, in order to fabricate the power device, a first stripe-shaped trench in which a gate structure is disposed is formed in the substrate corresponding to at least a portion of the chip region on the substrate. In an embodiment of the present invention, the first stripe-shaped trench extends in a direction parallel to the first crystal direction within the upper surface of the substrate. Since the first crystal orientation is periodically distributed around the center of the substrate in the upper surface of the substrate (e.g., in different radial directions of a silicon wafer, the <110> crystal orientation appears every 90 °), there may be two ways for the first stripe-shaped trench, one being to extend in the same direction parallel to the first crystal orientation in the upper surface of the substrate, thereby forming a straight trench; alternatively, the substrate may be bent and extended in different directions parallel to the first crystal direction in the upper surface of the substrate, thereby forming a curved groove.
Fig. 5 is a schematic plan view of a trench type power device manufactured by the method for manufacturing a trench type power device according to the embodiment of the invention. Referring to fig. 5, in an embodiment, by using the method for manufacturing a trench power device according to the embodiment of the present invention, in order to manufacture a trench power device on each chip area on a substrate 100, a plurality of first strip-shaped trenches 20 arranged in parallel are formed on each chip area. The first stripe-shaped groove 20 is not disposed in the reference direction corresponding to notch in the upper surface of the substrate 100, and extends in a direction parallel to a <110> crystal direction different from the crystal direction corresponding to the reference direction. Therefore, for the wafer specification shown in fig. 1, the method can be used for manufacturing a trench type power device with a trench parallel to the reference direction, and can also be used for manufacturing a trench forming a certain angle with the reference direction, and obtaining a trench type power device with a corresponding crystal orientation design, thereby reducing the requirement on the substrate specification. As shown in fig. 5, in the present embodiment, the extending direction of the first stripe-shaped groove 20 is parallel to the <110> crystal direction in the upper surface plane of the substrate 100. In further embodiments, the first stripe trench 20 may also extend in a crystal direction different from the crystal direction corresponding to the reference direction.
As an example, making the first stripe trench 20 described above may further include the following processes: firstly, sequentially forming a hard mask layer and a photoresist layer on the substrate 100; then, exposing and developing the photoresist layer by utilizing a stepping exposure mode, and etching the hard mask layer by utilizing the patterned photoresist layer as a mask to pattern the hard mask layer; then, the substrate 100 is etched using the patterned hard mask layer as a mask, so that the first stripe-shaped trench 20 is formed in at least a portion of the chip region within the coverage of each shot. Here, "step exposure" refers to exposing the photoresist layer on the substrate 100 region by region in accordance with a set exposure field range.
In the embodiment of the invention, the sizes of the exposure fields adopted in the successive exposure are the same, namely, the same number of chip areas can be covered. The design layout of the first strip-shaped grooves 20 of all chip areas of the substrate can be realized by designing the arrangement of the first strip-shaped grooves 20 of all chip areas in the coverage range of one exposure field. Fig. 6 to 10 are schematic groove layouts within an exposure field range according to a method for manufacturing a trench type power device in an embodiment of the present invention. The arrangement of the grooves within one exposure field is explained below.
Referring to fig. 6 to 10, in an embodiment of the invention, the substrate within one shot (shot) includes 16 chip (die) regions, the 16 chip regions are arranged in four rows and four columns, and gaps (scribes lines) left for subsequently dicing the substrate into single chips are disposed between the chip regions. In another embodiment, the number of chip regions in an exposure field range may also be greater than 16 or less than 16, such as 24, 36, 48, etc., which is not limited by the present invention.
Specifically, referring to fig. 5 and 6, in one embodiment, the first stripe-shaped trenches 20 may extend in the same direction parallel to the first crystal direction (e.g., the <110> crystal direction) in the upper surface of the substrate 100 in each chip region within the same exposure field range, thereby forming straight trenches. Also, since the first crystal orientation is periodically arranged around the center of the substrate, the first stripe-shaped trenches 20 formed in different chip regions may be non-parallel. Alternatively, as shown in fig. 6, in the same exposure field, the extending direction of the first linear groove 20 in at least one chip region in the upper surface of the substrate 100 is at a right angle to the extending direction of the first linear groove 20 in another chip region in the upper surface of the substrate 100, so that the substrate warpage risk can be reduced. As further described below.
It has been found that, for the trench design shown in fig. 3 or fig. 5, after forming relatively dense stripe trenches on the substrate, and forming the gate structure of the trench power device in the stripe trenches and performing heat treatment, the substrate is likely to warp significantly from the short side direction of the stripe trenches (here, the direction perpendicular to the trench extension direction in the plane of the wafer upper surface). This is because after the substrate is subjected to multiple processes of material deposition, etching, high temperature, etc., a large amount of stress is generated on the substrate, and particularly, stress mismatch is easily generated at the interface between the trench and the substrate to generate strain, so that the substrate is poor in flatness and deforms, i.e., warps. The warpage problem can have adverse effects on the manufacturing of power devices, especially on the influence of the warpage problem on the photolithography process, for example, in the exposure process, if the substrate is warped, the exposure beam incident on the surface of the substrate can generate focus offset, and cannot form a clear image, so that the pattern on the mask plate cannot be accurately transferred onto the substrate, which not only results in low yield of the devices, but also results in low yield of the devices, when the warped substrate is seriously transferred between the photolithography machine, the etching machine and other equipment, the vacuum adsorption on the transfer arm is easily lost, which leads to transfer errors and equipment alarm, the maintenance process not only causes cost increase, but also limits the improvement of the production efficiency. The existing methods for dealing with the warpage problem are mainly improved from the aspects of processes, such as reducing the thermal process, reducing the temperature of film deposition and annealing, reducing the thickness of the deposited film, and the like, however, the processes of the devices are often required to be changed by the methods, the performance of the devices is easily affected, and the effects need to be repeatedly verified, which is tedious and time-consuming.
Therefore, in some embodiments of the present invention, an included angle between an extending direction of the first stripe trench 20 in at least one of the chip regions in the same exposure field range in the upper surface of the substrate 100 and an extending direction of the first stripe trench 20 in another one of the chip regions in the upper surface of the substrate 100 is set to be a right angle, so that on the substrate, stresses generated in each chip region are dispersed or cancelled out, and an effect of avoiding substrate deformation caused by excessive concentration of the stresses in each chip region in the same direction can be achieved, thereby reducing a risk of substrate warpage.
Referring to fig. 6, the first stripe-shaped trenches 20 in two adjacent chip regions extend in a direction parallel to the <110> crystal direction and perpendicular to each other in one exposure field. But not limited thereto, in other embodiments, the second straight-grooved stripe-shaped grooves 30 may have other arrangements. For example, in an embodiment, only the extending direction of the first bar-shaped trench 20 in one or several chip regions may be perpendicular to the extending direction of the first bar-shaped trench 20 in the remaining chip regions, and the one or several chip regions may be uniformly or randomly distributed within the exposure field. In one embodiment, the extending directions of the first stripe-shaped trenches 20 in the whole chip area of the partial area and the whole chip area of the other partial area are perpendicular to each other within one exposure field.
Referring to fig. 7, the first stripe-shaped trench 20 may also be bent and extended in a different direction parallel to the first crystal direction (e.g., a <110> crystal direction) in the upper surface of the substrate 100, thereby forming a curved trench. That is, the first stripe-shaped trench 20 in a part or all of the chip area may not be a straight trench but a curved trench having a V-shape and a W-shape within one exposure field, each straight line segment in the curved trench being parallel to the first crystal direction. The same curved groove may comprise more than one segment of curved structure in the form of a V or W. By means of the bending design, after the gate structure of the first power device is formed in each first linear groove 20 in the same chip area and is subjected to heat treatment, stress directions generated by different linear segments are different, the effect of avoiding deformation of the substrate caused by excessive concentration of stress in each chip area in the same direction can be achieved, and therefore the risk of warping of the substrate is reduced.
Further, depending on the device design, the first stripe-shaped trench 20 of the straight trench shape as shown in fig. 6 may be formed in the partial chip region, and the first stripe-shaped trench 20 of the curved shape as shown in fig. 7 may be formed in the partial chip region within the same exposure field. Wherein, each straight slot can all arrange in same direction, also can arrange respectively in two mutually perpendicular directions.
In the embodiment of the invention, in order to save the tape-out cost, more than one trench type power device with crystal orientation design can be arranged on the same substrate. That is, in the process of performing the second step S2, a plurality of second stripe-shaped trenches located in the substrate 100 and a gate structure located in the second stripe-shaped trenches may be further formed in at least a portion of the chip region, and the first stripe-shaped trenches extend in parallel to another crystal direction different from the first crystal direction in the upper surface of the substrate 100. As an example, in an embodiment, the second stripe-shaped grooves are arranged to extend in a second crystal direction corresponding to the reference direction.
Further, referring to fig. 8, in the step-and-expose photolithography and etching of the substrate 100 to form the first stripe-shaped trench 20, a second stripe-shaped trench 30 may be formed in at least a portion of the chip region within the coverage of each exposure field, wherein the second stripe-shaped trench 30 extends in a direction parallel to the second crystal direction (e.g., <100> crystal direction) in the upper surface of the substrate 100.
Referring to fig. 8, the same second stripe-shaped trench 30 may extend in the same direction parallel to the second crystal direction within the upper surface of the substrate 100, thereby forming a straight trench. However, the present invention is not limited thereto, and the same second stripe-shaped trench 30 may be bent and extended in different directions parallel to the second crystal direction in the upper surface of the substrate 100, thereby forming a curved trench. For each chip region located in the same exposure field range, the first stripe-shaped trench 20 or the second stripe-shaped trench 30 therein may be provided as a straight trench or a curved trench as needed. Referring to fig. 9, in an embodiment, in the same exposure field, the first stripe trenches 20 are curved trenches, and the second stripe trenches 30 are straight trenches, and the arrangement directions of two adjacent first stripe trenches 20 may be perpendicular to each other, and the arrangement directions of two adjacent second stripe trenches 30 may also be perpendicular to each other, so that after a gate structure is formed and heat treatment is performed, the substrate warpage problem caused by stress concentration can be avoided. Referring to fig. 10, in one embodiment, a partial chip region is provided with a first stripe-shaped trench 20 having a curved shape to implement one power device design, and a partial chip region is provided with a second stripe-shaped trench 30 having a curved shape to implement another power device design, within the same exposure field. By providing the first and second stripe-shaped trenches 20 and 30 with curved shapes extending in a direction parallel to the first crystal direction (e.g., <110> crystal direction) and the second crystal direction (e.g., <100> crystal direction), respectively, it is helpful to disperse stress that is subsequently generated in the trench cross-section after the gate structure is formed, or to counteract the stress, so that the risk of warpage of the substrate after further heat treatment can be avoided.
In the embodiment of the present invention, the first stripe trench 20 and the second stripe trench 30 are used to manufacture a trench type power device, such as a trench MOSFET or a trench IGBT.
Fig. 11 to fig. 13 are schematic cross-sectional views of a manufacturing method of a trench type power device in the manufacturing process according to an embodiment of the present invention. Referring to fig. 11 to 13, a method for manufacturing a trench power device according to an embodiment of the present invention is further described by taking an example of manufacturing a trench power device in a chip region having a first stripe-shaped trench 20.
Fig. 11 is a schematic cross-sectional structure diagram of the manufacturing method of the trench power device after the first stripe trench is formed according to the embodiment of the invention. Referring to fig. 11, a first bar-shaped trench 20 is formed in a substrate 100 corresponding to at least a portion of a chip region using the above-described method. After the first stripe trench 20 is formed, the above-described hard mask layer used as a mask may be removed. Referring to fig. 11, more than two first bar-shaped grooves 20 (the number shown in the figure is merely an example) are arranged in parallel in each chip region, and the distance between two adjacent first bar-shaped grooves 20 is about 1 μm to 4 μm. The angle between the sidewall of each first stripe trench 20 and the upper surface of the substrate 100 is about 85-90 °, the sidewall and the bottom of each first stripe trench 20 are preferably smooth surfaces, the depth of each first stripe trench 20 is about 1 μm-6 μm (e.g., deep into the silicon epitaxial layer), the width of each first stripe trench 20 is about 0.2 μm-1.5 μm, and the length (the dimension of both ends in the extension direction) is about 3 times or more of the width in the plane of the upper surface of the substrate 100, which can be determined according to the device design.
And then forming a gate structure of a corresponding trench type power device in the first strip-shaped trench 20. Fig. 12 is a schematic cross-sectional view illustrating a gate structure formed in the first stripe trench by the method for manufacturing a trench power device according to the embodiment of the present invention. Referring to fig. 12, the gate structure includes a gate oxide layer 101 and a gate 102 covering the inner surface of the first stripe-shaped trench 20, first, the gate oxide layer 101 is deposited on the inner surface of the first stripe-shaped trench 20 and the upper surface of the substrate 100, and then polysilicon is deposited to fill each first stripe-shaped trench 20; and then, performing back etching on the polysilicon in each first strip-shaped trench 20 to obtain a gate 102, wherein the upper surface of the gate 102 is lower than the upper surface of the substrate 100, the back etching depth is less than 0.2 μm, and the shape of the substrate 100 is basically not influenced by the back etching due to the protection of the gate oxide layer 101. The polysilicon has conductive dopants therein.
After the gate structure is formed in the first stripe trench 20, stress is easily introduced into the trench sidewall region, and after further annealing, strain is easily generated in the width direction of the trench due to stress concentration, thereby causing substrate warpage. In the embodiment of the present invention, an included angle between an extending direction of the first bar-shaped trench 20 (or the second bar-shaped trench 30) in the upper surface of the substrate 100 in at least one of the chip regions and an extending direction of the first bar-shaped trench 20 (or the second bar-shaped trench 30) in another one of the chip regions in the upper surface of the substrate 100 may be set to be a right angle, so that stress on the substrate in the horizontal direction is dispersed or cancelled, and a risk of substrate warpage may be reduced. In addition, as the groove arrangement is adjusted, the process parameters of the device do not need to be changed, the thermal budget for manufacturing the device does not need to be changed, the influence on the process flow and the performance of the device is small, the possibility of alarming of a process system caused by the warping problem is reduced, and the yield and the production efficiency of the device are improved.
Fig. 13 is a schematic cross-sectional structure diagram of the manufacturing method of the trench power device after ion implantation according to the embodiment of the present invention. Referring to fig. 13, taking the fabrication of an N-type trench MOSFET as an example, after forming a gate structure, a body region and a source region of a trench power device are formed by ion implantation. First, selective P-type ion implantation is performed, and a body region 103 (P body) is formed in the substrate 100 on both sides of the first stripe-shaped trench 20 using high temperature annealing. The body region 103 is used for forming an inversion channel, and the depth of the inversion channel reaches about 2 μm to 4 μm below the upper surface of the substrate 100. The high temperature anneal is at a temperature in a range between about 1000 degrees Celsius and about 1200 degrees Celsius; then, a source region 104 is formed by N-type ion implantation, and the source region 104 is advanced to a certain depth in the substrate 100 by thermal annealing by adjusting the implantation energy and dose, the depth of the source region 104 ranges from about 0.2 μm to 1 μm, and the bottom of the source region 104 is lower than the upper surface of the gate 102.
In the embodiment of the present invention, the Gate structures formed in the first stripe Trench 20 and the second stripe Trench 30 may adopt a Trench Gate structure (see fig. 12) of a TBO (Trench Gate bottom oxide), or adopt a Trench Gate structure in which an SGT (Shielded Gate Trench) and a Gate are arranged from bottom to top from the bottom of the Trench, and may be specifically determined according to a device design. The drain region of the N-type trench MOSFET is disposed at one side of the lower surface of the substrate 100.
The method for manufacturing the trench power device according to the embodiment of the present invention may further include, after completing the trench power device designed correspondingly in each chip region on the substrate, the following third step: dicing the substrate to separate the respective chip regions to obtain a plurality of chips. The chip can be a trench MOSFET or a trench IGBT.
In the embodiment of the present invention, by adjusting the trench design, the first stripe trench for forming the gate structure does not need to be opened in the direction of the notch, i.e., the reference direction, but can be made by selecting a crystal orientation meeting the requirement based on the current specification of the substrate and based on the crystal orientation structure in the circumferential direction of the substrate according to the device design. By forming the first stripe-shaped trench in a first crystal direction different from the reference direction, the device design can be performed in a second crystal direction corresponding to the reference direction without being limited to the reference direction, and the requirement for the substrate specification can be reduced. It should be noted that although the method for manufacturing the trench type power device according to the embodiment of the present invention mainly describes the arrangement and the manufacturing of the trench for disposing the gate structure of the device, the structure and the processing steps of the well-known trench type power device may also be included therein.
The embodiment of the invention also comprises a groove type power device formed by adopting the manufacturing method. The trench power device formed by the above-mentioned manufacturing method is, for example, a trench MOSFET or a trench IGBT, and referring to fig. 5 to 13, a gate structure of the trench power device is disposed in a first stripe trench 20 formed in a substrate 100, the first stripe trench 20 extends in a direction parallel to a first crystal direction in an upper surface of the substrate, and a second crystal direction corresponding to the first crystal direction and a reference direction of the substrate belongs to a different crystal orientation group. Different groove type power device designs and flow sheets can be realized through the same substrate. In an embodiment, for a chip region on the same substrate 100, the gate structure is disposed in a second stripe-shaped trench 30 formed in the substrate 100, the second stripe-shaped trench 30 extends in a direction parallel to a second crystal direction within the substrate upper surface, the first crystal direction and the second crystal direction are periodically distributed around a center within the substrate upper surface, and the second crystal direction may be a crystal direction corresponding to notch.
According to the groove type power device provided by the embodiment of the invention, a certain crystal orientation except for the crystal orientation corresponding to the substrate notch can be selected according to the design for manufacturing, the requirement on the specification of the substrate is reduced, and the cost of the wafer can be saved.
It should be noted that the embodiments in this specification are described in a progressive manner, and for the structure disclosed in the embodiments, the features thereof correspond to the manufacturing method disclosed in the embodiments, so that the description is relatively simple, and relevant parts can be understood by reference.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A manufacturing method of a trench type power device is characterized by comprising the following steps:
providing a substrate, wherein a positioning groove is formed in the edge of the substrate, a connecting line between the center of the substrate and the positioning groove is a reference direction, a first crystal orientation and a second crystal orientation which belong to different crystal orientation groups are periodically distributed around the center in the upper surface of the substrate, the reference direction is parallel to the second crystal orientation, and the substrate comprises a plurality of chip areas; and the number of the first and second groups,
and forming a first strip-shaped groove and a gate structure positioned in the first strip-shaped groove in the substrate of at least part of the chip area, wherein the first strip-shaped groove extends in a direction parallel to the first crystal direction in the upper surface of the substrate.
2. The method of manufacturing of claim 1, further comprising: dicing the substrate to separate the respective chip regions to obtain a plurality of chips.
3. The method of manufacturing of claim 2, wherein the chip is a trench MOSFET or a trench IGBT.
4. The method according to claim 1, wherein the upper surface of the substrate has a (100) crystal plane, and the first crystal orientation and the second crystal orientation have a <110> crystal orientation or a <100> crystal orientation, respectively.
5. The method according to any one of claims 1 to 4, wherein the first stripe-shaped trench extends in the same direction parallel to the first crystal direction within the upper surface of the substrate, thereby forming a straight trench; or, the first strip-shaped groove is bent and extended in different directions parallel to the first crystal direction in the upper surface of the substrate, so as to form a bent groove.
6. The method of manufacturing according to any one of claims 1 to 4, wherein the step of manufacturing the first bar-shaped groove includes:
sequentially forming a hard mask layer and a photoresist layer on the substrate;
exposing and developing the photoresist layer by using a step exposure mode, and etching the hard mask layer by using the patterned photoresist layer as a mask to pattern the hard mask layer; and the number of the first and second groups,
and etching the substrate by using the patterned hard mask layer as a mask, wherein at least part of the chip area forms the first strip-shaped groove within the coverage range of each exposure field.
7. The method of claim 6, wherein each exposure field covers a region in which the first striped trench in at least one of the chip regions extends at a right angle to a direction in which the first striped trench in another one of the chip regions extends in the upper surface of the substrate.
8. The method according to claim 6, wherein in the step of etching the substrate, a second stripe-shaped trench is formed in at least a part of the chip region within each exposure field coverage, wherein the second stripe-shaped trench extends in a direction parallel to the second crystal direction within the upper surface of the substrate.
9. The method according to claim 8, wherein the second stripe-shaped trenches extend in the same direction parallel to the second crystal direction in the upper surface of the substrate, thereby forming straight trenches; or the second strip-shaped groove is bent and extended in different directions parallel to the second crystal direction in the upper surface of the substrate, so that a bent groove is formed.
10. A trench type power device formed by the method of any one of claims 1 to 9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113363252A (en) * | 2021-05-31 | 2021-09-07 | 上海积塔半导体有限公司 | Trench IGBT chip layout structure |
| CN114447159A (en) * | 2022-02-10 | 2022-05-06 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method of forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100766095B1 (en) * | 1997-06-12 | 2007-10-11 | 가부시키가이샤 니콘 | Substrate for device manufacturing, process for manufacturing the substrate, and method of exposure using the substrate |
| CN202977424U (en) * | 2012-12-13 | 2013-06-05 | 中国科学院微电子研究所 | Groove formed on IGBT (insulated gate bipolar transistor) or VDMOS (vertical diffused metal oxide semiconductor) |
| CN108987473A (en) * | 2017-05-31 | 2018-12-11 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
-
2020
- 2020-07-16 CN CN202010683697.2A patent/CN111564370A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100766095B1 (en) * | 1997-06-12 | 2007-10-11 | 가부시키가이샤 니콘 | Substrate for device manufacturing, process for manufacturing the substrate, and method of exposure using the substrate |
| CN202977424U (en) * | 2012-12-13 | 2013-06-05 | 中国科学院微电子研究所 | Groove formed on IGBT (insulated gate bipolar transistor) or VDMOS (vertical diffused metal oxide semiconductor) |
| CN108987473A (en) * | 2017-05-31 | 2018-12-11 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113363252A (en) * | 2021-05-31 | 2021-09-07 | 上海积塔半导体有限公司 | Trench IGBT chip layout structure |
| CN114447159A (en) * | 2022-02-10 | 2022-05-06 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method of forming the same |
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