WO2021010380A1

WO2021010380A1 - Semiconductor chip and methods for manufacturing semiconductor chip

Info

Publication number: WO2021010380A1
Application number: PCT/JP2020/027282
Authority: WO
Inventors: 一範原田; 秀人玉祖
Original assignee: 住友電気工業株式会社
Priority date: 2019-07-17
Filing date: 2020-07-13
Publication date: 2021-01-21
Also published as: JPWO2021010380A1; JP7487739B2

Abstract

A semiconductor chip comprises: a silicon carbide substrate having a first surface and a second surface opposite to the first surface; and a first electrode provided on the first surface of the silicon carbide substrate, wherein the first electrode has, in a plan view, a first region including a silicide and a second region not including a silicide.

Description

Semiconductor chips and methods for manufacturing semiconductor chips

This disclosure relates to a semiconductor chip and a method for manufacturing a semiconductor chip.

This application claims the priority based on Japanese Application No. 2019-131804 filed on July 17, 2019, and incorporates all the contents described in the Japanese application.

A semiconductor device made of silicon carbide (SiC) is used for applications such as power electronics because it can pass a large current with a higher withstand voltage than a semiconductor device made of silicon (Si). A silicon carbide semiconductor chip is used in a semiconductor device formed of such silicon carbide.

Japanese Patent Application Laid-Open No. 2016-9695 Japanese Patent Application Laid-Open No. 2014-196209

The semiconductor chip of the present disclosure has a silicon carbide substrate having a first surface and a second surface opposite to the first surface, and a first electrode provided on the first surface of the silicon carbide substrate. The first electrode has a first region containing silicide and a second region not containing VDD in a plan view.

FIG. 1 is a structural diagram of a silicon carbide substrate. FIG. 2 is an explanatory diagram of the amount of warpage of the silicon carbide substrate. FIG. 3 is a flowchart of a method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure. FIG. 4 is an explanatory diagram (1) of a method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure. FIG. 5 is an explanatory diagram (2) of a method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure. FIG. 6 is an explanatory diagram (3) of a method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure. FIG. 7 is an explanatory diagram (4) of a method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure. FIG. 8 is an explanatory diagram (1) of the semiconductor chip of the first embodiment of the present disclosure. FIG. 9 is an explanatory diagram (5) of a method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure. FIG. 10 is an explanatory diagram (2) of the semiconductor chip of the first embodiment of the present disclosure. FIG. 11 is an explanatory diagram (1) of a modified example of the method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure. FIG. 12 is an explanatory diagram (1) of a modified example of the semiconductor chip according to the first embodiment of the present disclosure. FIG. 13 is an explanatory diagram (2) of a manufacturing method of a modified example of the semiconductor chip according to the first embodiment of the present disclosure. FIG. 14 is an explanatory diagram (2) of a modified example of the semiconductor chip according to the first embodiment of the present disclosure. FIG. 15 is a plan view of the semiconductor chip of the first embodiment of the present disclosure. FIG. 16 is a cross-sectional view (1) of the semiconductor chip of the first embodiment of the present disclosure. FIG. 17 is a cross-sectional view (2) of the semiconductor chip of the first embodiment of the present disclosure. FIG. 18 is a cross-sectional view (3) of the semiconductor chip of the first embodiment of the present disclosure. FIG. 19 is a flowchart of a method for manufacturing a semiconductor chip according to the second embodiment of the present disclosure. FIG. 20 is an explanatory diagram (1) of a method for manufacturing a semiconductor chip according to the second embodiment of the present disclosure. FIG. 21 is an explanatory diagram (2) of a method for manufacturing a semiconductor chip according to the second embodiment of the present disclosure.

[Issues to be solved by this disclosure]
Silicon carbide semiconductor chips are manufactured through various manufacturing processes such as film formation, heat treatment, and polishing. In such manufacturing steps, the silicon carbide substrate forming the semiconductor chip may warp. If the silicon carbide substrate is warped, problems may occur when the semiconductor chip is mounted. Therefore, a semiconductor chip having a small warp of the silicon carbide substrate is required.

[Effect of the present disclosure]
According to the present disclosure, it is possible to provide a semiconductor chip having a small warp of a silicon carbide substrate.

The mode for implementation will be described below.

[Explanation of Embodiments of the present disclosure]
First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are designated by the same reference numerals, and the same description is not repeated for them.

[1] The semiconductor chip according to one aspect of the present disclosure includes a silicon carbide substrate having a first surface and a second surface opposite to the first surface, and a first surface provided on the first surface of the silicon carbide substrate. The first electrode has one electrode, and in plan view, the first electrode has a first region containing SiO and a second region not containing VDD.

This makes it possible to provide a semiconductor chip having a small warp in a silicon carbide substrate.

[2] The shape of the first region in a plan view includes a pair of short sides parallel to each other and a pair of long sides orthogonal to the short side and longer than the short side and parallel to each other. It is a rectangle to have.

This makes it possible to further provide a semiconductor chip having a small warp in the silicon carbide substrate.

[3] The length of the short side is 1.5 mm or more and 10.0 mm or less.

The larger the chip area, the larger the current can flow through the semiconductor chip. Further, the smaller the chip area, the less defects due to crystal defects, and in particular, when the chip exceeds 10.0 mm square, the defect rate increases remarkably.

[4] The shape of the semiconductor chip in a plan view is rectangular, and the length of the long side of the first region is the same as one side of the semiconductor chip.

[5] In a plan view, the first region is surrounded by the second region.

Even in this case, it is possible to provide a semiconductor chip having a small warp in the silicon carbide substrate.

[6] The first electrode contains nickel or titanium.

As a result, the alloy layer in the first region can be silicidized with Si contained in the silicon carbide substrate.

[7] In a plan view, the area of the first electrode with respect to the area of the first region is 73% or more and 98% or less.

The area of the first electrode with respect to the area of the first region is limited by the chip area and the chip thickness described later, and it is desirable to increase the electrode area in order not to reduce the drain current. Since the thickness of the semiconductor chip is about 100 μm to 200 μm, the area of the first electrode with respect to the area of the first region is 73% for the 1.5 mm square chip and 98% for the 10.0 mm square chip. It becomes.

[8] A second electrode is provided on the second surface, the thickness of the silicon carbide substrate is t, and the length in the first direction in a plan view of the first region is Wdx. When the length of the first direction in which the second electrode is viewed in a plane is Wsx, Wdx> Wsx + 2t, and the second region is orthogonal to the first direction in which the first region is viewed in a plane. When the length in the direction is Wdy and the length in the second direction when the second electrode is viewed in a plane is Wsy, Wdy> Wsy + 2t.

This makes it possible to provide a semiconductor chip with small warpage that does not affect the drain current.

[9] In the first direction and the second direction, the first region is wider than the second electrode by t or more on both sides.

As a result, it is possible to provide a semiconductor chip having a small warp that does not further affect the drain current.

[10] The concentration of silicon contained in the first region is 32 wt% or more and 49 wt% or less.

This makes it possible to form NiSi, which has the lowest resistivity among Ni-Si alloy systems.

[11] The method for manufacturing a semiconductor chip according to one aspect of the present disclosure includes a step of preparing a silicon carbide substrate having a first surface and a second surface opposite to the first surface, and the first aspect of the silicon carbide substrate. A step of forming an element region on two surfaces, a step of grinding the first surface of the silicon carbide substrate, a step of forming a metal film on the ground first surface, and a step toward the first surface. The first surface of the ground silicon carbide substrate has a concavely curved second surface, which comprises a step of forming VDD on a part of the metal film by irradiation with a laser beam. Between the step of grinding and the step of forming VDD on a part of the metal film, a plurality of long ones in a direction having a large amount of warpage among a first direction and a second direction orthogonal to each other on the first surface in a plan view. The step of defining the first region and the second region between the first regions, and the step of forming VDD on a part of the metal film, includes a laser in the second region. It has a step of irradiating the first region with a laser beam without irradiating the light.

As a result, the warpage of the silicon carbide substrate for manufacturing the semiconductor chip can be reduced.

[12] The amount of warpage of the second surface of the silicon carbide substrate ground in the step of grinding the first surface of the silicon carbide substrate is 1 μm or more and 500 μm or less, more preferably 50 μm or more and 300 μm. It is as follows.

It is not necessary to correct the warp on a board with a small amount of warpage, and on a board with an excessively large warp, there is a high possibility that the semiconductor chip is destroyed by deformation, so even if the warp is corrected, a good product may be obtained. Is low.

[13] The metal film contains nickel or titanium.

[14] There is a step of forming a silicon film between the step of forming the metal film and the step of forming VDD on a part of the metal film.

[15] The size of the silicon carbide substrate is 6 inches or more.

This is because the present invention is particularly effective when the size of the silicon carbide substrate is 6 inches or more because the warp becomes remarkable as the size of the silicon carbide substrate increases.

[16] The first area is in the shape of a strip.

As a result, the warpage of the silicon carbide substrate can be reduced in the semiconductor chip.

[17] After the step of forming VDD on a part of the metal film, the silicon carbide substrate is separated by dicing and formed into chips.

As a result, a semiconductor chip can be obtained.

[18] In the chipped semiconductor chip, the shape of the first region in a plan view is rectangular.

As a result, a semiconductor chip with a small warp can be obtained.

[19] The shape of the chipped semiconductor chip in a plan view is rectangular, and the length of the long side of the first region is the same as one side of the semiconductor chip.

As a result, a semiconductor chip with a small warp can be obtained.

[20] In the chipped semiconductor chip, the first region is surrounded by the second region in a plan view.

[21] In the plan view of the chipped semiconductor chip, the area of the first region with respect to the area of the first surface of the semiconductor chip is 75% or more and 96% or less.

The larger the area of the first region with respect to the area of the first surface of the semiconductor chip, the more it is possible to prevent the drain current from decreasing. Due to the above-mentioned limitation by the chip thickness, the thickness of the semiconductor chip is 100 μm to 200 μm, which is 75% for the 1.5 mm square chip and 96% for the 10.0 mm square chip.

[Details of Embodiments of the present disclosure]
Hereinafter, one embodiment of the present disclosure will be described in detail, but the present embodiment is not limited thereto. Further, in the present disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as directions orthogonal to each other. Further, the surface including the X1-X2 direction and the Y1-Y2 direction is described as the XY surface, the surface including the Y1-Y2 direction and the Z1-Z2 direction is described as the YZ surface, and the Z1-Z2 direction and the X1-X2 direction are described as the YZ surface. The including surface is referred to as a ZX surface.

[First Embodiment]
First, the warp in the semiconductor chip will be described.

First, as shown in FIG. 1, a silicon carbide substrate 10 having a first surface 10a and a second surface 10b opposite to the first surface 10a is prepared, and then a second surface of the silicon carbide substrate 10 is prepared. Ion implantation, electrode formation, film formation of an insulating film, heat treatment and the like are performed on 10b. After that, the first surface 10a of the silicon carbide substrate 10 is thinned by grinding, and the silicon carbide substrate 10 after grinding thinned through these steps has a concave second surface 10b as shown in FIG. , The first surface 10a may warp convexly. In the present application, the amount of warpage of the silicon carbide substrate 10 is the height difference between the second surface 10b of the silicon carbide substrate 10, that is, the height of the lowest portion and the highest portion of the second surface 10b of the silicon carbide substrate 10. It shall mean the difference between. The lowest and highest parts of the second surface 10b can be identified by measuring the shape of the second surface 10b using a laser autofocus microscope.

After that, an electrode is formed on the first surface 10a and separated into a semiconductor chip by a dicing saw. However, if the amount of warpage of the silicon carbide substrate 10 is large, the warp of the separated semiconductor chip also becomes large, so that the semiconductor chip can be separated. The vacuum chuck becomes incomplete. Therefore, the semiconductor chip cannot be conveyed, which causes a problem when the semiconductor chip is mounted.

(Manufacturing method of semiconductor chip)
The method for manufacturing the semiconductor chip of the first embodiment will be described with reference to FIG.

First, in step 102 (S102), the silicon carbide substrate 10 is prepared. As shown in FIG. 1, the silicon carbide substrate 10 has a first surface 10a and a second surface 10b opposite to the first surface 10a, and has a thickness of 350 μm to 500 μm and a size of 350 μm to 500 μm. It is one of 4 inches, 6 inches, and 8 inches. Since this embodiment reduces the warp of the silicon carbide substrate 10, it is particularly preferable to apply it to the silicon carbide substrate 10 having a size of 6 inches or more. Therefore, in this description, the case where the 6-inch silicon carbide substrate 10 is used will be described.

Next, in step 104 (S104), a step of forming an element region on the second surface 10b of the silicon carbide substrate 10 is performed. Specifically, the element region 20 is formed as shown in FIG. 5, which will be described later, by performing ion implantation, electrode formation, film formation of an insulating film, heat treatment, and the like on the second surface 10b of the silicon carbide substrate 10. To.

Next, in step 106 (S106), a step of grinding the first surface 10a of the silicon carbide substrate 10 is performed. The first surface 10a of the silicon carbide substrate 10 is ground by a back surface grinding machine (Grinder), CMP (chemical mechanical polishing), or the like until the thickness of the silicon carbide substrate 10 becomes 150 μm or more and 300 μm or less.

Next, in step 108 (S108), the amount of warpage of the second surface 10b of the silicon carbide substrate 10 is measured. Specifically, as shown in FIG. 4, the amount of warpage in the X1-X2 direction and the Y1-Y2 direction is measured on the second surface 10b of the silicon carbide substrate 10. In this embodiment, in the silicon carbide substrate 10, the second surface 10b of the silicon carbide substrate 10 is curved in the X1-X2 direction or the Y1-Y2 direction, as shown in FIG. And. In the measurement of the amount of warpage, the shape of the second surface 10b is measured using a laser autofocus microscope, the difference in height between the lowest part and the highest part of the second surface 10b is calculated, and this difference is used as the amount of warpage. And.

Next, in step 110 (S110), as shown in FIG. 5, a metal film 30 is formed on the first surface 10a of the silicon carbide substrate 10 by sputtering or the like. The metal film 30 is for forming an ohmic electrode, and is made of Ni (nickel), Ti (titanium), or the like. In the present embodiment, for example, the metal film 30 is formed of Ni having a film thickness of 90 nm or more and 110 nm or less.

Next, in step 112 (S112), laser light is irradiated. For example, in the X1-X2 direction, when the second surface 10b of the silicon carbide substrate 10 is curved in a concave shape, as shown in FIG. 6, the metal film 30 is formed on the first surface 10a side. , A strip-shaped laser irradiation region 41 long in the X1-X2 direction is set, and laser light is irradiated. That is, the region to be irradiated with the laser beam and the region not to be irradiated with the laser beam are defined according to the warp of the second surface 10b, and the laser beam is irradiated to the first surface 10a. Specifically, the metal film 30 of the strip-shaped laser irradiation region 41 long in the X1-X2 direction is irradiated while scanning the spot of the laser beam. As a result, the metal film 30 and the like are heated, and the Ni contained in the metal film 30 and the Si contained in the silicon carbide substrate 10 form a NiSi alloy layer 31 to be an ohmic electrode, as shown in FIG. The wavelength of the irradiated laser beam is, for example, 365 nm. The case where the second surface 10b of the silicon carbide substrate 10 is warped concavely in the X1-X2 direction means that the second surface 10b of the silicon carbide substrate 10 is warped concavely as shown in FIG. Is.

If the silicon carbide substrate 10 is not warped, the entire surface on the first surface 10a side is irradiated with laser light. Therefore, the method for manufacturing a semiconductor chip of the present embodiment is performed when the amount of warpage of the second surface 10b of the silicon carbide substrate 10 in the X1-X2 direction or the Y1-Y2 direction is 1 μm or more and 500 μm or less. If the amount of warpage of the second surface 10b is less than 1 μm, it is not necessary to perform a process for correcting the warp. If the amount of warpage of the second surface 10b exceeds 500 μm, the element in the element region 20 may be destroyed, and it is unlikely that a good product can be obtained even if the warp is corrected.

The NiSi alloy layer 31 is formed by silicidizing the metal film 30 of the laser irradiation region 41 irradiated with the laser beam into a NiSi alloy. Therefore, the NiSi alloy layer is not formed because the laser unirradiated region 42 between the adjacent laser irradiation regions 41, which is not irradiated with the laser beam, is not silicated. Therefore, in the laser unirradiated region 42, the metal film 30 is still formed on the first surface 10a of the silicon carbide substrate 10. In this way, silicide is formed on a part of the metal film 30.

In the present application, the region where the laser irradiation region 41 and the NiSi alloy layer 31 are formed is described as the first region, and the metal film 30 is formed on the laser non-irradiation region 42 and the first surface 10a of the silicon carbide substrate 10. The as-is region is referred to as the second region. Further, an electrode on the first surface 10a side, for example, a drain electrode is formed by the first region and the second region.

The NiSi alloy layer 31 is alloyed to generate stress that pulls the silicon carbide substrate 10. Therefore, by forming the NiSi alloy layer 31 so that the X1-X2 direction is the longitudinal direction, a stress that pulls the silicon carbide substrate 10 in the X1-X2 direction is generated, so that the second surface 10b of the silicon carbide substrate 10 is warped. The amount is small and can be made flat.

Next, in step 114 (S114), the silicon carbide substrate 10 is made into chips by dicing. Specifically, the silicon carbide substrate 10 is cut by a dicing saw along the broken lines in the X1-X2 direction and the Y1-Y2 direction shown in FIG. As a result, the semiconductor chip 101 on which the NiSi alloy layer 31 is formed can be obtained in the laser irradiation region 41 of the first surface 10a as shown in FIG. That is, in the plan view of the first surface 10a, the semiconductor chip 101 having a region where the NiSi alloy layer 31 is formed and a region where the metal film 30 which is not silicidized remains as it is is formed. In the present application, the plan view means that the first surface 10a side of the silicon carbide substrate 10 is viewed from the Z2 direction, or the second surface 10b side of the silicon carbide substrate 10 is viewed from the Z1 direction.

Next, when the second surface 10b of the silicon carbide substrate 10 is concavely warped in the Y1-Y2 direction shown in FIG. 4, that is, the second surface 10b of the silicon carbide substrate 10 in the Y1-Y2 direction is shown in FIG. The case of warpage as shown in 5 will be described. In this case, when the laser beam of step 112 is irradiated, as shown in FIG. 9, a strip-shaped long strip in the Y1-Y2 direction is formed on the first surface 10a side on which the metal film 30 is formed. The laser irradiation region 41 is set and the laser beam is irradiated. That is, the region to be irradiated with the laser beam and the region not to be irradiated with the laser beam are defined according to the warp of the second surface 10b, and the laser beam is irradiated to the first surface 10a. Specifically, the metal film 30 of the strip-shaped laser irradiation region 41 long in the Y1-Y2 direction is irradiated while scanning the spot of the laser beam. As a result, the metal film 30 and the like are heated, and the NiSi alloy layer 31 is formed by the Ni contained in the metal film 30 and the Si contained in the silicon carbide substrate 10. The NiSi alloy layer 31 is formed by silicating the metal film 30 in the laser irradiation region 41 irradiated with the laser beam. Therefore, in the laser unirradiated region 42 between the adjacent laser irradiation regions 41 where the laser beam is not irradiated, the NiSi alloy layer is not formed because silicidization is not performed, and the metal film 30 is formed on the first surface 10a of the silicon carbide substrate 10. It is in a state of being. In this way, silicide is formed on a part of the metal film 30.

By forming the NiSi alloy layer 31 so that the Y1-Y2 direction is the longitudinal direction in this way, a stress that pulls the silicon carbide substrate 10 in the Y1-Y2 direction is generated, so that the second surface 10b of the silicon carbide substrate 10 is generated. The warp is reduced and it can be made flat.

After that, in step 114 (S114), the silicon carbide substrate 10 is made into chips by dicing. Specifically, the silicon carbide substrate 10 is cut by a dicing saw along the broken lines in the X1-X2 direction and the Y1-Y2 direction shown in FIG. As a result, the semiconductor chip 102 on which the NiSi alloy layer 31 is formed can be obtained in the laser irradiation region 41 of the first surface 10a as shown in FIG.

It should be noted that the determination of whether to set the strip-shaped laser irradiation region 41 long in the Y1-Y2 direction or the long strip-shaped laser irradiation region 41 in the X1-X2 direction may be made in step 108. In this case, the amount of warpage in the X1-X2 direction and the amount of warpage in the Y1-Y2 direction may be compared for judgment. For example, when the amount of warpage in the Y1-Y2 direction is larger than the amount of warpage in the X1-X2 direction, a strip-shaped laser irradiation region 41 long in the Y1-Y2 direction may be set. Further, when the amount of warpage in the X1-X2 direction is larger than the amount of warpage in the Y1-Y2 direction, a strip-shaped laser irradiation region 41 long in the X1-X2 direction may be set. Further, in the present embodiment, the width of the laser irradiation region 41 may be adjusted so that the amount of warpage is the smallest based on the amount of warpage obtained in step 108. For example, in the case shown in FIG. 6, the width of the laser irradiation region 41 in the Y1-Y2 direction may be adjusted, and in the case shown in FIG. 9, the width of the laser irradiation region 41 in the X1-X2 direction is adjusted. You may.

The above-mentioned

semiconductor chips

101 and 102 are square semiconductor chips having a side of 6 mm square.

As shown in FIG. 8, in the semiconductor chip 101, the width Wy of the NiSi alloy layer 31 in the Y1-Y2 direction is 1.3 μm or more and 9.8 μm or less, more preferably 2.8 μm or more and 5.8 μm or less. More preferably, it is 2.6 μm or more and 5.6 μm or less. This is the width Wy of the alloy layer required when the chip thickness is 100 μm, the upper limit is a 10.0 mm square chip, and the lower limit is a 1.5 mm square chip. In the semiconductor chip 101, the shape of the NiSi alloy layer 31 is a rectangle having the long side in the X1-X2 direction and the short side in the Y1-Y2 direction, and the length of the long side in the X1-X2 direction is that of the semiconductor chip 101. Equal to the length of one side.

As shown in FIG. 10, in the semiconductor chip 102, the width Wx in the X1-X2 direction of the NiSi alloy layer 31 is in the same range as the width Wy. The shape of the NiSi alloy layer 31 formed on the semiconductor chip 102 is a rectangle having a long side in the Y1-Y2 direction and a short side in the X1-X2 direction, and the length of the long side in the Y1-Y2 direction is the semiconductor. Equal to the length of one side of the chip 102.

(Modification example)
Next, a modified example of this embodiment will be described. The laser irradiation region does not have to be strip-shaped as long as it is a rectangle long in a predetermined direction in the semiconductor chip.

For example, in the X1-X2 direction shown in FIG. 4, when the second surface 10b of the silicon carbide substrate 10 is curved in a concave shape, as shown in FIGS. 11 and 12, in each semiconductor chip, A rectangular laser irradiation region 41 having a long side in the X1-X2 direction is set. In this modification, in step 112 of FIG. 3, the laser irradiation region 41 is irradiated with laser light. By irradiating the metal film 30 of the laser irradiation region 41 while scanning the spot of the laser beam, the metal film 30 and the like are heated, and NiSi contained in the metal film 30 and Si contained in the silicon carbide substrate 10 causes NiSi. The alloy layer 31 is formed. The region other than the laser irradiation region 41 is the laser unirradiated region 42 that is not irradiated with the laser beam, and in the laser unirradiated region 42, the metal film 30 is not silicated and remains the metal film 30.

In the next step 114, the silicon carbide substrate 10 is made into chips by dicing. Specifically, the silicon carbide substrate 10 is cut with a dicing saw along the broken line shown in FIG. As a result, the semiconductor chip 103 on which the NiSi alloy layer 31 is formed can be obtained in the laser irradiation region 41 of the first surface 10a as shown in FIG.

In the semiconductor chip 103 shown in FIG. 12, the NiSi alloy layer 31 is formed in a rectangular shape in which the length Wx1 in the X1-X2 direction is longer than the length Wy1 in the Y1-Y2 direction. For example, the length Wx1 in the X1-X2 direction is 9.8 μm, and the length Wy1 in the Y1-Y2 direction is 4.9 μm.

The NiSi alloy layer 31 is formed by silicating the metal film 30 in the laser irradiation region 41 irradiated with the laser beam. Since the unirradiated region 42 of the laser that is not irradiated with the laser beam is not silicated, the metal film 30 remains formed on the first surface 10a of the silicon carbide substrate 10 in the unirradiated region 42 of the laser.

Therefore, by forming the rectangular NiSi alloy layer 31 having a long side in the X1-X2 direction, a stress for pulling the silicon carbide substrate 10 is generated in the X1-X2 direction, so that the second surface 10b of the silicon carbide substrate 10 is generated. The amount of warpage can be reduced to make it more flat.

Further, in the Y1-Y2 direction shown in FIG. 4, when the second surface 10b of the silicon carbide substrate 10 is curved in a concave shape, as shown in FIGS. 13 and 14, in each semiconductor chip, A rectangular laser irradiation region 41 having a long side in the Y1-Y2 direction is set. In this modification, in step 112 of FIG. 3, the laser irradiation region 41 is irradiated with laser light. By irradiating the metal film 30 of the laser irradiation region 41 while scanning the spot of the laser beam, the metal film 30 and the like are heated, and NiSi is generated by Ni contained in the metal film 30 and Si contained in the silicon carbide substrate 10. The alloy layer 31 is formed. The region other than the laser irradiation region 41 is the laser unirradiated region 42 that is not irradiated with the laser beam, and in the laser unirradiated region 42, the metal film 30 is not silicated and remains the metal film 30.

In the next step 114, the silicon carbide substrate 10 is made into chips by dicing. Specifically, the silicon carbide substrate 10 is cut with a dicing saw along the broken line shown in FIG. As a result, the semiconductor chip 104 on which the NiSi alloy layer 31 is formed can be obtained in the laser irradiation region 41 of the first surface 10a as shown in FIG.

In the semiconductor chip 104 shown in FIG. 14, the NiSi alloy layer 31 is formed in a rectangular shape in which the length Wy2 in the Y1-Y2 direction is longer than the length Wx2 in the X1-X2 direction. For example, the length Wx2 in the X1-X2 direction is 9.8 μm, and the length Wy2 in the Y1-Y2 direction is 4.9 μm.

Therefore, by forming the NiSi alloy layer 31 in a rectangular region having a long side in the Y1-Y2 direction, a stress for pulling the silicon carbide substrate 10 in the Y1-Y2 direction is generated, so that the second silicon carbide substrate 10 is used. The amount of warpage of the surface 10b can be reduced to make the surface 10b almost flat.

In the

semiconductor chips

103 and 104 in this modification, on the first surface 10a, the second region where the metal film 30 remains surrounds the NiSi alloy layer 31 which is the first region.

In this modification, the lengths Wx1 and Wy2 of the long sides are 1.3 μm or more and 9.8 μm or less, more preferably 2.8 μm or more and 5.8 μm or less, and further preferably 2.6 μm or more. It is 5.6 μm or less. The short side lengths Wy1 and Wx2 are 0.7 μm or more and 4.9 μm or less, more preferably 1.4 μm or more and 2.6 μm or less, still more preferably 1.3 μm or more and 2.8 μm. It is as follows. This is the length Wx and Wy2 of the long side of the alloy layer required when assuming a chip thickness of 100 μm, an upper limit of 10.0 mm square chips, and a lower limit of 1.5 mm square chips.

Further, in a plan view, the area of the NiSi alloy layer 31 with respect to the area of the second surface of the semiconductor chip is 75% or more and 96% or less, more preferably 85% or more and 90% or less. As a result, a sufficient area of the NiSi alloy layer can be secured even for a 1.5 mm square to 10.0 mm square chip, and a decrease in drain current can be prevented.

(Semiconductor chip)
Next, the semiconductor chip 100 in the first embodiment will be described with reference to FIGS. 15 to 18. The semiconductor chip in this embodiment can be manufactured by the method for manufacturing a semiconductor chip in this embodiment. FIG. 15 is a plan view of the semiconductor chip in this embodiment. 16 is a cross-sectional view cut along the alternate long and short dash line 15A-15B in FIG. 15, FIG. 17 is a sectional view cut along the alternate long and short dash line 15C-15D in FIG. 15, and FIG. 18 is a sectional view taken along the alternate long and short dash line 15C-15D. It is sectional drawing which cut at -15F.

In the semiconductor chip 100, a plurality of gate electrodes 21, a gate runner 22, and a gate electrode pad 23 are formed on the second surface 10b of the silicon carbide substrate 10, and an insulating film 24 covering each gate electrode 21 is further formed. It is formed. Each gate electrode 21 is formed long in the X1-X2 direction, and the source electrode 25 is formed on the insulating film 24 and on the second surface 10b of the silicon carbide substrate 10 between the insulating film 24 and the insulating film 24. Is formed. Further, a drain electrode 33 is formed on the first surface 10a of the silicon carbide substrate 10 by the NiSi alloy layer 31 and the remaining metal film 30. In the present application, the drain electrode 33 may be referred to as a first electrode.

The gate electrode 21 is made of polysilicon, and the gate runner 22 has a cross-sectional structure in which polysilicon is covered with Al (aluminum). The insulating film 24 is made of silicon oxide, and the source electrode 25 is made of a material containing aluminum.

In the present embodiment, the semiconductor chip 100 is formed so that the NiSi alloy layer 31 of the drain electrode 33 is wider than the source electrode 25 in the X1-X2 direction and the Y1-Y2 direction. In the present application, the source electrode 25 may be referred to as a second electrode.

If the NiSi alloy layer 31 is narrower than the source electrode 25, the amount of current flowing between the source electrode 25 and the NiSi alloy layer 31 of the drain electrode 33 may decrease. If the NiSi alloy layer 31 is formed to a region wider than the range extending at an angle of 45 ° from both ends of the source electrode 25, it flows between the source electrode 25 and the NiSi alloy layer 31 of the drain electrode 33. It is considered that there is almost no effect on the amount of current. Therefore, when the thickness of the silicon carbide substrate 10 is t, the NiSi alloy layer 31 of the drain electrode 33 is formed to a region wider than t on the outside of each region corresponding to the source electrode 25. .. Therefore, the length of the NiSi alloy layer 31 is formed to be longer than the value obtained by adding 2t to the length of the source electrode 25.

For example, as shown in FIG. 16, when the length of the NiSi alloy layer 31 is Wdy and the length of the source electrode 25 is Wsy in the Y1-Y2 direction,
Wdy> Wsy + 2t
Next,
Further, as shown in FIG. 18, when the length of the NiSi alloy layer 31 is Wdx and the length of the source electrode 25 is Wsx in the X1-X2 direction,
Wdx> Wsx + 2t
It is formed so as to be.

Further, as shown in FIG. 16, in the Y1-Y2 direction, the NiSi alloy layer 31 is formed wider than the source electrode 25 in both the X1 direction and the X2 direction by t or more.

Further, as shown in FIG. 18, in the X1-X2 direction, the NiSi alloy layer 31 is formed wider than the source electrode 25 in both the Y1 direction and the Y2 direction by t or more.

[Second Embodiment]
Next, the method of manufacturing the semiconductor chip in the second embodiment will be described with reference to FIG.

In the method for manufacturing a semiconductor chip in the present embodiment, as shown in FIG. 19, a step of forming a silicon film is performed in step 210 (S210) after the step of forming a metal film in step 110. Specifically, after preparing the silicon carbide substrate (S102), forming the element region (S104), grinding (S106), measuring the amount of warpage of the silicon carbide substrate (S108), and forming a metal film (S110). , A silicon film is formed (S210). In the step of forming the silicon film, the silicon film 150 is formed on the metal film 30 as shown in FIG. The film thickness of the silicon film 150 to be formed is, for example, about 100 nm. In addition, step 110 and step 210 may be performed continuously.

After that, laser light irradiation (S112) is performed. In the present embodiment, as shown in FIG. 21, the NiSi alloy layer 131 is formed by the irradiation of the laser beam with the Ni of the metal film 30 and the Si of the silicon film 150 mainly. Therefore, it is possible to prevent a shortage of silicon supply from the silicon carbide substrate and stably form a NiSi alloy layer having a low resistivity. After that, dicing (S114) is performed to obtain the semiconductor chip of the present embodiment.

The concentration of Si in the NiSi alloy layer 131 formed in this way is 32 wt% or more and 49 wt% or less. When the concentration of Si is 32 wt% or more and 49 wt% or less, the resistivity of the NiSi alloy layer 131 can be suppressed low. The concentration of Si is determined by the secondary ion mass spectroscopy (SIMS) method, X-ray Photoelectron Spectroscopy (XPS) method, and energy dispersion X-ray spectroscopy (EDX). It can be measured by the method, Auger electron spectroscopy (AES) method, and inductively coupled plasma spectroscopy (ICP-MS) method.

The contents other than the above are the same as those in the first embodiment.

Although the embodiments have been described in detail above, the embodiments are not limited to the specific embodiments, and various modifications and changes can be made within the scope of the claims.

10 Silicon carbide substrate 10a 1st surface 10b 2nd surface 20 Element region 21 Gate electrode 22 Gate runner 23 Gate electrode pad 24 Insulation film 25 Source electrode 30 Metal film 31 NiSi alloy layer 33 Drain electrode 41 Laser irradiation region 42 Laser non-irradiation region 100

Semiconductor chips

101, 102, 103, 104 Semiconductor chips 131 NiSi alloy layer 150 Silicon film

Claims

A silicon carbide substrate having a first surface and a second surface opposite to the first surface,
With the first electrode provided on the first surface of the silicon carbide substrate,
Have,
The first electrode is a semiconductor chip having a first region containing VDD and a second region not containing VDD in a plan view.
The shape of the first region in a plan view is
A pair of short sides parallel to each other,
A pair of long sides that are orthogonal to the short side, longer than the short side, and parallel to each other.
The semiconductor chip according to claim 1, which is a rectangle having.
The semiconductor chip according to claim 2, wherein the length of the short side is 1.5 mm or more and 10.0 mm or less.
The shape of the semiconductor chip in a plan view is rectangular,
The semiconductor chip according to claim 2 or 3, wherein the length of the long side of the first region is the same as one side of the semiconductor chip.
The semiconductor chip according to any one of claims 1 to 3, wherein the first region is surrounded by the second region in a plan view.
The semiconductor chip according to any one of claims 1 to 5, wherein the first electrode contains nickel or titanium.
The semiconductor chip according to any one of claims 1 to 6, wherein the area of the first region with respect to the area of the first electrode is 73% or more and 98% or less in a plan view.
A second electrode is provided on the second surface.
The thickness of the silicon carbide substrate is t, the length in the first direction when the first region is viewed in a plane is Wdx, and the length in the first direction when the second electrode is viewed in a plane is Wsx. If,
Wdx> Wsx + 2t
And
When the length in the second direction orthogonal to the first direction in which the first region is viewed in a plane is Wdy, and the length in the second direction in which the second electrode is viewed in a plane is Wsy. ,
Wdy> Wsy + 2t
The semiconductor chip according to any one of claims 1 to 7.
The semiconductor chip according to claim 8, wherein in the first direction and the second direction, the first region is wider than t on both sides of the second electrode.
The semiconductor chip according to any one of claims 1 to 9, wherein the concentration of silicon contained in the first region is 32 wt% or more and 49 wt% or less.
A step of preparing a silicon carbide substrate having a first surface and a second surface opposite to the first surface, and
A step of forming an element region on the second surface of the silicon carbide substrate, and
The step of grinding the first surface of the silicon carbide substrate and
A step of forming a metal film on the ground first surface, and
A step of forming silicide on a part of the metal film by irradiating the first surface with a laser beam, and
Have,
The second surface of the ground silicon carbide substrate is curved in a concave shape.
The amount of warpage in the first direction and the second direction orthogonal to each other in the first surface viewed in a plan view between the step of grinding the first surface and the step of forming silicide on a part of the metal film. It comprises a step of defining a plurality of first regions that are long in a large direction and a second region between the first regions.
A method for manufacturing a semiconductor chip, which comprises a step of irradiating the first region with a laser beam without irradiating the second region with a laser beam, in a step of forming VDD on a part of the metal film.
The method for manufacturing a semiconductor chip according to claim 11, wherein the amount of warpage of the second surface of the silicon carbide substrate ground in the step of grinding the first surface of the silicon carbide substrate is 1 μm or more and 500 μm or less.
The method for manufacturing a semiconductor chip according to claim 11 or 12, wherein the metal film contains nickel or titanium.
The method according to any one of claims 11 to 13, further comprising a step of forming a silicon film between the step of forming the metal film and the step of forming silicide on a part of the metal film. A method for manufacturing a semiconductor chip.
The method for manufacturing a semiconductor chip according to any one of claims 11 to 14, wherein the size of the silicon carbide substrate is 6 inches or more.
The method for manufacturing a semiconductor chip according to any one of claims 11 to 15, wherein the first region is a strip-shaped strip.
The method for manufacturing a semiconductor chip according to any one of claims 11 to 16, further comprising a step of forming the silicide on a part of the metal film and then separating the silicon carbide substrate into chips by dicing. ..
The semiconductor chip manufacturing method according to claim 17, wherein the chipped semiconductor chip has a rectangular shape in the first region in a plan view.
The shape of the chipped semiconductor chip in a plan view is rectangular.
The method for manufacturing a semiconductor chip according to claim 18, wherein the length of the long side of the first region is the same as one side of the semiconductor chip.
The method for manufacturing a semiconductor chip according to claim 17 or 18, wherein the first region is surrounded by the second region in a plan view of the chipped semiconductor chip.
The chipped semiconductor chip has any of claims 17 to 20, wherein the area of the first region with respect to the area of the first surface of the semiconductor chip is 75% or more and 96% or less in plan view. The method for manufacturing a semiconductor chip according to claim 1.