JPS61163635A - Semiconductor impurity doping device - Google Patents
Semiconductor impurity doping deviceInfo
- Publication number
- JPS61163635A JPS61163635A JP468285A JP468285A JPS61163635A JP S61163635 A JPS61163635 A JP S61163635A JP 468285 A JP468285 A JP 468285A JP 468285 A JP468285 A JP 468285A JP S61163635 A JPS61163635 A JP S61163635A
- Authority
- JP
- Japan
- Prior art keywords
- impurity
- semiconductor wafer
- electron beam
- thin film
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000010894 electron beam technology Methods 0.000 claims abstract description 32
- 239000010409 thin film Substances 0.000 claims abstract description 20
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 7
- 230000001133 acceleration Effects 0.000 claims description 9
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 16
- 238000010438 heat treatment Methods 0.000 abstract description 9
- 230000005672 electromagnetic field Effects 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 9
- 239000010410 layer Substances 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 238000004949 mass spectrometry Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000010019 resist printing Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
く技術分野〉
本発明は半導体不純物添加装置、より詳しくは、［ＬＳ
Ｉのウニハエ程においてフォトレジストの次工程である
不純物をウェハに添加する工程を行なう半導体不純物添
加装置に関する。[Detailed Description of the Invention] Technical Field> The present invention relates to a semiconductor impurity doping device, more specifically, [LS
The present invention relates to a semiconductor impurity doping apparatus that performs a step of adding impurities to a wafer, which is the next step of photoresist processing in the wafer process.
〈従来技術〉
超ＬＳＩの製造プロセスにおけるウニハエ程では、半導
体ウェハにレジストを印刷し、光、Ｘ線あるいは電子ビ
ーム等により露光し、露光部分のみをプラズマアッシン
グもしくはプラズマエツチングによって取り除く。次に
、イオン注入法により、イオン化した不純物を電界によ
り加速して半導体ウェハのレジストが除去された部分に
打込み、不純物を半導体ウェハに注入してｐｎ反転層を
形成する。<Prior Art> In the process of manufacturing a VLSI, a resist is printed on a semiconductor wafer, exposed to light, X-rays, or an electron beam, and only the exposed portion is removed by plasma ashing or plasma etching. Next, using an ion implantation method, ionized impurities are accelerated by an electric field and implanted into the portion of the semiconductor wafer from which the resist has been removed, and the impurities are implanted into the semiconductor wafer to form a pn inversion layer.
第４図はイオン注入装置の構成を示す。イオン源１０１
では、加熱によって発生した金属蒸気に熱電子を照射し
てイオン化する。イオンを電界によって加速及び集束し
、質量分析系１０２に導く。FIG. 4 shows the configuration of the ion implantation device. Ion source 101
Then, the metal vapor generated by heating is ionized by irradiating thermionic electrons. The ions are accelerated and focused by an electric field and guided to the mass spectrometry system 102.
質量分析されたイオンは、注入系１０３においてその運
動エネルギが設定値になるように加速もしくは減速され
、半導体ウェハ１０４に照射される。The mass-analyzed ions are accelerated or decelerated in the implantation system 103 so that their kinetic energy reaches a set value, and are irradiated onto the semiconductor wafer 104.
半導体ウェハ１０４のイオンの注入層厚さはイオン加速
電圧で制御され、イオンの注入量はイオン電流で制御さ
れる。The thickness of the ion implantation layer of the semiconductor wafer 104 is controlled by the ion acceleration voltage, and the amount of ions implanted is controlled by the ion current.
このイオン注入法では、イオンが半導体ウェハ１０４の
全面に一様に照射されるので、半導体ウェハ１０４のイ
オンを注入する部分以外の部分に保護膜を形成するため
に、上述のレジスト印刷。In this ion implantation method, ions are uniformly irradiated over the entire surface of the semiconductor wafer 104, so in order to form a protective film on a portion of the semiconductor wafer 104 other than the portion into which ions are to be implanted, the above-described resist printing is performed.
露光、剥離というマスク作成工程が必要になる。A mask creation process of exposure and peeling is required.
また、このイオン注入法では、イオンの打込みによって
半導体ウェハのイオン注入層の結晶格子が乱れ、格子欠
陥密度が大きいばかりでなく、注入した不純物原子も格
子間位置に存在するため、イオン注入を行なっただけで
は不純物は自由キャリアを供給しない。このため、不純
物原子を格子位置におさめて乱れた格子構造をなくし、
不純物原子を電気的に活性化するために、熱処理が必要
になる。しかるに、この熱処理を行なうと、不純物が拡
散して、当初に意図した不純物濃度のプロファイルが得
られない。第５図は不純物の注入直後と熱処理後におけ
るウェハの表面層深さと不純物濃度との関係を示し、実
線が注入直後の不純物濃度、鎖線が熱処理後の不純物濃
度をそれぞれ示す。熱処理により不純物が拡散してウェ
ハの内部深く再分布するのが分る。In addition, in this ion implantation method, the crystal lattice of the ion implanted layer of the semiconductor wafer is disturbed by ion implantation, and not only does the lattice defect density become large, but the implanted impurity atoms also exist in interstitial positions. Impurities alone do not supply free carriers. For this reason, impurity atoms are placed in lattice positions to eliminate the disordered lattice structure,
Heat treatment is required to electrically activate the impurity atoms. However, when this heat treatment is performed, the impurities diffuse and the initially intended impurity concentration profile cannot be obtained. FIG. 5 shows the relationship between the depth of the surface layer of the wafer and the impurity concentration immediately after impurity implantation and after heat treatment, where the solid line represents the impurity concentration immediately after implantation, and the chain line represents the impurity concentration after heat treatment. It can be seen that the heat treatment causes impurities to diffuse and redistribute deep inside the wafer.
〈発明の目的〉
本発明は上記事情に鑑みてなされたものであり、その目
的は、マスク作成工程と熱処理工程を不要とするととも
に、意図した不純物濃度のプロファイルが得られるよう
にした半導体不純物添加装置を提供することである。<Purpose of the Invention> The present invention was made in view of the above circumstances, and its purpose is to provide a semiconductor impurity doping method that eliminates the need for a mask making process and a heat treatment process, and that enables an intended impurity concentration profile to be obtained. The purpose is to provide equipment.
〈発明の構成〉
本発期においては、電子ビーム（レーザビームあるいは
Ｘ線ビーム等のビーム）発生器と、上記電子ビームを加
速する電子ビーム加速系と（レーザビーム、ｘｉｓビー
ムにおいては不要）、この電子ビーム加速系からの電子
ビームあるいは上記ビーム発生器からのレーザビームあ
るいはＸ線ビーム等のビームを半導体ウェハに対して走
査して照射するビーム走査系とを備え、添加すべき不純
物あるいは不純物とバルク物質との化合物の薄膜が形成
された上記半導体ウェハに対して上記ビームを走査して
照射することにより、上記薄膜と上記半導体ウェハの所
要部分のみを溶融させて上記半導体ウェハに上記不純物
の添加層を形成することを特徴とする。<Structure of the Invention> In the present stage, an electron beam (beam such as a laser beam or an X-ray beam) generator, an electron beam acceleration system for accelerating the electron beam (not necessary for a laser beam or an It is equipped with a beam scanning system that scans and irradiates the semiconductor wafer with an electron beam from the electron beam acceleration system or a beam such as a laser beam or an By scanning and irradiating the semiconductor wafer on which a thin film of a compound with a bulk substance is formed, only the thin film and a required portion of the semiconductor wafer are melted, and the impurity is added to the semiconductor wafer. It is characterized by forming a layer.
〈実施例〉 以下、本発明の一実施例について説明する。<Example> An embodiment of the present invention will be described below.
第１図は半導体不純物添加装置の構成を示す。FIG. 1 shows the configuration of a semiconductor impurity doping device.
ビーム加速系３は、電子ビーム発生用フィラメント電源
３１．電子ビーム発生源３２．加速用電源３３、集束用
電源３４からなる。このビーム加速系３では、発生した
電子ビーム１が加速用電源３３と集束用電源３４により
生成される電磁界で加速及び集束され、ビーム走査系４
へ送られる。The beam acceleration system 3 includes a filament power source 31 for generating an electron beam. Electron beam source 32. It consists of an acceleration power source 33 and a focusing power source 34. In this beam acceleration system 3, the generated electron beam 1 is accelerated and focused by an electromagnetic field generated by an acceleration power source 33 and a focusing power source 34, and a beam scanning system 4
sent to.
ビーム走査系４は、静電集束電源４１．４２゜電子ビー
ムスキャニング用電源４３．電子電流測定器４４からな
る。このビーム走査系４では、添加すべき不純物あるい
は不純物とバルク物質との化合物のＷｌ膜が形成された
半導体ウェハ２の所要部分に対して電子ビーム１を走査
して照射し、該部分を溶融させる。電子ビーム１０半導
体ウェハ２に対する走査は、電子ビームスキャニング用
電源４３によって制御される。電子電流測定器４４は、
電子ビームｌの強度を測定する。主として、この電子ビ
ームｌの強度と電子ビームスキャニング用電源４３によ
って制御される電子ビームｌの照射時間とにより、半導
体ウェハ２の不純物の添加層厚さが制御される。一方、
不純物の添加量は、上述の不純物薄膜の膜厚あるいは不
純物とバルク物質との化合物の組成比で制御される。The beam scanning system 4 includes an electrostatic focusing power source 41.42° and an electron beam scanning power source 43. It consists of an electronic current measuring device 44. In this beam scanning system 4, the electron beam 1 is scanned and irradiated onto a desired part of the semiconductor wafer 2 on which a WL film of an impurity to be added or a compound of an impurity and a bulk substance is formed, and the part is melted. . Scanning of the electron beam 10 on the semiconductor wafer 2 is controlled by an electron beam scanning power source 43. The electronic current measuring device 44 is
Measure the intensity of the electron beam l. The thickness of the impurity-doped layer of the semiconductor wafer 2 is mainly controlled by the intensity of the electron beam 1 and the irradiation time of the electron beam 1, which is controlled by the electron beam scanning power source 43. on the other hand,
The amount of impurity added is controlled by the thickness of the impurity thin film described above or the composition ratio of the compound of the impurity and the bulk substance.
第２図（ａ）ないしくｄ）は、上述の半導体不純物添加
装置を用いて半導体ウェハにｐｎ反転層を形成するとき
の各段階における半導体ウェハの断面組成を示す。第２
図（ａ）に示すように、先ず、シリコンウェハ２１の表
面に添加しようとする不純物例えばヒ素、リン、カドミ
ウム等の薄膜もしくはバルク物質と不純物との化合物の
薄膜２２を、分子線ビーム、イオンクラスタービーム、
イオンビーム等で形成する。FIGS. 2(a) to 2d) show the cross-sectional composition of a semiconductor wafer at each stage when a pn inversion layer is formed on a semiconductor wafer using the above-mentioned semiconductor impurity doping apparatus. Second
As shown in Figure (a), first, a thin film 22 of an impurity to be added to the surface of a silicon wafer 21, such as arsenic, phosphorus, cadmium, etc., or a thin film 22 of a compound of a bulk substance and an impurity, is coated with a molecular beam beam or an ion cluster. beam,
Formed using an ion beam, etc.
次に、電子ビーム１を電磁界により偏向して半導体ウェ
ハ上で走査し、第２図（ｂ）に示すように、シリコンウ
ェハ２１の不純物を添加しようとする部分２１ａの上の
薄膜２２ａに向けて電子ビーム１を照射する。このとき
、電子ビーム１は、薄膜２２ａを透過してシリコンウェ
ハ２１の部分２１ｂにまで侵入し、薄膜２２ａとともに
シリコンウェハ２１の部分２ｊａが溶融する。そして、
溶融した不純物あるいは化合物とシリコンとが互いに拡
散する。この電子ビーム１の照射から照射部分の溶融ま
での時間は、数マイクロ秒程度である。この後、電子ビ
ームｌが走査により移動した後の冷却によって、溶融部
分が液相エピタキシープロセスを経て再結晶化し、第２
図（Ｃ）に示すように、ｎ形の不純物添加層２３が形成
される。Next, the electron beam 1 is deflected by an electromagnetic field and scanned over the semiconductor wafer, and as shown in FIG. irradiate with electron beam 1. At this time, the electron beam 1 passes through the thin film 22a and penetrates into the portion 21b of the silicon wafer 21, melting the portion 2ja of the silicon wafer 21 together with the thin film 22a. and,
The molten impurity or compound and silicon diffuse into each other. The time from irradiation with the electron beam 1 to melting of the irradiated portion is approximately several microseconds. After this, by cooling after the electron beam l moves by scanning, the melted part undergoes a liquid phase epitaxy process and recrystallizes, and the second
As shown in Figure (C), an n-type impurity doped layer 23 is formed.
以上の工程の後、不要な薄膜２２をプラズマエツチング
によって除去すると、第２図（ｄｌに示すように、Ｐ形
のシリコンウェハ２１とｎ形の不純物添加層２３からな
るｐｎ反転層が形成される。After the above steps, unnecessary thin film 22 is removed by plasma etching, and as shown in FIG. .
第３図に示す装置は、上述の半導体不純物添加装置であ
るビーム系１１と不純物または化合物の薄膜を形成する
薄膜成長系１２とをひとつの真空装置１０の内部に配置
したもので、ターゲットである半導体ウェハ２に異種類
の不純物の連続添加が可能であり、さらに、３次元集積
素子の作成が可能である。The apparatus shown in FIG. 3 has a beam system 11, which is the above-mentioned semiconductor impurity doping apparatus, and a thin film growth system 12, which forms a thin film of impurities or compounds, arranged inside one vacuum apparatus 10. It is possible to continuously add different types of impurities to the semiconductor wafer 2, and furthermore, it is possible to create three-dimensional integrated devices.
なお、本実施例では半導体ウェハに照射するビームとし
て電子ビームを用いたが、他にレーザビーム、Ｘ線等を
用いることもできる。In this embodiment, an electron beam was used as the beam to irradiate the semiconductor wafer, but other laser beams, X-rays, etc. may also be used.
〈発明の効果〉
以上説明したように、本発明においては、電子ビーム等
を不純物あるいは不純物の化合物の薄膜が形成された半
導体ウェハに対して走査して照射し、薄膜と半導体ウェ
ハの所要部分のみを溶融させて不純物を添加するように
したので、従来のマスク作成工程が不要であり、さらに
、不純物の添加が熱平衡状態で行なわれるので、不純物
の活性化のための熱処理工程が不要になる。<Effects of the Invention> As explained above, in the present invention, an electron beam or the like is scanned and irradiated onto a semiconductor wafer on which a thin film of an impurity or a compound of impurities is formed, and only the thin film and the required portions of the semiconductor wafer are irradiated. Since the impurities are added by melting the impurities, there is no need for the conventional mask making process.Furthermore, since the impurities are added in a thermal equilibrium state, there is no need for a heat treatment process to activate the impurities.
また、本発明においては、ビームの照射部分が数マイク
ロ秒程度で溶融するので、短時間で不純物添加プロセス
が完了し、不純物の拡散によって熱的再分布がほとんど
なく、当初意図した不純物濃度のプロファイルが得られ
る。さらに、溶融部分のみに不純物を均一に添加できる
ことから、従来のイオン注入法や熱拡散法に比べて、添
加層厚がより浅く、さらにより急峻なｐｎ接合が形成で
きる。In addition, in the present invention, the irradiated part of the beam melts in about a few microseconds, so the impurity addition process is completed in a short time, and there is almost no thermal redistribution due to impurity diffusion, resulting in the originally intended impurity concentration profile. is obtained. Furthermore, since the impurity can be added uniformly only to the molten portion, the thickness of the added layer is shallower and a steeper pn junction can be formed compared to conventional ion implantation or thermal diffusion methods.
さらに、本発明においては、ビームの強度や照射時間を
制御することにより、不純物の高密度添加が可能となり
、トンネル効果素子を作成することができる。また、不
純物添加プロセスと不純物の薄膜形成プロセスをひとつ
の真空装置において行なうことができるので、異！！類
の不純物の連続添加及び３次元集積素子の作成が可能で
ある。Furthermore, in the present invention, by controlling the beam intensity and irradiation time, it is possible to add impurities at a high density, thereby making it possible to create a tunnel effect element. In addition, the impurity addition process and the impurity thin film formation process can be performed in one vacuum device, making it completely different! ! It is possible to continuously add similar impurities and create three-dimensional integrated devices.
第１図は本発明実施例の構成を示すブロック図、第２図
（ａｌ、 （ｂ）、 （ｃ）、 （ｄ）は本発明実施例
の半導体ウェハの断面組成を示す図、第３図は本発明実
施例のビーム系と薄膜成長系とを配置した真空装置の概
略構成を示す図、第４図は従来例のイオン注入装置の構
成を示すブロック図、第５図は従来例の不純物濃度分布
を示すグラフである。
ｌ−・−電子ビーム ２−・半導体ウェハ３−ビ
ーム加速系 ４−ビーム走査系２１− シリコンウ
ェハ ２２−１膜
２３・−・不純物添加層FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 4 is a block diagram showing the configuration of a conventional ion implantation device, and FIG. 5 is a diagram showing the configuration of a conventional ion implantation device. It is a graph showing the concentration distribution. 1-・-Electron beam 2-・Semiconductor wafer 3-Beam acceleration system 4-Beam scanning system 21- Silicon wafer 22-1 Film 23・-・Impurity doped layer
Claims (2)
のビーム）発生器と、上記電子ビームを加速する電子ビ
ーム加速系と（レーザビーム、Ｘ線ビームにおいては不
要）、この電子ビーム加速系からの電子ビームあるいは
上記ビーム発生器からのレーザビームあるいはＸ線ビー
ム等のビームを半導体ウェハに対して走査して照射する
ビーム走査系とを備え、添加すべき不純物あるいは不純
物とバルク物質との化合物の薄膜が形成された上記半導
体ウェハに対して上記ビームを走査して照射することに
より、上記薄膜と上記半導体ウェハの所要部分のみを溶
融させて上記半導体ウェハに上記不純物の添加層を形成
することを特徴とする半導体不純物添加装置。(1) An electron beam (beam such as a laser beam or an X-ray beam) generator, an electron beam acceleration system that accelerates the electron beam (not necessary for a laser beam or an A beam scanning system that scans and irradiates a semiconductor wafer with an electron beam, a laser beam, an X-ray beam, etc. from the beam generator, and a thin film of an impurity to be added or a compound of an impurity and a bulk substance. By scanning and irradiating the semiconductor wafer on which the semiconductor wafer is formed, the thin film and only the required portions of the semiconductor wafer are melted, thereby forming the impurity-added layer on the semiconductor wafer. Semiconductor impurity doping equipment.
として上記ビームの強度と照射時間で制御し、上記不純
物の添加量は上記不純物薄膜の膜厚あるいは上記化合物
の組成比で制御する特許請求の範囲第１項記載の半導体
不純物添加装置。(2) A patent claim in which the thickness of the impurity-added layer of the semiconductor wafer is controlled mainly by the intensity and irradiation time of the beam, and the amount of the impurity added is controlled by the thickness of the impurity thin film or the composition ratio of the compound. The semiconductor impurity doping device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP468285A JPS61163635A (en) | 1985-01-14 | 1985-01-14 | Semiconductor impurity doping device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP468285A JPS61163635A (en) | 1985-01-14 | 1985-01-14 | Semiconductor impurity doping device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61163635A true JPS61163635A (en) | 1986-07-24 |
Family
ID=11590660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP468285A Pending JPS61163635A (en) | 1985-01-14 | 1985-01-14 | Semiconductor impurity doping device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61163635A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5183780A (en) * | 1990-02-22 | 1993-02-02 | Sanyo Electric Co., Ltd. | Method of fabricating semiconductor device |
| JPH11169416A (en) * | 1997-12-15 | 1999-06-29 | Toshiba Tec Corp | Air massage machine |
-
1985
- 1985-01-14 JP JP468285A patent/JPS61163635A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5183780A (en) * | 1990-02-22 | 1993-02-02 | Sanyo Electric Co., Ltd. | Method of fabricating semiconductor device |
| JPH11169416A (en) * | 1997-12-15 | 1999-06-29 | Toshiba Tec Corp | Air massage machine |
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