CN109727851A - Multiple-interval exposure pattern and preparation method thereof - Google Patents
Multiple-interval exposure pattern and preparation method thereof Download PDFInfo
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- CN109727851A CN109727851A CN201711049885.4A CN201711049885A CN109727851A CN 109727851 A CN109727851 A CN 109727851A CN 201711049885 A CN201711049885 A CN 201711049885A CN 109727851 A CN109727851 A CN 109727851A
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- 238000005530 etching Methods 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims description 201
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- 229910015900 BF3 Inorganic materials 0.000 claims description 6
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 6
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- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 49
- SYHGEUNFJIGTRX-UHFFFAOYSA-N methylenedioxypyrovalerone Chemical compound C=1C=C2OCOC2=CC=1C(=O)C(CCC)N1CCCC1 SYHGEUNFJIGTRX-UHFFFAOYSA-N 0.000 claims 1
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- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
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Abstract
The invention provides a multiple-interval exposure pattern and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate, and forming a polycrystalline silicon layer on the semiconductor substrate, wherein the polycrystalline silicon layer comprises a plurality of polycrystalline silicon units, and a gap is generated between the polycrystalline silicon units; carrying out ion doping on the side face of the polycrystalline silicon unit to enable the polycrystalline silicon unit to be exposed at the side part of the gap to form a doped part, wherein the polycrystalline silicon unit is also provided with an intrinsic part which is adjacent to the doped part and is not subjected to ion doping, and the etching rate of the doped part is far less than that of the intrinsic part; and etching the intrinsic part by adopting a specific etching selection ratio so as to remove the intrinsic part and reserve the doped part. Through the scheme, the method provided by the invention effectively solves the problem that the existing exposure and development technology reaches the physical limit, can obtain the semiconductor pattern structure with a miniature linear diameter, has simple process, is not easily influenced by the outside, and obtains the pattern with accurate size and easy control.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, more particularly to a kind of multiple spacing exposing patterns and its preparation side
Method and using double exposure pattern formation technology that radial line is miniature method in semiconductor structure preparation.
Background technique
As the integrated level of semiconductor chip is continuously improved, the characteristic size of transistor constantly reduces, to photoetching process
It challenges also increasing.As the line footpath of dynamic RAM (DRAM) reduces, waterfall photo development processes (immersion) have reached
To its physics limit, although line footpath is may be implemented in EUV waterfall photo development processes miniature, but will not be used in a short time, this light
Lithography is not solved there are many more technological difficulties, such as cost of equipment valuableness.
Currently, in semiconductor preparing process, double-exposure technique in traditional photoetching technique by continuous exposure come
The imaging for realizing small size figure, so as to cause the interest of more and more researchers, by double exposure pattern formation technology
(Double patterning-Pitch Double) is miniature by line footpath.
However, the main way of realization of current double-exposure technique has photoetching-etching-photoetching-etching or photoetching-light
Quarter-techniques such as etching, these techniques need complicated step mostly, and cost is much larger than conventional exposure technology, some need into
Row photoresist curing process etc. is affected by the external environment big, is difficult to control.
Therefore, a kind of semiconductor structure preparation method for being related to double exposure pattern formation technology how is provided, to solve
The problems such as exposure development technique has reached physics limit and pattern forming technology complexity, is difficult to control in the prior art belongs in fact
It is necessary.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of multiple spacing exposing patterns and
Preparation method, for solve exposure development technique in the prior art have reached physics limit and pattern forming technology it is complicated,
The problems such as not easy to control.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation side of multiple spacing exposing patterns
Method, comprising steps of
1) semiconductor substrate is provided, and in forming polysilicon layer, and the polysilicon layer packet on the semiconductor base
Several polysilicon units are included, generate a gap between the polysilicon unit；
2) ion doping is carried out for the side of the polysilicon unit, the polysilicon unit is made to be revealed in the gap
Side be formed as doping, and the polysilicon unit separately has and does not carry out adjacent to the doping and ion doping again
Intrinsic portion, wherein the etch rate of the doping is much smaller than the etch rate in the intrinsic portion；And
3) the intrinsic portion is compared using specific etching selection to perform etching, mixed described in the intrinsic portion and reservation with removing
Miscellaneous portion.
As a preferred solution of the present invention, in step 1), the step of forming the polysilicon layer, includes:
1-1) Yu Suoshu semiconductor substrate surface forms one layer of polysilicon material layer；
1-2) Yu Suoshu polycrystalline silicon material layer surface forms a layer photoresist layer, and the graphical photoresist layer；And
1-3) polysilicon material layer is performed etching using the patterned photoresist layer as exposure mask, includes to be formed
The polysilicon layer of several polysilicon units and remaining photoresist layer positioned at the polysilicon layer surface.
As a preferred solution of the present invention, in step 2), ion is carried out in the side of each polysilicon unit and is mixed
Miscellaneous step includes:
So that the semiconductor base is in first direction inclination, is exposure mask to described more using the remaining photoresist layer
Crystal silicon layer carries out first time ion implanting with first angle, to form the first injection in the first side of each polysilicon unit
Area；
It 2-2) rotates the semiconductor base to second direction to tilt, continues using the remaining photoresist layer to be exposure mask to institute
It states polysilicon layer and second of ion implanting is carried out with second angle, in the formation of the second side of each polysilicon unit and institute
State the second opposite injection region of the first injection region, wherein mix described in first injection region and second injection region composition
Miscellaneous portion, not ion implanted region constitutes the intrinsic portion in the polysilicon unit.
As a preferred solution of the present invention, the first angle and the second angle are according to the adjacent polycrystalline
The depth-to-width ratio for the groove that gap between silicon unit is constituted is set, and reaches the area injected with control injection ion
Domain, to form first injection region and second injection region.
As a preferred solution of the present invention, each polysilicon unit is parallel and is equidistantly intervally arranged, and described the
The differential seat angle of one direction and the second direction is 180 °, and the first angle is equal with the second angle.
As a preferred solution of the present invention, step 2-1) in, the first angle is 10 °~70 °, the first time
The implantation dosage of ion implanting is 5E+13 to 1E+15 atom/square centimeter, and Implantation Energy is 1~20KeV, first injection
The width in area is 3.3~66nm；Step 2-2) in, the second angle is 10 °~70 °, the note of second of ion implanting
Entering dosage is 5E+13 to 1E+15 atom/square centimeter, and Implantation Energy is 1~20KeV, and the width of second injection region is
3.3~66nm.
As a preferred solution of the present invention, in step 2), ion is carried out in the two sides of each polysilicon unit and is mixed
Miscellaneous step includes:
2-1) using the remaining photoresist layer as exposure mask, and to the semiconductor base in a manner of rectilinear ion implanting
Region corresponding to surface carries out ion implanting, in the formation edge doped region of the two sides of each polysilicon unit；
2-2) the obtained structure of step 2-1) is made annealing treatment, is diffused the edge doped region, with shape
Region at the doping, and in each polysilicon unit without diffusion constitutes the intrinsic portion.
As a preferred solution of the present invention, step 2-2) in, the step of forming the doping are as follows:
After 2-2-1) making annealing treatment to the structure that step 2-1) is obtained, the edge doped region diffuses to form diffusion
Area, wherein the diffusion region include the doping to be formed the first diffusion region and be located at first diffusion region both ends
And perpendicular to the second diffusion region of first diffusion region；
2-2-2) surface of the structure obtained by step 2-2-1) forms one layer of etching barrier layer, and the etching barrier layer is sudden and violent
Expose second diffusion region；
2-2-3) using the etching barrier layer as exposure mask, second diffusion region is removed using etching technics；And
The remaining etching barrier layer 2-2-4) is removed, to form the doping being intervally arranged, and it is adjacent described
The region without diffusion between doping constitutes the intrinsic portion.
As a preferred solution of the present invention, step 2-1) in, the implantation dosage of the ion implanting is 3E+15 to 8E
+ 16 atoms/square centimeter, Implantation Energy are 0.2~10KeV；Step 2-2) in, the temperature of the annealing is 900~
1200 DEG C, width of the edge doped region after spreading is 3.3~66nm, and length of the edge doped region after spreading is
1.5~3nm.
As a preferred solution of the present invention, in step 2), ion is carried out in the two sides of each polysilicon unit and is mixed
Miscellaneous step includes:
So that the semiconductor base is in first direction, to the polysilicon layer with first angle carry out for the first time from
Son injection, to form the first injection region in the side of each polysilicon unit；
2-2) rotate the semiconductor base to second direction, to the polysilicon layer with second angle carry out second from
Son injection, to form second injection region opposite with first injection region, and institute in the other side of each polysilicon unit
It states the first injection region and second injection region and collectively covers the top without ion implanted regions in the polysilicon unit
Portion and lateral wall；And
2-3) by dry etch process remove the region by ion implanting at the top of each polysilicon unit until
Expose not ion implanted region, wherein remaining first injection region and remaining second injection region structure
At the doping, not ion implanted region constitutes the intrinsic portion in the polysilicon unit.
As a preferred solution of the present invention, the first angle and the second angle are according to the adjacent polycrystalline
The depth-to-width ratio for the groove that gap between silicon unit is constituted is set, and reaches the area injected with control injection ion
Domain, to form first injection region and second injection region.
As a preferred solution of the present invention, each polysilicon unit is equidistantly intervally arranged in parallel, and described first
The differential seat angle of direction and the second direction is 180 °, and the first angle is equal with the second angle.
As a preferred solution of the present invention, in step 1), the semiconductor base includes the stacking on substrate
Gate structure, the stacked gate architectures include: the grid oxic horizon positioned at the substrate surface；Positioned at the grid oxic horizon
The polysilicon layer on surface；And the metal layer positioned at the polysilicon layer surface.
As a preferred solution of the present invention, one layer of diffusion resistance is also formed between the polysilicon layer and the metal layer
Barrier；The layer on surface of metal also forms one layer of grid protection layer.
As a preferred solution of the present invention, in step 3), specific etching selection ratio includes using the default etching
Liquid is to the etch rate in the intrinsic portion greater than the default etching liquid to 15 times of the doping etch rate.
As a preferred solution of the present invention, in step 3), the default etching liquid be alkaline etch solution, it is described from
Any one of Doped ions in the group that boron, arsenic, phosphorus and boron fluoride are constituted in sub- doping process.
The present invention also provides a kind of multiple spacing exposing patterns, comprising:
Semiconductor substrate；And
Polysilicon layer is formed on the semiconductor base, and the polysilicon layer includes several polysilicon units, institute
State between polysilicon unit one first gap of generation, the polysilicon unit have be revealed in the doping in first gap with
And the intrinsic portion of ion doping is not being carried out adjacent to the doping and, wherein the etch rate of the doping is much smaller than
The etch rate in the intrinsic portion；
Wherein, when performing etching removal using the specific etching selection comparison intrinsic portion, the doping retains, same
One second gap is generated between the doping of polysilicon unit.
As a preferred solution of the present invention, the Doped ions of the doping are selected from boron, arsenic, phosphorus and boron fluoride institute
Any one in the group of composition.
As a preferred solution of the present invention, the semiconductor base includes the stacked gate architectures on substrate,
The stacked gate architectures include: the grid oxic horizon positioned at the substrate surface；Positioned at the more of the gate oxidation layer surface
Crystal silicon layer；And the metal layer positioned at the polysilicon layer surface.
As a preferred solution of the present invention, one layer of diffusion resistance is also formed between the polysilicon layer and the metal layer
Barrier；The layer on surface of metal also forms one layer of grid protection layer.
As described above, multiple spacing exposing patterns and preparation method thereof of the invention, have the advantages that
The forming methods of multiple spacing exposing patterns provided by the invention, the existing exposure development technology of effective solution
The method and process of limited problem, the miniature semiconductor pattern structure of available line footpath, double exposure development is simple, is not easy
It is influenced by the external world, obtains the accurate size of pattern, it is easily controllable, and can be omitted the work of excess stock layer removal (chopping)
Skill.
Detailed description of the invention
Fig. 1 is shown as the process flow chart of multiple spacing exposing patterns preparation method provided by the invention.
The structure that Fig. 2 is shown as providing semiconductor base in multiple spacing exposing patterns preparation method provided by the invention is shown
It is intended to.
Fig. 3 is shown as forming the structural representation of polysilicon layer in multiple spacing exposing patterns preparation method provided by the invention
Figure.
The structure that Fig. 4 is shown as in multiple spacing exposing patterns preparation method provided by the invention after progress ion doping is shown
It is intended to.
Fig. 5, which is shown as being formed in multiple spacing exposing patterns preparation method provided by the invention, has double exposure pattern
The structural schematic diagram of polysilicon layer.
Fig. 6 is shown as forming the first polysilicon material layer in multiple spacing exposing patterns preparation method provided by the invention
Structural schematic diagram.
Fig. 7 is shown as forming the structural representation of photoresist layer in multiple spacing exposing patterns preparation method provided by the invention
Figure.
Fig. 8 is shown as the structure in multiple spacing exposing patterns preparation method provided by the invention after graphical photoresist layer
Schematic diagram.
Fig. 9 is shown as forming the structural representation of polysilicon layer in multiple spacing exposing patterns preparation method provided by the invention
Figure.
Figure 10 is shown as a kind of showing for ion doping method in multiple spacing exposing patterns preparation method provided by the invention
It is intended to.
Figure 11 is shown with Figure 10 method and carries out the structural schematic diagram obtained after ion doping.
Figure 12 is shown as showing the structure obtained after being corroded using the structure after Figure 10 method progress ion implanting
It is intended to.
Figure 13 is shown as another ion doping method in multiple spacing exposing patterns preparation method provided by the invention
Schematic diagram.
Figure 14 is shown with Figure 13 method and carries out the structural schematic diagram obtained after ion doping.
Figure 15 is shown as the structural representation after annealing to the structure for obtain after ion doping using Figure 13 method
Figure.
Figure 16 is shown as Figure 15 and obtains the top view of structure.
Structure re-forms photoresist layer to remove the signal of extra diffusion region after Figure 17 is shown as the annealing obtained to Figure 15
Figure.
Structure removes the top view after extra diffusion layer after Figure 18 is shown as the annealing obtained to Figure 15.
Figure 19 is shown as another ion doping method in multiple spacing exposing patterns preparation method provided by the invention
Schematic diagram.
Figure 20 is shown with Figure 19 method and carries out the structural schematic diagram obtained after ion doping.
Figure 21 is shown as to using the structural schematic diagram after removal top layer doped region after Figure 19 method progress ion implanting.
Figure 22 is shown as the semiconductor underlying structure provided in multiple spacing exposing patterns preparation method of the invention.
The multiple spacing exposing patterns that Figure 23 is shown as of the invention prepare the semiconductor base and polycrystalline provided in an example
Si layer structure.
Figure 24 is shown as the structural schematic diagram for modifying the polysilicon layer in Figure 23 structure.
Figure 25 is shown as the structure of the deposition side wall of the polysilicon layer surface after modification.
Figure 26 is shown as removing the structural schematic diagram after extra side wall.
Figure 27 is shown as the polysilicon layer after removal modification and retains the double exposure pattern schematic diagram of side wall formation.
Component label instructions
11 semiconductor bases
111 substrates
112 grid oxic horizons
113 polysilicon layers
114 diffusion barrier layers
115 metal layers
116 grid protection layers
12 polysilicon layers
121 polysilicon units
13 intrinsic portions
14 doping
15 polysilicon layers with double exposure pattern
16 polysilicon material layers
17 photoresist layers
171 patterned photoresist layers
18 diffusion regions
19 without diffusion region
20 edge doped regions
201 first diffusion regions
202 second diffusion regions
21 etching barrier layers
22 not ion implanted regions
23 ion implanted regions
31 semiconductor bases
32 photoresist layers
33 modified photoresist layers
34 side walls
35 side walls with double exposure pattern
S1~S3 step 1)~step 3)
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 27.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout form may also be increasingly complex.
As shown in Figure 1, the present invention provides a kind of preparation method of semiconductor structure, include the following steps:
1) semiconductor substrate is provided, and in forming polysilicon layer, and the polysilicon layer packet on the semiconductor base
Several polysilicon units are included, generate a gap between the polysilicon unit；
2) ion doping is carried out for the side of the polysilicon unit, the polysilicon unit is made to be revealed in the gap
Side be formed as doping, and the polysilicon unit separately has and is not carrying out adjacent to the doping and ion doping
Intrinsic portion, wherein the etch rate of the doping is much smaller than the etch rate in the intrinsic portion；And
3) the intrinsic portion is compared using specific etching selection to perform etching, mixed described in the intrinsic portion and reservation with removing
Miscellaneous portion.
The preparation method of semiconductor structure of the invention is discussed in detail below in conjunction with attached drawing.
Shown in S1 as shown in figure 1 and Fig. 2~3, Fig. 6~9, step 1) is carried out, provides semiconductor substrate 11, and in described
Polysilicon layer 12 is formed on semiconductor base 11, and the polysilicon layer 12 includes several polysilicon units 121, the polycrystalline
A gap is generated between silicon unit 121；
Specifically, the semiconductor base 11 is selected according to actual demand, can be further etched for any needs
Structure, such as can be gate structure to be formed structure sheaf, can be layer of material layer, or two layers and more than
The laminated material bed of material, be not particularly limited herein.In addition, the polysilicon layer 12 formed on 11 surface of semiconductor base
It is subsequent that required patterning will be formed by double exposure developing technique, wherein described more in the polysilicon layer 12
Size, shape, quantity and arrangement of crystal silicon unit 121 etc. are selected according to actual demand, it is preferable that in the present embodiment,
The identical polysilicon unit 121 of the evenly sized shape of each polysilicon unit 121, each polysilicon unit 121 it is parallel and
Equidistantly it is intervally arranged.
It should be noted that when the semiconductor base 11 is the structure sheaf of gate structure to be formed, it is adjacent described more
The area of grid of the corresponding formation of being etched in gap between crystal silicon unit 121, i.e., between the adjacent polysilicon unit 121
Width is the grid width of institute's gate structure to be formed, and as critical size CD in the present embodiment, determines in order to illustrate aspect
Justice is b, and the thickness of the polysilicon layer 12 is defined as a, as shown in having in Figure 10 and 13.
As an example, as shown in Fig. 6~9, in step 1), the step of forming polysilicon layer 12, includes:
1-1) 11 surface of Yu Suoshu semiconductor base forms one layer of polysilicon material layer 16；
1-2) 16 surface of Yu Suoshu polysilicon material layer forms a layer photoresist layer 17, and the graphical photoresist layer；
And
It is 1-3) that exposure mask performs etching the polysilicon material layer 16 with the patterned photoresist layer 171, with shape
At the polysilicon layer 12 for including several polysilicon units 121 and the remaining photoetching positioned at 12 surface of polysilicon layer
Glue-line.
Specifically, atomic deposition processing procedure (Atomic Layer Deposition) or plasma vapor deposition can be used
(Chemical Vapor Deposition) film forms the polysilicon material layer 16, and in the polysilicon material layer 16
Surface forms the patterned photoresist layer, and figure corresponds to the figure of subsequent the polysilicon unit 121 to be formed,
Again by the technique of etching, to form the polysilicon layer 12, at this point, being respectively formed on one in each polysilicon unit 121
Divide remaining photoresist, i.e., there are one layer of remaining photoresist layer, this layer of remaining photoresist layer can be gone before subsequent technique
It removes, is also used as the middle mask layer structure of subsequent technique, selected according to actual process.
As shown in figure 22, as an example, in step 1), the semiconductor base 11 includes the stacking on substrate 111
Gate structure, the stacked gate architectures include: the grid oxic horizon 112 positioned at 111 surface of substrate；Positioned at the grid
The polysilicon layer 113 on 112 surface of oxide layer；And the metal layer 115 positioned at 113 surface of polysilicon layer.
As an example, also forming one layer of diffusion barrier layer 114 between the polysilicon layer 113 and the metal layer 115；Institute
It states 115 surface of metal layer and also forms one layer of grid protection layer 116.
Specifically, the substrate 111 can be ripe for those of ordinary skill in the art such as silicon substrate, silicon-on-insulator substrates
Any substrate known, the grid oxic horizon 112 include but is not limited to silica；The metal layer 115 includes but is not limited to
Metal tungsten layer；The diffusion barrier layer 114 includes but is not limited to titanium nitride layer, as the expansion between tungsten metal layer and polysilicon layer
Dissipate barrier layer；The grid protection layer 116 includes but is not limited to that silicon nitride layer is such as being subsequently formed for protecting gate structure
When the doping 14, diffusion ion accumulation scattering is unlikely to damage gate structure.
Shown in S2 and Fig. 4, Figure 10~21 as shown in figure 1, step 2) is carried out, for the side of the polysilicon unit 121
Ion doping is carried out, the side for making the polysilicon unit 121 be revealed in the gap is formed as doping 14, and the polycrystalline
Silicon unit 121 separately has adjacent to the doping 14 and does not carry out the intrinsic portion 13 of ion doping, wherein the doping 14
Etch rate be much smaller than the intrinsic portion 13 etch rate；
It should be noted that the processing by the step, forms two class formations in each polysilicon unit 121, it is a kind of
It is undoped polysilicon, referred to as intrinsic portion 13, one is the structures after overdoping, referred to as doping 14, wherein pass through
Material after doping, the characteristic with certain resistance to etching solution etching have and slow down by ammonia such as by the material of boron ion doping
The characteristic of water etching, and the present invention is based on this, and use ion implantation apparatus, can be precisely controlled mix element its inject depth,
Concentration, the technology of specific region provide a kind of double exposure pattern formation technology.In addition, formed the doping 14 and
Structure, the quantity in the intrinsic portion 13 etc. and actual demand selection.
For the method that the side of each polysilicon unit 121 carries out ion doping, specifically below in conjunction with attached drawing
It is bright, wherein for being formed with the structure of remaining photoresist layer before carrying out ion doping, to provide the following two kinds mode:
As shown in Figure 10~12, as an example, one of doping way is provided, in step 2), in each polysilicon
The two sides of unit 121 carry out the step of ion doping and include:
So that the semiconductor base 11 is in first direction inclination, is exposure mask to described using the remaining photoresist layer
Polysilicon layer 12 carries out first time ion implanting with first angle, is formed with the first side in each polysilicon unit 121
First injection region；
It 2-2) rotates the semiconductor base 11 to second direction to tilt, continue using the remaining photoresist layer as exposure mask pair
The polysilicon layer 12 carries out second of ion implanting with second angle, in the second side of each polysilicon unit 121
Form second injection region opposite with first injection region, wherein first injection region and second injection region structure
At the doping 14, not ion implanted region constitutes the intrinsic portion 13 in the polysilicon unit 121.
Specifically, in this example, using the remaining photoresist layer as exposure mask, by the way of ion implanting twice into
Row ion doping, firstly, implant angle is tilted to by wafer or for semiconductor base, such as first angle, using BL
(Beam Line) tool (ion implantation apparatus type) can be precisely controlled angle (the vertical or special angle) Lai Zhihang of injection from
Son injection, at this point, semiconductor-basedly in first to, such as rotation to 90 ° of direction, so that the first injection region is formed, similarly, according to
The second injection region is formed according to similar operation, wherein rotates the position that the second direction extremely determines the second injection region, such as
Second injection direction selects 270 °, then is formed and set with symmetrical second injection region in the first injection region, foundation actual demand.Institute
It states the first injection region and second injection region and ultimately forms the doping 14, the polysilicon unit except remaining injection region
Just as intrinsic region, the intrinsic region can be finally etched away in region in 121.
In addition, since ion implanting is the angled injection of tool, and have the presence of mask layer, therefore the doping of its formation
And undoped intrinsic portion is not the shape of rule, as shown in figure 11, the top of the entire polysilicon unit does not have completely
There is carry out ion implanting, in this way, intrinsic portion can be eroded by being directly over subsequent corrosion, and remaining doping is by simple
Planarization process the shapes of needs can be obtained, it is even, not through planarization to be directly used as subsequent use.
As an example, the first angle and the second angle are according between the adjacent polysilicon unit 121
The depth-to-width ratio for the groove that gap is constituted is set, and reaches the region injected with control injection ion, to form institute
State the first injection region and second injection region.
As an example, step 2-1) in, the first angle is 10 °~70 °, the injectant of the first time ion implanting
Amount is 5E+13 to 1E+15 atom/square centimeter, and Implantation Energy is 1~20KeV, the width of first injection region is 3.3~
66nm；Step 2-2) in, the second angle is 10 °~70 °, the implantation dosage of second of ion implanting be 5E+13 extremely
1E+15 atom/square centimeter, Implantation Energy are 1~20KeV, and the width of second injection region is 3.3~66nm.
Specifically, the thickness (a) of the selection gist polysilicon layer 12 of the first angle and second angle and crucial ruler
The depth-to-width ratio of very little CD (b, the grid width of design) determines, as described in Figure 10, for example, to the intermediate polysilicon unit 121
When carrying out first time ion implanting, when first angle selects, ion beam cannot be allowed to influence the polysilicon unit 121 in left side,
Preferably, it controls at least a branch of ion beam and injects intermediate polysilicon unit via the 121 upper right side vertex of polysilicon unit in left side
121 lower-left angular vertex, for another example, when depth-to-width ratio a/b is respectively 0.5,1,1.5,2, corresponding first angle be 26.6 °, 45 °,
56.3°,63.4°.Wherein, the doping 14 that the width of first injection region and second injection region as needs to obtain
Width.
Preferably, the first angle is 45 °, the implantation dosage of the first time ion implanting be 2E+14 atom/square
Centimetre, Implantation Energy 10KeV, the width of first injection region is 5nm；The second angle is 45 °, described second from
The implantation dosage of son injection is 2E+14 atom/square centimeter, and Implantation Energy 10KeV, the width of second injection region is
5nm。
As an example, each polysilicon unit 121 is parallel and equidistantly is intervally arranged, the first direction and described the
The differential seat angle in two directions is 180 °, and the first angle is equal with the second angle.
Specifically, forming a kind of double-exposure technique figure relative to the polysilicon layer 12 according to the exemplary selection
Case is to get the doping 14 for having arrived twice 121 quantity of polysilicon unit.
As shown in figure 13 to 18, as an example, providing another doping side under remaining photoresist layer effect
Formula in step 2), includes: in the step of two sides of each polysilicon unit 121 carry out ion doping
2-1) using the remaining photoresist layer as exposure mask, and to the semiconductor base in a manner of rectilinear ion implanting
11 regions corresponding to surface carry out ion implanting, in the formation edge doped region of the two sides of each polysilicon unit 121
20；
2-2) the obtained structure of step 2-1) is made annealing treatment, is diffused the edge doped region 20, with
The doping 14 is formed, and the region in each polysilicon unit 121 without diffusion constitutes the intrinsic portion 13.
Specifically, in this example, using the remaining photoresist layer as exposure mask, carrying out the ion implanting of vertical mode, adopting
The angle (vertical or special angle) of injection can be precisely controlled with BL (Beam Line) tool (ion implantation apparatus type) to hold
Row ion implanting, it is of course also possible to use PLAD (Plasma Doping, plasma formula) mode executes, wherein in exposure mask
Effect in the case of, do not have in ion implanting to polysilicon unit 121, High dose implantation makes ion accumulation semiconductor-based
On the exposed surface in bottom, such as the surface Nitride, and ion scattering mode is generated, the ion of scattering makes 121 liang of polysilicon unit
There is mixing for dosage in side, forms the edge doped region 20, further, needs to carry out a step annealing treatment process, makes the side
It being diffused in the peripherad polysilicon unit 121 of edge doped region 20, the region after diffusion may eventually form the doping 14,
And it can be by the control of annealing condition, further to control the size of the required doping 14 formed.
As an example, step 2-1) in, the implantation dosage of the ion implanting be 3E+15 to 8E+16 atom/square li
Rice, Implantation Energy are 0.2~10KeV；Step 2-2) in, the temperature of the annealing is 900~1200 DEG C, and the edge is mixed
Width of the miscellaneous area 20 after spreading is 3.3~66nm, and length of the edge doped region 20 after spreading is 1.5~3nm.
Preferably, step 2-1) in, the implantation dosage of the ion implanting is 5E+16 atom/square centimeter, Implantation Energy
For 5KeV；Step 2-2) in, the temperature of the annealing is 1000 DEG C, and width of the edge doped region 20 after spreading is
5nm, length of the edge doped region 20 after spreading are 2nm.
As an example, step 2-2) in, the step of forming doping 14 are as follows:
After 2-2-1) making annealing treatment to the structure that step 2-1) is obtained, the edge doped region 20 diffuses to form diffusion
Area 18, remaining is without diffusion region 19, wherein the diffusion region includes the first diffusion region 201 of the doping 14 to be formed
And positioned at 201 both ends of the first diffusion region and perpendicular to the second diffusion region 202 of first diffusion region 201；
2-2-2) surface of the structure obtained by step 2-2-1) forms one layer of etching barrier layer 21, the etching barrier layer
21 expose second diffusion region 202；
It is 2-2-3) exposure mask with the etching barrier layer 21, second diffusion region 202 is removed using etching technics；And
The remaining etching barrier layer is removed, 2-2-4) to form the doping 14 being intervally arranged, and adjacent institute
The region without diffusion stated between doping 14 constitutes the intrinsic portion 13.
It, can be to carrying out around it after the edge doped region 20 is made annealing treatment specifically, as shown in figures 15 to 18
Diffusion surrounds the diffusion region without diffusion region so that being formed, that is, finally formed diffusion region includes first diffusion region
201 and second diffusion region 202, wherein second diffusion region 202 is extra doped region, is needed ultimately forming
It is removed it before stating doping 14, specific practice is that can be gone under the blocking of photoresist by dry etch process
It removes, the top view of formed structure is as shown in figure 18 after removal.
As shown in Figure 19~21, in this example, a kind of example that ion doping is carried out under the effect of no exposure mask is provided,
In step 2), include: in the step of two sides of each polysilicon unit 121 carry out ion doping
So that the semiconductor base 11 is in first direction inclination, the polysilicon layer 12 is carried out with first angle
First time ion implanting, to form the first injection region in the first side of each polysilicon unit 121；
It 2-2) rotates the semiconductor base 11 to second direction to tilt, the polysilicon layer 12 is carried out with second angle
Second of ion implanting, to form opposite with first injection region the in the second side of each polysilicon unit 121
Two injection regions, and first injection region and second injection region are common as shown in 23 structure of label in Figure 20, are covered in
In the polysilicon unit 121 without ion implanted regions as shown in 22 structure of label in 20, top and lateral wall；And
The straight by the region of ion implanting of each 121 top of the polysilicon unit 2-3) is removed by dry etch process
To not ion implanted region is exposed, as shown in figure 21, wherein remaining first injection region and remaining described
Second injection region constitutes the doping 14, and not ion implanted region is constituted described intrinsic in the polysilicon unit 121
Portion 13.
Specifically, in this example, the remaining photoresist layer first in removal previous step technique, using two secondary ions
The mode of injection carries out ion doping, firstly, implant angle is tilted to by wafer or for semiconductor base, such as described first jiao
Degree can be precisely controlled angle (the vertical or specific angle of injection using BL (Beam Line) tool (ion implantation apparatus type)
Degree) Lai Zhihang ion implanting, at this point, semiconductor-basedly in first to as rotated to 90 ° of direction, to form the first note
Enter area, similarly, forms the second injection region according to similar operation, wherein the second direction rotated extremely determines the second note
Enter the position in area, such as the second injection direction selects 270 °, then formed with symmetrical second injection region in the first injection region, first, the
Two injection regions are set as shown in figure label 23 according to actual demand.First injection region and second injection region are most
For end form at the doping 14, the region in polysilicon unit 121 except remaining injection region is described just as intrinsic region
It does kind of meeting and is etched away in intrinsic region.
As an example, the first angle and the second angle are according between the adjacent polysilicon unit 121
The depth-to-width ratio for the groove that gap is constituted is set, and reaches the region injected with control injection ion, to form institute
State the first injection region and second injection region.
As an example, step 2-1) in, the first angle is 10 °~70 °, the injectant of the first time ion implanting
Amount is 5E+13 to 1E+15 atom/square centimeter, and Implantation Energy is 1~20KeV, the width of first injection region is 3.3~
66nm；Step 2-2) in, the second angle is 10 °~70 °, the implantation dosage of second of ion implanting be 5E+13 extremely
1E+15 atom/square centimeter, Implantation Energy are 1~20KeV, and the width of second injection region is 3.3~66nm.
Specifically, the thickness (a) of the selection gist polysilicon layer 12 of the first angle and second angle and crucial ruler
The depth-to-width ratio of very little CD (b, the grid width of design) determines, as described in Figure 10, for example, to the intermediate polysilicon unit 121
When carrying out first time ion implanting, when first angle selects, ion beam cannot be allowed to influence the polysilicon unit 121 in left side,
Preferably, it controls at least a branch of ion beam and injects intermediate polysilicon unit via the 121 upper right side vertex of polysilicon unit in left side
121 lower-left angular vertex, for another example, when depth-to-width ratio a/b is respectively 0.5,1,1.5,2, corresponding first angle be 26.6 °, 45 °,
56.3°,63.4°.Wherein, the doping 14 that the width of first injection region and second injection region as needs to obtain
Width.
Preferably, the first angle is 45 °, the implantation dosage of the first time ion implanting be 2E+14 atom/square
Centimetre, Implantation Energy 10KeV, the width of first injection region is 5nm；The second angle is 45 °, described second from
The implantation dosage of son injection is 2E+14 atom/square centimeter, and Implantation Energy 10KeV, the width of second injection region is
5nm。
As an example, each polysilicon unit 121 is equidistantly intervally arranged in parallel, the first direction and described second
The differential seat angle in direction is 180 °, and the first angle is equal with the second angle.
Specifically, forming a kind of double-exposure technique figure relative to the polysilicon layer 12 according to the exemplary selection
Case is to get the doping 14 for having arrived twice 121 quantity of polysilicon unit.
Shown in S3 and Fig. 5, Figure 12 as shown in figure 1, step 3) is carried out, the intrinsic portion 13 is compared using specific etching selection
It performs etching, to remove the intrinsic portion 13 and retain the doping 14.
Specifically, the step is by adulterating the corrosion that obtained structure carries out the default etching liquid to step 2), from
And the polysilicon layer 15 with double exposure pattern required for obtaining, wherein described more with double exposure pattern
The doping 14 of the resistance to default etching corrosion is only remained in crystal silicon layer 15.
As an example, specific etching selection ratio includes using to be greater than the etch rate in the intrinsic portion 13 in step 3)
15 times to 14 etch rate of doping of the default etching liquid.As an example, the default etching liquid is alkaline etch
Solution, the Doped ions in the ion doping technique are any one in the group that boron, arsenic, phosphorus and boron fluoride are constituted
Kind.
Specifically, the default etching liquid is greater than the default etching liquid to described to the etch rate in the intrinsic portion 13
15 times of 14 etch rate of doping, in the present embodiment, selection is set as 18 times, so as to more effectively by the intrinsic portion
13 erode, to obtain the required polysilicon layer 15 with double exposure pattern.In addition, the doping being doped from
Sub to correspond with the default etching liquid, the material adulterated through the Doped ions must have to slow down by the default quarter
The characteristic of liquid etching is lost, as long as such as hydroxide ion (OH at the alkaline etch solution ionization-), it is excellent in the present embodiment
It is selected as ammonium hydroxide, injection ion and alkaline etch solution use, and need to consider that etching selection ratio, and etching control whether essence in selection
Really, product programming design can be met.
The present invention also provides a kind of multiple spacing exposing patterns, wherein the multiple spacing exposing patterns preferably use
Multiple spacing exposing patterns preparation method in the present embodiment is prepared, and certainly, in other examples, can also use other
Method preparation, is not particularly limited, the multiple spacing exposing patterns include: herein
Semiconductor substrate；And
Polysilicon layer is formed on the semiconductor base, and the polysilicon layer includes several polysilicon units, institute
State between polysilicon unit one first gap of generation, the polysilicon unit have be revealed in the doping in first gap with
And the intrinsic portion of ion doping is not being carried out adjacent to the doping and, wherein the etch rate of the doping is much smaller than
The etch rate in the intrinsic portion；
Wherein, when performing etching removal using the specific etching selection comparison intrinsic portion, the doping retains, same
One second gap is generated between the doping of polysilicon unit.
As an example, the Doped ions of the doping are any in the group that boron, arsenic, phosphorus and boron fluoride are constituted
It is a kind of.
Specifically, the semiconductor base 11 is selected according to actual demand, can be further etched for any needs
Structure, such as can be gate structure to be formed structure sheaf, can be layer of material layer, or two layers and more than
The laminated material bed of material, be not particularly limited herein.In addition, the polysilicon layer 12 formed on 11 surface of semiconductor base
It is subsequent that required patterning will be formed by double exposure developing technique, wherein described more in the polysilicon layer 12
Size, shape, quantity and arrangement of crystal silicon unit 121 etc. are selected according to actual demand, it is preferable that in the present embodiment,
The identical polysilicon unit 121 of the evenly sized shape of each polysilicon unit 121, each polysilicon unit 121 it is parallel and
Equidistantly it is intervally arranged.It should be noted that when the semiconductor base 11 is the structure sheaf of gate structure to be formed, it is adjacent
The area of grid of the corresponding formation of being etched in gap between the polysilicon unit 121, i.e., the adjacent polysilicon unit 121
Between width be gate structure to be formed grid width, as critical size CD.
As an example, the semiconductor base includes the stacked gate architectures on substrate, the stacked gate architectures
It include: the grid oxic horizon positioned at the substrate surface；Positioned at the polysilicon layer of the gate oxidation layer surface；And it is located at institute
State the metal layer on polysilicon layer surface.
As an example, also forming one layer of diffusion barrier layer between the polysilicon layer and the metal layer；The metal layer
Surface also forms one layer of grid protection layer.
Specifically, the substrate 111 can be ripe for those of ordinary skill in the art such as silicon substrate, silicon-on-insulator substrates
Any substrate known, the grid oxic horizon 112 include but is not limited to silica；The metal layer 115 includes but is not limited to
Metal tungsten layer；The diffusion barrier layer 114 includes but is not limited to titanium nitride layer, as the expansion between tungsten metal layer and polysilicon layer
Dissipate barrier layer；The grid protection layer 116 includes but is not limited to that silicon nitride layer is such as being subsequently formed for protecting gate structure
When the doping 14, diffusion ion accumulation scattering is unlikely to damage gate structure.
In addition, the present invention also provides the forming methods of another double exposure pattern, specific to make as shown in Figure 23~27
Preparation Method are as follows: the surface prior to semiconductor base 31 forms one layer of photoresist layer 32, then modifies the photoresist layer 32, so that
The width for obtaining photoresist layer can continue the photoresist layer 33 for reducing, being modified, wherein the size of the photoresist layer after modification is practical to be needed
It asks and sets, to finally obtain the double exposure pattern of required size, then, 33 periphery of photoresist layer after modification forms one
The continuous side wall 34 of layer, the side wall 34 is used to constitute final institute's double exposure pattern to be formed, then removes the more of side wall 34
Remaining part point, obtains structure as shown in figure 26, the two sides of each photoresist unit in the original photoresist layer 33 by modification
Forming respectively side wall, i.e. quantity is twice of photoresist element number in photoresist layer 33, modified photoresist layer 33 is finally removed,
Retain sidewall section, the side wall 36 with double exposure pattern has been obtained, to complete double exposure technique.
In conclusion the present invention provides a kind of multiple spacing exposing patterns and preparation method thereof, comprising steps of providing half
Conductor substrate, and in forming polysilicon layer on the semiconductor base, and the polysilicon layer includes several polysilicon units,
A gap is generated between the polysilicon unit；Ion doping is carried out for the side of the polysilicon unit, makes the polycrystalline
The side that silicon unit is revealed in the gap is formed as doping, and the polysilicon unit separately has adjacent to the doping
Portion and the intrinsic portion for not carrying out ion doping, wherein etching speed of the etch rate of the doping much smaller than the intrinsic portion
Rate；And the intrinsic portion is compared using specific etching selection and is performed etching, to remove the intrinsic portion and retain the doping
Portion.Through the above technical solutions, method for forming semiconductor structure provided by the invention, the existing exposure development of effective solution
The method and process of the limited problem of technology, the miniature semiconductor pattern structure of available line footpath, double exposure development is simple,
It is not influenced vulnerable to the external world, obtains the accurate size of pattern, it is easily controllable, and can be omitted excess stock layer removal (chopping)
Technique.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (20)
1. a kind of preparation method of multiple spacing exposing patterns, which comprises the steps of:
1) provide semiconductor substrate, and in forming polysilicon layer on the semiconductor base, and if the polysilicon layer include
A polysilicon unit is done, generates a gap between the polysilicon unit；
2) ion doping is carried out for the side of the polysilicon unit, the polysilicon unit is made to be revealed in the side in the gap
Portion is formed as doping, and the polysilicon unit separately has and do not carrying out adjacent to the doping and the intrinsic of ion doping
Portion, wherein the etch rate of the doping is much smaller than the etch rate in the intrinsic portion；And
3) it compares the intrinsic portion using specific etching selection to perform etching, to remove the intrinsic portion and retain the doping
Portion.
2. the preparation method of multiple spacing exposing patterns according to claim 1, which is characterized in that in step 1), formed
The step of polysilicon layer includes:
1-1) Yu Suoshu semiconductor substrate surface forms one layer of polysilicon material layer；
1-2) Yu Suoshu polycrystalline silicon material layer surface forms a layer photoresist layer, and the graphical photoresist layer；And
1-3) polysilicon material layer is performed etching using the patterned photoresist layer as exposure mask, includes several to be formed
The polysilicon layer of a polysilicon unit and remaining photoresist layer positioned at the polysilicon layer surface.
3. the preparation method of multiple spacing exposing patterns according to claim 2, which is characterized in that in step 2), in each
The side of the polysilicon unit carries out the step of ion doping and includes:
So that the semiconductor base is in first direction inclination, is exposure mask to the polysilicon using the remaining photoresist layer
Layer carries out first time ion implanting with first angle, to form the first injection region in the first side of each polysilicon unit；
It 2-2) rotates the semiconductor base to second direction to tilt, continues using the remaining photoresist layer to be exposure mask to described more
Crystal silicon layer carries out second of ion implanting with second angle, to be formed and described the in the second side of each polysilicon unit
The second opposite injection region of one injection region, wherein first injection region and second injection region constitute the doping,
Not ion implanted region constitutes the intrinsic portion in the polysilicon unit.
4. the preparation method of multiple spacing exposing patterns according to claim 3, which is characterized in that the first angle and
The depth-to-width ratio for the groove that the second angle is constituted according to the gap between the adjacent polysilicon unit is set, with control
Injection ion reaches the region injected, to form first injection region and second injection region.
5. the preparation method of multiple spacing exposing patterns according to claim 3, which is characterized in that each polysilicon list
Member is parallel and is equidistantly intervally arranged, and the differential seat angle of the first direction and the second direction is 180 °, the first angle
It is equal with the second angle.
6. the preparation method of multiple spacing exposing patterns according to claim 3, which is characterized in that step 2-1) in, institute
Stating first angle is 10 °~70 °, and the implantation dosage of the first time ion implanting is 5E+13 to 1E+15 atom/square centimeter,
Implantation Energy is 1~20KeV, and the width of first injection region is 3.3~66nm；Step 2-2) in, the second angle is
10 °~70 °, the implantation dosage of second of ion implanting is 5E+13 to 1E+15 atom/square centimeter, Implantation Energy 1
~20KeV, the width of second injection region are 3.3~66nm.
7. the preparation method of multiple spacing exposing patterns according to claim 2, which is characterized in that in step 2), in each
The two sides of the polysilicon unit carry out the step of ion doping and include:
2-1) using the remaining photoresist layer as exposure mask, and to the semiconductor substrate surface in a manner of rectilinear ion implanting
Corresponding region carries out ion implanting, in the formation edge doped region of the two sides of each polysilicon unit；
2-2) the obtained structure of step 2-1) is made annealing treatment, is diffused the edge doped region, to be formed
Doping is stated, and the region in each polysilicon unit without diffusion constitutes the intrinsic portion.
8. the preparation method of multiple spacing exposing patterns according to claim 7, which is characterized in that step 2-2) in, shape
The step of at the doping are as follows:
After 2-2-1) making annealing treatment to the structure that step 2-1) is obtained, the edge doped region diffuses to form diffusion region,
In, the diffusion region includes the first diffusion region of the doping to be formed and is located at first diffusion region both ends and vertical
In the second diffusion region of first diffusion region；
2-2-2) surface of the structure obtained by step 2-2-1) forms one layer of etching barrier layer, and the etching barrier layer exposes
Second diffusion region；
2-2-3) using the etching barrier layer as exposure mask, second diffusion region is removed using etching technics；And
The remaining etching barrier layer is removed, 2-2-4) to form the doping being intervally arranged, and the adjacent doping
The region without diffusion between portion constitutes the intrinsic portion.
9. the preparation method of multiple spacing exposing patterns according to claim 7, which is characterized in that step 2-1) in, institute
The implantation dosage for stating ion implanting is 3E+15 to 8E+16 atom/square centimeter, and Implantation Energy is 0.2~10KeV；Step 2-2)
In, the temperature of the annealing is 900~1200 DEG C, and width of the edge doped region after spreading is 3.3~66nm, institute
Stating length of the edge doped region after spreading is 1.5~3nm.
10. the preparation method of multiple spacing exposing patterns according to claim 1, which is characterized in that in step 2), in each
The two sides of the polysilicon unit carry out the step of ion doping and include:
2-1) make the semiconductor base be in first direction inclination, to the polysilicon layer with first angle carry out for the first time from
Son injection, to form the first injection region in the first side of each polysilicon unit；
The semiconductor base to second direction 2-2) is rotated to tilt, to the polysilicon layer with second angle carry out second from
Son injection, to form second injection region opposite with first injection region in the second side of each polysilicon unit, and
First injection region and second injection region collectively cover in the polysilicon unit without ion implanted regions
Top and lateral wall；And
The region by ion implanting at the top of each polysilicon unit 2-3) is removed by dry etch process until exposure
Not ion implanted region out, wherein remaining first injection region and remaining second injection region constitute institute
State doping, not ion implanted region constitutes the intrinsic portion in the polysilicon unit.
11. the preparation method of multiple spacing exposing patterns according to claim 10, which is characterized in that the first angle
And the depth-to-width ratio setting of the groove that is constituted according to the gap between the adjacent polysilicon unit of the second angle, with control
System injection ion reaches the region injected, to form first injection region and second injection region.
12. the preparation method of multiple spacing exposing patterns according to claim 10, which is characterized in that each polysilicon
Unit is equidistantly intervally arranged in parallel, and the differential seat angle of the first direction and the second direction is 180 °, the first angle
It is equal with the second angle.
13. the preparation method of multiple spacing exposing patterns according to claim 1, which is characterized in that described in step 1)
Semiconductor base includes the stacked gate architectures on substrate, and the stacked gate architectures include: positioned at the substrate surface
Grid oxic horizon；Positioned at the polysilicon layer of the gate oxidation layer surface；And the metal positioned at the polysilicon layer surface
Layer.
14. the preparation method of multiple spacing exposing patterns according to claim 13, which is characterized in that the polysilicon layer
One layer of diffusion barrier layer is also formed between the metal layer；The layer on surface of metal also forms one layer of grid protection layer.
15. the preparation method of multiple spacing exposing patterns, feature described according to claim 1~any one of 14 exist
In in step 3), specific etching selection ratio includes to the etch rate in the intrinsic portion using default etching liquid greater than described pre-
If etching liquid is to 15 times of the doping etch rate.
16. the preparation method of multiple spacing exposing patterns according to claim 15, which is characterized in that in step 3), institute
Stating default etching liquid is alkaline etch solution, and the Doped ions in the ion doping technique are selected from boron, arsenic, phosphorus and boron fluoride
Any one in the group constituted.
17. a kind of multiple spacing exposing patterns characterized by comprising
Semiconductor substrate；And
Polysilicon layer is formed on the semiconductor base, and the polysilicon layer includes several polysilicon units, described more
Between crystal silicon unit generate one first gap, the polysilicon unit have be revealed in first gap doping and
The intrinsic portion of ion doping is not carried out adjacent to the doping and, wherein the etch rate of the doping is much smaller than described
The etch rate in intrinsic portion；
Wherein, when performing etching removal using the specific etching selection comparison intrinsic portion, the doping retains, same polycrystalline
One second gap is generated between the doping of silicon unit.
18. multiple spacing exposing patterns according to claim 17, which is characterized in that the Doped ions of the doping select
From any one in the group that boron, arsenic, phosphorus and boron fluoride are constituted.
19. multiple spacing exposing patterns according to claim 17, which is characterized in that the semiconductor base includes being located at
Stacked gate architectures on substrate, the stacked gate architectures include: the grid oxic horizon positioned at the substrate surface；Positioned at institute
State the polysilicon layer of gate oxidation layer surface；And the metal layer positioned at the polysilicon layer surface.
20. multiple spacing exposing patterns according to claim 19, which is characterized in that the polysilicon layer and the metal
One layer of diffusion barrier layer is also formed between layer；The layer on surface of metal also forms one layer of grid protection layer.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110610851A (en) * | 2019-09-20 | 2019-12-24 | 长江存储科技有限责任公司 | Method for protecting wafer edge in TMAH process |
| CN112928209A (en) * | 2021-01-22 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Preparation method of polysilicon resistor |
| CN113495430A (en) * | 2020-04-07 | 2021-10-12 | 芯恩（青岛）集成电路有限公司 | Photoresist patterning method and photoresist stripping method |
| CN115332069A (en) * | 2022-10-14 | 2022-11-11 | 广州粤芯半导体技术有限公司 | Method for etching polycrystalline silicon by dry method and preparation method of semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04196423A (en) * | 1990-11-28 | 1992-07-16 | Seiko Epson Corp | Manufacture of semiconductor device |
| US20090233448A1 (en) * | 2008-03-11 | 2009-09-17 | Nanya Technology Corp. | Lithography resolution improving method |
| CN103681293A (en) * | 2012-09-10 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Self-alignment duplex patterning method |
| CN106887382A (en) * | 2011-10-20 | 2017-06-23 | 台湾积体电路制造股份有限公司 | The method for forming integrated circuit |
-
2017
- 2017-10-31 CN CN201711049885.4A patent/CN109727851B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04196423A (en) * | 1990-11-28 | 1992-07-16 | Seiko Epson Corp | Manufacture of semiconductor device |
| US20090233448A1 (en) * | 2008-03-11 | 2009-09-17 | Nanya Technology Corp. | Lithography resolution improving method |
| CN106887382A (en) * | 2011-10-20 | 2017-06-23 | 台湾积体电路制造股份有限公司 | The method for forming integrated circuit |
| CN103681293A (en) * | 2012-09-10 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Self-alignment duplex patterning method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110610851A (en) * | 2019-09-20 | 2019-12-24 | 长江存储科技有限责任公司 | Method for protecting wafer edge in TMAH process |
| CN113495430A (en) * | 2020-04-07 | 2021-10-12 | 芯恩（青岛）集成电路有限公司 | Photoresist patterning method and photoresist stripping method |
| CN113495430B (en) * | 2020-04-07 | 2023-09-26 | 芯恩（青岛）集成电路有限公司 | Photoresist patterning method and photoresist stripping method |
| CN112928209A (en) * | 2021-01-22 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Preparation method of polysilicon resistor |
| CN115332069A (en) * | 2022-10-14 | 2022-11-11 | 广州粤芯半导体技术有限公司 | Method for etching polycrystalline silicon by dry method and preparation method of semiconductor structure |
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