CN111370309B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN111370309B CN111370309B CN201811605461.6A CN201811605461A CN111370309B CN 111370309 B CN111370309 B CN 111370309B CN 201811605461 A CN201811605461 A CN 201811605461A CN 111370309 B CN111370309 B CN 111370309B
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- 239000010703 silicon Substances 0.000 claims description 27
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- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 claims description 7
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate; forming a plurality of discrete first mask patterns on a substrate; forming a sacrificial side wall on the side wall of the first mask pattern; forming a second mask pattern on the side wall of the sacrificial side wall; the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern on the same first mask pattern side wall form pattern units, and the interval between the second mask patterns in adjacent pattern units is an integer multiple of the width of the first mask pattern; removing the sacrificial side wall; and etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a plurality of discrete fin parts. And etching the substrate by taking the first mask pattern and the second mask pattern as masks, and adjusting the spacing between the fin parts formed subsequently by changing the spacing between the corresponding adjacent pattern units on the substrate, thereby further improving the performance of the semiconductor structure.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous improvement of the integration level of integrated circuits, the integrated circuits are rapidly developed to submicron and deep submicron directions, and the line width of patterns is also finer, which puts higher demands on the semiconductor process. Therefore, intensive research on how to realize a fine line width pattern to accommodate new requirements of a semiconductor process has become an unprecedented topic.
Photolithography (Lithograph) is a key process technology for implementing integrated circuit patterns. In the photolithography technique, a photosensitive material (photoresist) is coated on a film of a substrate, light of a wavelength band corresponding to the photosensitive characteristic of the photoresist is irradiated to the surface of the photoresist through a mask plate with a specific pattern, and a photoresist pattern corresponding to the pattern on the mask plate is formed after development. In the subsequent process of the integrated circuit, the photoresist pattern is used as a barrier layer to selectively etch the film below the photoresist pattern, so that the pattern on the mask plate can be completely transferred to the film on the substrate. The finer the line width of the pattern of the integrated circuit, the higher the imaging resolution of the photoresist is required, and the imaging resolution of the photoresist is inversely proportional to the wavelength of the exposure light source, so that reducing the wavelength of the exposure light source becomes a main way to realize a fine line width pattern.
Double patterning is a technique developed in semiconductor fabrication for photolithography to enhance feature density. In commonly implemented photolithography, a photoresist is applied to a surface of a semiconductor wafer, and then a pattern is defined in the photoresist. The pattern in the patterned photoresist is defined in the photolithographic mask. Self-aligned double patterning (SADP) is a semiconductor process designed to reduce the number of photolithography steps required to develop a monolayer. SADP employs forming hard mask spacers to create other patterns not formed in the photolithographic mask. The pattern created by the spacers is etched and filled to create other patterns in the semiconductor substrate without using an additional photolithographic mask.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of discrete first mask patterns on the substrate; forming a sacrificial side wall on the side wall of the first mask pattern; forming a second mask pattern on the side wall of the sacrificial side wall; the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern on the same side wall of the first mask pattern form pattern units, and the interval between the second mask patterns in adjacent pattern units is an integer multiple of the width of the first mask pattern; removing the sacrificial side wall; and etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a plurality of discrete fin parts.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a plurality of first mask patterns, which are separated on the substrate, wherein the first mask patterns are used for forming fin parts; the sacrificial side wall is positioned on the side wall of the first mask pattern; the second mask pattern is positioned on the side wall of the sacrificial side wall and is used for forming fin parts; the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern on the same side wall of the first mask pattern form pattern units, and the distance between the second mask patterns in adjacent pattern units is an integer multiple of the width of the first mask pattern.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, a plurality of discrete first mask patterns are formed on the substrate; forming a sacrificial side wall on the side wall of the first mask pattern; and forming a second mask pattern on the side wall of the sacrificial side wall. The first mask pattern and the second mask pattern are arranged at intervals through the sacrificial side wall, and in general, the etched rate of the sacrificial side wall is larger than that of the first mask pattern and the second mask pattern, even in a technical node with a tiny size, in the process of removing the sacrificial side wall, the damage of the first mask pattern and the second mask pattern is still less, the shape quality of a fin portion formed by etching the substrate by taking the first mask pattern and the second mask pattern as masks is still better, and further, the electrical performance of a semiconductor structure can be optimized. Because the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern on the same side wall of the first mask pattern form a pattern unit, and the interval between the second mask patterns in adjacent pattern units is an integer multiple of the width of the first mask pattern; therefore, the first mask pattern and the second mask pattern are used as masks for etching the substrate, the distance between the formed fin parts is a multiple of the width of the fin parts, and the distance between the fin parts formed subsequently can be adjusted by changing the distance between the corresponding adjacent pattern units on the substrate so as to meet the design requirements of different semiconductor structures, and further improve the performance of the semiconductor structures.
In an alternative, the second mask pattern in the partial pattern unit includes: a device second mask pattern for forming a Fin portion, and a dummy second mask pattern corresponding to a Fin cut (Fin cut) position; after forming a second mask pattern, before removing the sacrificial side wall, forming a first shielding layer exposing the pseudo second mask pattern, wherein in the process of carrying out ion doping on the pseudo second mask pattern by taking the first shielding layer as a mask, the structure covered by the first shielding layer is not easy to be doped; and the etching selection ratio of the pseudo second mask pattern after being ion doped to the second mask pattern of the device is increased, so that other structures in the pattern unit are not easily damaged in the process of removing the ion doped pseudo second mask pattern, and the electrical performance of the semiconductor structure is improved.
In an alternative, the first mask pattern includes: a device first mask pattern for forming a fin portion, and a dummy first mask pattern corresponding to a fin cut position; after forming a second mask pattern, forming a second shielding layer exposing the pseudo first mask pattern before removing the sacrificial side wall; therefore, the second shielding layer is used as a mask, and the structure covered by the second shielding layer is not easily damaged in the process of removing the pseudo first mask pattern, so that the electrical performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 8 to 18 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention;
fig. 19 to 21 are schematic structural views corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;
FIG. 22 is a schematic diagram of an embodiment of a semiconductor structure according to an embodiment of the present invention;
FIG. 23 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention;
fig. 24 is a schematic view of a semiconductor structure according to another embodiment of the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
As shown in fig. 1, a plurality of discrete core layers 2 are formed on a substrate 1, and a first pattern material layer (not shown in the figure) is conformally covered on the core layers 2 and the substrate 1 where the core layers 2 are exposed; the first pattern material layer on the core layer 2 and on the substrate 1 is removed, forming a first pattern layer 3 on the side wall of the core layer 2.
As shown in fig. 2, the core layer 2 is removed in preparation for subsequent formation of a second pattern layer on the sidewalls of the first pattern layer 3.
As shown in fig. 3, a second pattern material layer (not shown in the figure) is conformally covered on the first pattern layer 3 and the substrate 1 where the first pattern layer 3 is exposed; and removing the second pattern material layer on the first pattern layer 3 and the substrate 1 to form a second pattern layer 4 positioned on the side wall of the first pattern layer 3.
As shown in fig. 4, the first pattern layer 3 is removed in preparation for the subsequent formation of a third pattern layer on the sidewalls of the second pattern layer 4.
As shown in fig. 5, a third pattern material layer (not shown in the figure) is conformally covered on the second pattern layer 4 and the substrate 1 where the second pattern layer 4 is exposed; and removing the third pattern material layer on the second pattern layer 4 and the substrate 1 to form a third pattern layer 5 positioned on the side wall of the second pattern layer 4, wherein the third pattern layer 5 comprises a pseudo third pattern layer 7 and a device third pattern layer 6.
As shown in fig. 6, the second graphics layer 4 is removed.
As shown in fig. 7, the dummy third pattern layer 7 in the third pattern layer 5 is removed.
As the integrated circuit integration level is continuously improved, the line width and the pitch of the patterns in the integrated circuit are also smaller and smaller, because the resolution capability of the current lithography machine is insufficient, when the dummy third pattern layer 7 is removed, the third pattern layer 6 of the device adjacent to the dummy third pattern layer 7 is easily damaged (as shown in a and B in the figure), and after the substrate 1 is etched by the damaged third pattern 6 of the device, the formed fin portion has structural defects, so that the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, the embodiment of the invention forms a plurality of discrete first mask patterns on the substrate; forming a sacrificial side wall on the side wall of the first mask pattern; and forming a second mask pattern on the side wall of the sacrificial side wall. The first mask pattern and the second mask pattern are arranged at intervals through the sacrificial side wall, the etched rate of the sacrificial side wall is generally larger than that of the first mask pattern and the second mask pattern, the first mask pattern and the second mask pattern are less damaged in the process of removing the sacrificial side wall, and the fin portion morphology quality formed by taking the first mask pattern and the second mask pattern as masks for etching the substrate is better even in a technical node with a tiny size, so that the electrical performance of the semiconductor structure can be optimized. Because the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal; the first mask patterns, the sacrificial side walls and the second mask patterns which are positioned on the same side wall of the first mask patterns form pattern units, and the distance between the second mask patterns positioned in adjacent pattern units is an integer multiple of the width of the first mask patterns; therefore, the first mask pattern and the second mask pattern are used as masks for etching the substrate, the distance between the formed fin portions is a multiple of the width of the fin portions, and the distance between the fin portions formed subsequently can be adjusted by changing the distance between corresponding adjacent pattern units on the substrate so as to meet the design requirements of different semiconductor structures, and further the performance of the semiconductor structures is improved.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 8 to 18 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.
Referring to fig. 8, a substrate 100 is provided. The substrate 100 is used to provide a process platform for the subsequent formation of fins.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In the step of providing the substrate 100, further comprising forming an etch resist layer 101 on said substrate 100. The etch-resistant layer 101 protects the substrate 100 from etching during subsequent formation of the first mask pattern and the second mask pattern on the substrate 100.
In this embodiment, the material of the anti-etching layer 101 is silicon nitride. In other embodiments, the material of the anti-etching layer may be one or more of silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Referring to fig. 9 to 11, a plurality of discrete first mask patterns 102 (shown in fig. 11) are formed on the substrate 100. The first mask pattern 102 provides for the subsequent formation of a second mask pattern.
The step of forming a plurality of discrete first mask patterns 102 on the substrate 100 includes: forming a core material layer 103 on the substrate 100, a core mask material layer (not shown) on the core material layer 103, and a photoresist layer 104 on the core mask material layer; etching the core mask material layer by using the photoresist layer 104 as a mask to form a first core mask layer 105 (as shown in fig. 9); etching a portion of the sidewall of the first core mask layer 105 to form a second core mask layer 106 (as shown in fig. 10); and etching the core material layer 103 by taking the second core mask layer 106 as a mask to form a first mask pattern 102.
The material of the first mask pattern 102 includes one or more of titanium nitride, silicon nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound. In this embodiment, the material of the first mask pattern 102 is silicon nitride.
In this embodiment, the pitch between adjacent first mask patterns 102 is five widths of the first mask patterns 102. In other embodiments, the pitch of the first mask patterns 102 may also be an integer multiple greater than five.
In this embodiment, the width of the first mask pattern 102 is 7nm to 8nm. Accordingly, a minimum pitch (pitch) D adjacent to the first mask pattern 102 is 42 nm to 48 nm.
In this embodiment, as shown in fig. 11, the first mask pattern 102 includes a device first mask pattern 1022 for forming a fin portion, and a dummy first mask pattern 1021 corresponding to a fin cut (fin cut) position.
With continued reference to fig. 9 and 10, a wet etching process is used to etch a portion of the sidewall of the first core mask layer 105, forming a second core mask layer 106.
And removing part of the side wall of the first core mask layer 105 by etching, so that the width of the second core mask layer 106 is smaller than that of the first core mask layer 105, and preparing the second core mask layer 106 for subsequent etching of the core material layer 103 to form the first core mask layer 105.
In the existing photolithography process, the first core mask layer 105 with a wider width is formed first, the difficulty of the forming process is small, and then the second core mask layer 106 with a narrower width is easily formed by removing part of the side wall of the first core mask layer 105 through etching.
Specifically, the material of the first core mask layer 105 is silicon nitride, and correspondingly, the etching solution is a phosphoric acid solution.
Referring to fig. 12, sacrificial spacers 107 are formed on sidewalls of the first mask pattern 102. A second mask pattern is then formed on the sidewalls of the sacrificial sidewall 107, where the sacrificial sidewall 107 is used to define a space between the second mask pattern and the first mask pattern 102.
The step of forming the sacrificial sidewall 107 includes: a sacrificial spacer material layer (not shown) is formed on the sacrificial spacer 107 and the substrate 100 exposed by the sacrificial spacer 107, and the sacrificial spacer material layer on the first mask pattern 102 and the substrate 100 is removed, so as to form the sacrificial spacer 107 on the sidewall of the first mask pattern 102.
In this embodiment, the material of the sacrificial sidewall 107 is amorphous carbon, amorphous germanium or amorphous silicon.
In this embodiment, the width of the sacrificial sidewall 107 is 7nm to 8nm.
In this embodiment, the sacrificial material layer is formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD) or an atomic layer deposition process (Atomic Layer Deposition, ALD). The chemical vapor deposition and the atomic layer deposition have good conformal coverage capability, and the formed sacrificial side wall material layers have good thickness uniformity.
Referring to fig. 13, a second mask pattern 108 is formed on the sidewall of the sacrificial sidewall 107; the widths of the first mask pattern 102, the sacrificial sidewall 107 and the second mask pattern 108 are equal, the first mask pattern 102, the sacrificial sidewall 107 and the second mask pattern 108 on the same sidewall of the first mask pattern 102 form a pattern unit, and the space between the second mask patterns 108 in adjacent pattern units is an integer multiple of the width of the first mask pattern 102.
The first mask pattern 102 and the second mask pattern 108 provide for the subsequent formation of fins.
In the embodiment of the invention, a plurality of discrete first mask patterns 102 are formed on the substrate; forming a sacrificial sidewall 107 on the sidewall of the first mask pattern 102; a second mask pattern 108 is formed on the sidewalls of the sacrificial sidewall 107. The first mask pattern 102 and the second mask pattern 108 are arranged at intervals through the sacrificial side wall 107, and in general, the etched rate of the sacrificial side wall 107 is greater than the etched rate of the first mask pattern 102 and the second mask pattern 108, even in a technical node with a tiny size, the damage of the first mask pattern 102 and the second mask pattern 108 is still less in the subsequent process of removing the sacrificial side wall 107, and the shape quality of a fin portion formed by etching the substrate by taking the first mask pattern 102 and the second mask pattern 108 as masks is still better, so that the electrical performance of the semiconductor structure can be optimized. Because the widths of the first mask pattern 102, the sacrificial sidewall 107 and the second mask pattern 108 are equal, the first mask pattern 102 and the sacrificial sidewall 107 and the second mask pattern 108 on the same sidewall of the first mask pattern 102 form a pattern unit, and the space between the second mask patterns 108 in adjacent pattern units is an integer multiple of the width of the first mask pattern 102; therefore, the substrate 100 is etched by using the first mask pattern 102 and the second mask pattern 108 as masks, the pitches between the adjacent fin portions are multiple of the widths of the fin portions, and the pitches between the fin portions formed subsequently can be adjusted by changing the pitches between the corresponding adjacent pattern units on the substrate 100, so as to meet the design requirements of different semiconductor structures, and further improve the performance of the semiconductor structures.
In this embodiment, the distance d between the second mask patterns 108 in the adjacent pattern units is the width of one first mask pattern 102, that is, the distance between the adjacent pattern units is the width of one first mask pattern 102. In other embodiments, the pitch of the second mask pattern 108 in adjacent pattern units may also be a multiple of more than one width of the first mask pattern 102.
In this embodiment, the step of forming the second mask pattern 108 includes: a second mask pattern material layer (not shown) is formed on the first mask pattern 102 and the sacrificial sidewall 107 and on the substrate 100 where the first mask pattern 102 and the sacrificial sidewall 107 are exposed, and the second mask pattern material layer on the first mask pattern 102, the sacrificial sidewall 107 and the substrate 100 is removed to form a second mask pattern 108 on the sidewall of the sacrificial sidewall 107.
The material of the second mask pattern 108 includes one or more of silicon, titanium nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound, and the material of the second mask pattern 108 is different from the material of the first mask pattern 102. In this embodiment, the material of the second mask pattern 108 is silicon.
It should be noted that the etched rate of the first mask pattern 102 is greater than the etched rate of the second mask pattern 108, so as to prepare for the subsequent wet removal of the first mask pattern 102.
In this embodiment, the second mask pattern material layer is formed by using a chemical vapor deposition process or an atomic layer deposition process. The chemical vapor deposition and the atomic layer deposition have good conformal coverage capability, and the formed second mask material layers have good thickness uniformity.
In this embodiment, the width of the second mask pattern 108 is 7nm to 8nm.
In this embodiment, the second mask pattern 108 in a part of the pattern units includes: a device second mask pattern 1082 for forming the fin, and a dummy second mask pattern 1081 corresponding to the fin cut position.
The subsequent step further includes etching the dummy second mask pattern 1081 to avoid fin formation at the location.
Therefore, referring to fig. 14, after forming the second mask pattern 108, before removing the sacrificial sidewall 107, the method further includes: forming a first shielding layer 109 exposing the dummy second mask pattern 1081; ion doping is performed on the pseudo second mask pattern 1081 by using the first shielding layer 109 as a mask, so that the etching selection ratio of the doped pseudo second mask pattern 1081 to the device second mask pattern 1082 is increased; the ion doped dummy second mask pattern 1081 is removed.
In the process of performing ion doping on the pseudo second mask pattern 1081 by using the first shielding layer 109 as a mask, the first mask pattern 102 covered by the first shielding layer 109 and the device second mask pattern 1082 are not easy to be doped; the structure covered by the shielding layer 109 is not easily damaged in the process of removing the ion doped dummy second mask pattern 1081, which is beneficial to improving the electrical performance of the semiconductor structure.
After the dummy second mask pattern 1081 is ion-doped, the dummy second mask pattern 1081 is etched at a rate greater than that of the device second mask pattern 1082, so that the dummy second mask pattern 1081 is more easily removed than before doping.
In this embodiment, the step of forming the first shielding layer 109 includes: forming a layer of masking material (not shown) overlying the pattern elements and a photoresist layer over the layer of masking material; the masking material layer is etched using the photoresist layer as a mask to form a first masking layer 109.
It should be noted that, in this embodiment, since the etched rate of the dummy second mask pattern 1081 is greater than the etched rate of the device second mask pattern 1082, the damage to the device second mask pattern 1082 in the process of removing the dummy second mask pattern 1081 is smaller, and therefore, the first shielding layer 109 exposes not only the dummy second mask pattern 1081 but also the device second mask pattern 1082 close to the dummy second mask pattern 1081 in the adjacent pattern unit, thereby increasing the process window for forming the first shielding layer 109 and reducing the process difficulty for forming the first shielding layer 109. In other embodiments, the first blocking layer may only expose the dummy second mask pattern.
In this embodiment, the material of the first shielding layer 109 is an organic material, which is easy to be removed in the subsequent process, and is not easy to have residues. Specifically, the material of the first shielding layer 109 is BARC (bottom anti-reflective coating) material. In other embodiments, the material of the first shielding layer may be an ODL (organic dielectric layer ) material, a photoresist, a DARC (dielectric anti-reflective coating) material, a DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide) material, or an APF (Advanced Patterning Film ) material.
In this embodiment, ions are doped in the dummy second mask pattern 1081 by ion implantation. The dummy second mask pattern 1081 doped with ions has an etching rate greater than that of the device second mask pattern 1082.
Specifically, the doping ions are germanium ions. In this embodiment, the material of the dummy second mask pattern 1081 is silicon, and after the corresponding germanium ions are implanted, the material of the dummy second mask pattern 1081 is silicon germanium, and the material of the device second mask pattern 1082 is silicon, and the etching selectivity of silicon germanium and silicon is relatively large, so that when the dummy second mask pattern 1081 is removed, the etched rate of the dummy second mask pattern 1081 is greater than the etched rate of the device second mask pattern 1082. In other embodiments, the doping ions may be oxygen ions, and the material of the dummy second mask pattern is silicon, and after the oxygen ions are implanted correspondingly, the material of the dummy second mask pattern 1081 is changed into silicon oxide, so that when the dummy second mask pattern is removed, the etched rate of the dummy second mask pattern is greater than the etched rate of the device second mask pattern 1082.
The doping ion implantation dose should not be too large or too small. If the doping ion implantation dosage is too large, too much process time is spent, and the production efficiency is low; if the doping ion implantation dose is too small, it is not beneficial to increase the etching selection ratio of the dummy second mask pattern 1081 of the doping ion to the second mask pattern 1082 of the device, and is not beneficial to removing the dummy second mask pattern 1081 subsequently. In this example, the implant dose is 1.0E14 atoms per square centimeter to 5.0E15 atoms per square centimeter.
The implantation energy of the dopant ions should not be too large or too small. If the doping ion implantation energy is too large, the doping ions are easy to enter the sacrificial sidewall 107 through the dummy second mask pattern 1081, which is not beneficial to increasing the etching selection ratio of the dummy second mask pattern 1081 to the device second mask pattern 1082, and is not beneficial to removing the dummy second mask pattern 1081 by subsequent etching, and the doping ions also enter the substrate 100 to cause pollution; if the doping ion implantation energy is too small, the doping ions are easy to stay on the surface of the dummy second mask pattern 1081, which is not beneficial to increasing the etching selection ratio of the entire dummy second mask pattern 1081 to the device second mask pattern 1082, and is not beneficial to removing the dummy second mask pattern 1081 subsequently. In this embodiment, the implantation energy is 1Kev to 10Kev.
It should be noted that the angle between the direction of the ion implantation and the normal to the surface of the substrate 100 should not be too large or too small. If the included angle between the direction of ion implantation and the normal line is too large, ions are not easy to be implanted into the bottom of the pseudo second mask pattern 1081, and the implanted ions easily enter the sacrificial side wall 107 and the first mask pattern 102, so that the subsequent etching is not easy to remove the pseudo second mask pattern 1081; if the included angle between the direction of ion implantation and the normal line of the surface of the substrate 100 is too small, the implanted ions are easily concentrated on the top of the dummy second mask pattern 1081 and in the sacrificial sidewall 107, so that the implanted ions at the bottom of the dummy second mask pattern 1081 are too small, which is not beneficial to removing the dummy second mask pattern 1081 in the subsequent etching. In this embodiment, the angle between the direction of ion implantation and the normal to the surface of the substrate 100 is 10 degrees to 40 degrees.
In this embodiment, after ion doping, a wet etching process is used to remove the dummy second mask pattern 1081. Specifically, the material of the pseudo second mask pattern 1081 after being doped with ions is silicon, and correspondingly, the etching solution adopted in the wet etching process is a tetramethylammonium hydroxide solution. In other embodiments, the material of the dummy second mask pattern is silicon, the doped ions are oxygen ions, and correspondingly, the etching solution adopted in the wet etching process is a hydrofluoric acid solution.
Note that, in this embodiment, the dummy second mask pattern 1081 corresponds to a fin cut region, and the dummy second mask pattern 1081 is located on the right side in the partial pattern unit. In other embodiments, the dummy second mask pattern may also be located on the left side in the partial graphic unit, and the corresponding method steps for removing the dummy second mask pattern are the same, which is not described herein.
Referring to fig. 15, the method for forming the semiconductor structure further includes: after the dummy second mask pattern 1081 is removed, the first shielding layer 109 is removed. The removal of the first masking layer 109 provides for the subsequent formation of a second masking layer exposing the dummy first mask pattern 1021.
In this embodiment, the material of the first shielding layer 109 is BARC material, and ashing is used to remove the first shielding layer 109. In other embodiments, a dry etching process may also be used to remove the first shielding layer.
Referring to fig. 16, the method for forming the semiconductor structure includes: after forming the second mask pattern 108, forming a second shielding layer 110 exposing the dummy first mask pattern 1021 (as shown in fig. 15) before removing the sacrificial sidewall 107; and removing the pseudo first mask pattern 1021 by taking the second shielding layer 110 as a mask.
The second shielding layer 110 is used as a mask, so that the first mask pattern 1022 and the second mask pattern 108 of the device covered by the second shielding layer 110 are not easily damaged in the process of removing the pseudo first mask pattern 1021, which is beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, the step of forming the second shielding layer 110 includes: forming a layer of masking material (not shown) overlying the pattern elements and a photoresist layer over the layer of masking material; and etching the shielding material layer by taking the photoresist layer as a mask to form a second shielding layer 110.
It should be noted that, in this embodiment, since the etched rate of the first mask pattern 102 is greater than the etched rate of the second mask pattern 108, that is, the etched rate of the dummy first mask pattern 1021 is greater than the etched rate of the second mask pattern 108, the second shielding layer 110 exposes not only the dummy first mask pattern 1021 but also the second mask pattern 108 and the sacrificial sidewall 107 of the device in the pattern unit where the dummy first mask pattern 1021 is located, thereby increasing the process window for forming the second shielding layer 110, and being applicable in the process of the smaller process node. In other embodiments, the first blocking layer may only expose the dummy first mask pattern.
In this embodiment, a wet etching process is used to remove the dummy first mask pattern 1021.
Specifically, in this embodiment, the material of the dummy first mask pattern 1021 is silicon nitride, and correspondingly, the etching solution used in the wet etching process is phosphoric acid solution.
After removing the dummy first mask pattern 1021, the second shielding layer 110 is removed (as shown in fig. 16).
In this embodiment, the second shielding layer 110 is removed by ashing. In other embodiments, a dry etching process may also be used to remove the second shielding layer.
Referring to fig. 17, the sacrificial sidewall 107 is removed (as shown in fig. 16). And removing the sacrificial side wall 107 to prepare for the subsequent etching of the substrate 100 by taking the first mask pattern 1021 and the second mask pattern 1082 of the device as masks to form fin portions.
In this embodiment, a wet etching process is used to remove the sacrificial sidewall 107, where the etched rate of the sacrificial sidewall 107 is greater than the etched rate of the first mask pattern 102 and the second mask pattern 108. In other embodiments, a dry etching process may be used to remove the sacrificial sidewall.
Specifically, in this embodiment, a tetramethylammonium hydroxide solution is used to remove the sacrificial sidewall 107.
Referring to fig. 18, the substrate 100 is etched using the first mask pattern 102 and the second mask pattern 108 as masks (as shown in fig. 17), and a plurality of discrete fins 111 are formed.
In this embodiment, in the process of forming the fin 111, the first mask pattern 102 is a device first mask pattern 1022, and the second mask pattern 108 is a device second mask pattern 1082.
In this embodiment, a dry etching process is used to etch the substrate 100 to form a plurality of discrete fins 111. In other embodiments, the substrate may also be etched using a combination of dry and wet processes to form a plurality of discrete fins.
In this embodiment, the dummy second mask pattern 1081 (as shown in fig. 14) is removed first, and then the dummy first mask pattern 1021 (as shown in fig. 14) is removed. In other embodiments, the dummy first mask pattern 1021 may be removed first, and then the dummy second mask pattern 1081 may be removed.
Fig. 19 to 21 are schematic structural views corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to the present invention.
The present embodiment is the same as that of the first embodiment, and will not be described in detail herein. This embodiment differs from one embodiment in that: and forming the first mask pattern.
Referring to fig. 19, a core layer 202 is formed on a substrate 200. The substrate 200 is used to provide a process platform for the subsequent formation of fins.
In the step of providing the substrate 200, further comprising forming an etch resist layer 201 on said substrate 200.
For a specific description of the substrate 200 and the etching resist layer 201, reference may be made to the corresponding description in the first embodiment, and a detailed description is omitted herein.
Referring to fig. 20, a first mask pattern 203 is formed on a sidewall of the core layer 202. The first mask pattern 203 provides for the subsequent formation of a second mask pattern.
The step of forming the first mask pattern 203 includes: conformally covering the first mask pattern material layer on the core layer 202 and the substrate 200 where the core layer 202 is exposed; the core layer 202 and the first mask pattern material layer on the substrate 200 are removed, and a first mask pattern 203 is formed on the sidewall of the core layer 202.
The material of the first mask pattern 203 includes one or more of titanium nitride, silicon nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound. In this embodiment, the material of the first mask pattern 203 is silicon nitride.
In this embodiment, a minimum distance (pitch) D between adjacent first mask patterns 203 is 42 nm to 48 nm.
In this embodiment, the pitch between adjacent first mask patterns 203 is five widths of the first mask patterns 203. In other embodiments, the pitch of the first mask patterns 203 may also be an integer multiple greater than five.
Accordingly, in this embodiment, the width of the first mask pattern 203 is 7nm to 8nm.
Referring to fig. 21, after the first mask pattern 203 is formed, the core layer 202 (shown in fig. 20) is removed.
In this embodiment, the method for forming the first mask pattern 203 and the subsequent second mask pattern and the corresponding effects are the same as those of the first embodiment, and the description of this embodiment is omitted.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. With continued reference to fig. 13, a schematic structural diagram of a first embodiment of the semiconductor structure of the present invention is shown.
As shown in fig. 13, the semiconductor structure includes: a substrate 100; a plurality of first mask patterns 102, which are separated on the substrate 100, wherein the first mask patterns 102 are used for forming fin portions; sacrificial sidewall 107 located on a sidewall of the first mask pattern 102; a second mask pattern 108 located on a sidewall of the sacrificial sidewall 107, where the second mask pattern 108 is used to form a fin portion; the widths of the first mask pattern 102, the sacrificial sidewall 107 and the second mask pattern 108 are equal, the first mask pattern 102, the sacrificial sidewall 107 and the second mask pattern 108 on the same sidewall of the first mask pattern 102 form a pattern unit, and the distance d between the second mask patterns 108 in adjacent pattern units is an integer multiple of the width of the first mask pattern 102.
In the embodiment of the invention, a plurality of discrete first mask patterns 102 are formed on the substrate; forming a sacrificial sidewall 107 on the sidewall of the first mask pattern 102; a second mask pattern 108 is formed on the sidewalls of the sacrificial sidewall 107. The first mask pattern 102 and the second mask pattern 108 are arranged at intervals through the sacrificial side wall 107, and in general, the etched rate of the sacrificial side wall 107 is greater than the etched rate of the first mask pattern 102 and the second mask pattern 108, even in a technical node with a tiny size, the damage to the first mask pattern 102 and the second mask pattern 108 is still less in the subsequent process of removing the sacrificial side wall 107, and the shape and quality of a fin portion formed by etching the substrate by taking the first mask pattern 102 and the second mask pattern 108 as masks are still better, so that the electrical performance of the semiconductor structure can be optimized.
Because the widths of the first mask pattern 102, the sacrificial sidewall 107 and the second mask pattern 108 are equal, the first mask pattern 102 and the sacrificial sidewall 107 and the second mask pattern 108 on the same sidewall of the first mask pattern 102 form a pattern unit, and the distance d between the second mask patterns 108 in adjacent pattern units is an integer multiple of the width of the first mask pattern 102; therefore, the substrate 100 is etched by using the first mask pattern 102 and the second mask pattern 108 as masks, the pitches between the adjacent fin portions are multiple of the widths of the fin portions, and the pitches between the fin portions formed subsequently can be adjusted by changing the pitches between the corresponding adjacent pattern units on the substrate 100, so as to meet the design requirements of different semiconductor structures, and further improve the performance of the semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the semiconductor structure further includes: an etch-resistant layer 101, the etch-resistant layer 101 being located on the substrate 100. Accordingly, a first mask pattern 102, a sacrificial sidewall 107, and a second mask pattern 108 are located on the etch-resistant layer 101.
In this embodiment, the material of the anti-etching layer 101 is silicon nitride. In other embodiments, the material of the anti-etching layer may be one or more of silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The material of the first mask pattern 102 includes one or more of titanium nitride, silicon nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound. In this embodiment, the material of the first mask pattern 102 is silicon nitride.
In this embodiment, the width of the first mask pattern 102 is 7nm to 8nm.
In this embodiment, the pitch between adjacent first mask patterns 102 is five widths of the first mask patterns 102. In other embodiments, the pitch of the first mask patterns 102 may also be an integer multiple greater than five.
Accordingly, the minimum distance D between adjacent first mask patterns 102 is 42 nm to 48 nm.
The sacrificial sidewall 107 is used to ensure a space between the second mask pattern 108 and the first mask pattern 102.
In this embodiment, the material of the sacrificial sidewall 107 is amorphous carbon, amorphous germanium or amorphous silicon.
In this embodiment, the width of the sacrificial sidewall 107 is 7nm to 8nm.
In this embodiment, the etched rate of the first mask pattern 102 is greater than the etched rate of the second mask pattern 108.
The material of the second mask pattern 108 includes one or more of silicon, titanium nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound, and the material of the second mask pattern 108 is different from the material of the first mask pattern 102. In this embodiment, the material of the second mask pattern 108 is silicon.
In this embodiment, the width of the second mask pattern 108 is 7nm to 8nm.
Referring to fig. 22, a schematic structural diagram of a second embodiment of the semiconductor structure of the present invention is shown. The present embodiment is the same as the first embodiment, and will not be described again. The present embodiment is different from the first embodiment in that:
the second mask pattern 308 in the semiconductor structure includes: a device second mask pattern 3082 for forming a fin portion, and a dummy second mask pattern 3081 corresponding to a fin cut position; and doped ions are located in the dummy second mask pattern 3081 to increase the etching selectivity of the doped dummy second mask pattern 3081 to the device second mask pattern 3082.
The etching rate of the pseudo second mask pattern 3081 containing the doped ions is greater than that of the device second mask pattern 3082, damage to the device second mask pattern 3082 is not easily caused in the process of subsequently removing the pseudo second mask pattern 3081 doped with ions, and further the fin portion formed by etching the substrate 300 by taking the device second mask pattern 3082 as a mask has better shape quality, so that the electrical performance of a semiconductor structure is improved.
In this embodiment, the doped ions are germanium ions. In other embodiments, the dopant ions may also be oxygen ions.
For specific structure and advantage descriptions of the semiconductor in this embodiment, reference may be made to the related descriptions of the first embodiment, which are not repeated.
Referring to fig. 23, a schematic structural diagram of a third embodiment of the semiconductor structure of the present invention is shown. The present embodiment is the same as the first embodiment, and will not be described again. The present embodiment is different from the first embodiment in that:
the semiconductor structure further includes a first dummy pattern unit 410 including: opposite sacrificial sidewall 407 and a second mask pattern 408 on the sidewall of said sacrificial sidewall 407; the opposite sacrificial side wall 407 and the substrate 400 enclose an opening 409, the position of the opening 409 corresponds to the position of the fin cut, and the width of the opening 409 is equal to the width of the first mask pattern 402.
In this semiconductor structure, the sacrificial sidewall 407 and the substrate 400 enclose an opening 409, and in the subsequent etching process of the substrate 400 with the second mask pattern 408, the sacrificial sidewall 407 and the substrate 400 below the opening 409 are etched, so that fin portions are formed at positions corresponding to the second mask pattern 408, and the first dummy pattern unit 410 provides for subsequently forming multiple fin portion pitches on the substrate 400, which is beneficial to improving the electrical performance of the semiconductor structure.
For specific structure and advantage descriptions of the semiconductor in this embodiment, reference may be made to the related descriptions of the first embodiment, which are not repeated.
Referring to fig. 24, a schematic structural diagram of a fourth embodiment of the semiconductor structure of the present invention is shown. The present embodiment is the same as that of the first embodiment, and will not be described in detail herein. The present embodiment is different from the first embodiment in that:
the semiconductor structure further includes a second dummy pattern unit 510 including: the device comprises a first mask pattern 502, a sacrificial side wall 507 positioned on the side wall of the first mask pattern 502, and a second mask pattern 508 positioned on any side of the sacrificial side wall 507 away from the first mask pattern 502; the other side where the second mask pattern 508 is not formed corresponds to the fin cut position.
In this semiconductor structure, the second mask pattern 508 is formed only on one side of the second dummy pattern unit 510, and the substrate 500 under the first mask pattern 502 and the second mask pattern 508 is etched to form a fin portion in the region corresponding to the second dummy pattern unit 510 on the substrate 500; the sacrificial sidewall 507 in the second dummy pattern unit 510 and the substrate 500 between the first mask pattern 502 and the second mask pattern 508 in an adjacent pattern unit are etched. The second dummy pattern unit 510 provides for forming multiple fin pitches on the substrate 500 later, which is beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, the second mask pattern 508 is formed on the sacrificial sidewall 507 at the left side of the second dummy pattern unit 510. In other embodiments, the second mask pattern 508 may also be formed on the sacrificial sidewall 507 on the right side in the second dummy pattern unit 510.
For specific structure and advantage descriptions of the semiconductor in this embodiment, reference may be made to the related descriptions of the first embodiment, which are not repeated.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
Forming a plurality of discrete first mask patterns on the substrate, the step of forming a plurality of discrete first mask patterns on the substrate comprising: forming a core material layer covering the substrate, a core mask material layer positioned on the core material layer and a photoresist layer positioned on the core mask material layer; etching the core mask material layer by taking the photoresist layer as a mask to form a first core mask layer; etching part of the side wall of the first core mask layer to form a second core mask layer, wherein the width of the second core mask layer is smaller than that of the first core mask layer; etching the core material layer by taking the second core mask layer as a mask to form a first mask pattern;
forming a sacrificial side wall on the side wall of the first mask pattern;
forming a second mask pattern on the side wall of the sacrificial side wall, wherein the material of the second mask pattern is different from that of the first mask pattern; the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern on the same side wall of the first mask pattern form pattern units, and the interval between the second mask patterns in adjacent pattern units is an integer multiple of the width of the first mask pattern; the second mask patterns in the partial pattern units comprise device second mask patterns used for forming fin parts and pseudo second mask patterns corresponding to fin cutting positions; the first mask patterns comprise device first mask patterns used for forming fin parts and pseudo first mask patterns corresponding to fin cutting positions;
Removing the pseudo first mask pattern, and then removing the pseudo second mask pattern; or removing the pseudo second mask pattern, and then removing the pseudo first mask pattern; removing the sacrificial side wall after removing the pseudo first mask pattern and the pseudo second mask pattern;
and etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a plurality of discrete fin parts.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming a semiconductor structure comprises: after the second mask pattern is formed, a first shielding layer exposing the pseudo second mask pattern is formed before the sacrificial side wall is removed;
ion doping is carried out on the pseudo second mask pattern by taking the first shielding layer as a mask, and the etching selection ratio of the pseudo second mask pattern to the second mask pattern of the device after doping is increased;
and removing the pseudo second mask pattern subjected to ion doping.
3. The method of forming a semiconductor structure of claim 1, wherein the method of forming a semiconductor structure comprises: after the second mask pattern is formed, a second shielding layer exposing the pseudo first mask pattern is formed before the sacrificial side wall is removed;
And taking the second shielding layer as a mask, and removing the pseudo first mask pattern.
4. The method of forming a semiconductor structure of claim 2, wherein ions are doped in said dummy second mask pattern by ion implantation.
5. The method of forming a semiconductor structure of claim 2, wherein the dopant ions are germanium ions or oxygen ions.
6. The method of forming a semiconductor structure of claim 2, 4 or 5, wherein the ion doping process parameters include: the implantation dose is 1.0E14 atoms per square centimeter to 5.0E15 atoms per square centimeter; the injection energy is 1Kev to 10Kev; the angle between the direction of ion implantation and the normal of the substrate surface is 10-40 degrees.
7. The method of forming a semiconductor structure of claim 2, wherein the dummy second mask pattern is removed using a wet etching process.
8. The method of claim 7, wherein the wet etching process uses an etching solution that is a tetramethylammonium hydroxide solution or a hydrofluoric acid solution.
9. The method of forming a semiconductor structure of claim 3, wherein the dummy first mask pattern is removed using a wet etching process.
10. The method of forming a semiconductor structure as recited in claim 9 wherein the etching solution used in the wet etching process is a phosphoric acid solution.
11. The method of claim 1, wherein a pitch between adjacent ones of the first mask patterns is five widths of the first mask patterns.
12. A semiconductor structure formed by the method of forming a semiconductor structure as claimed in any one of claims 1 to 11, comprising:
a substrate;
a plurality of first mask patterns, which are separated on the substrate, wherein the first mask patterns are used for forming fin parts;
the sacrificial side wall is positioned on the side wall of the first mask pattern;
the second mask pattern is positioned on the side wall of the sacrificial side wall and is used for forming fin parts, and the material of the second mask pattern is different from that of the first mask pattern; the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern on the same side wall of the first mask pattern form pattern units, and the interval between the second mask patterns in adjacent pattern units is an integer multiple of the width of the first mask pattern; the second mask patterns in the partial pattern units comprise device second mask patterns used for forming fin parts and pseudo second mask patterns corresponding to fin cutting positions; the first mask patterns comprise device first mask patterns used for forming fin parts and pseudo first mask patterns corresponding to fin cutting positions;
The sacrificial sidewall, the dummy first mask pattern and the dummy second mask pattern are used to be removed.
13. The semiconductor structure of claim 12, wherein dopant ions are located in said dummy second mask pattern for increasing an etch selectivity of said dummy second mask pattern to said device second mask pattern after doping.
14. The semiconductor structure of claim 12, further comprising a first dummy pattern unit, the first dummy pattern unit comprising: the sacrificial side wall is arranged oppositely, and the second mask pattern is positioned on the side wall of the sacrificial side wall; the opposite sacrificial side wall and the substrate enclose an opening, the position of the opening corresponds to the position of the fin cut, and the width of the opening is equal to the width of the first mask pattern.
15. The semiconductor structure of claim 12, further comprising a second dummy pattern unit, the second dummy pattern unit comprising: the first mask pattern, the sacrificial side wall positioned on the side wall of the first mask pattern, and the second mask pattern positioned on any side of the sacrificial side wall away from the first mask pattern; the position of the other side, where the second mask pattern is not formed, corresponds to the fin cutting position.
16. The semiconductor structure of claim 12, wherein the sacrificial sidewall material is amorphous carbon, amorphous germanium, or amorphous silicon.
17. The semiconductor structure of claim 12, wherein a minimum pitch adjacent the first mask pattern is 42 nm to 48 nm.
18. The semiconductor structure of claim 12, wherein the material of the first mask pattern comprises silicon, titanium nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound;
the material of the second mask pattern includes silicon, titanium nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound or nickel silicon compound.
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| US10079180B1 (en) * | 2017-03-14 | 2018-09-18 | United Microelectronics Corp. | Method of forming a semiconductor device |
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