CN111370309A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN111370309A CN111370309A CN201811605461.6A CN201811605461A CN111370309A CN 111370309 A CN111370309 A CN 111370309A CN 201811605461 A CN201811605461 A CN 201811605461A CN 111370309 A CN111370309 A CN 111370309A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a plurality of discrete first mask patterns on a substrate; forming a sacrificial side wall on the side wall of the first mask pattern; forming a second mask pattern on the side wall of the sacrificial side wall; the widths of the first mask graph, the sacrificial side wall and the second mask graph are equal, the first mask graph, the sacrificial side wall and the second mask graph which are positioned on the side wall of the same first mask graph form graph units, and the distance between the second mask graphs positioned in adjacent graph units is integral multiple of the width of the first mask graph; removing the sacrificial side wall; and etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a plurality of discrete fin parts. And etching the substrate by taking the first mask pattern and the second mask pattern as masks, and adjusting the distance between the subsequently formed fin parts by changing the distance between the corresponding adjacent pattern units on the substrate so as to further improve the performance of the semiconductor structure.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the continuous improvement of the integration level of the integrated circuit, the integrated circuit is rapidly developed to the submicron and deep submicron directions, the line width of the pattern of the integrated circuit is thinner and thinner, and the higher requirement is provided for the semiconductor process. Therefore, it is an urgent subject to study how to realize fine line width patterns to meet new requirements of semiconductor processes.
Photolithography (Lithograph) is a key process technology for implementing integrated circuit patterns. In the photolithography technique, a photosensitive material (photoresist) is coated on a thin film of a substrate, light of a wavelength band corresponding to the photosensitive characteristic of the photoresist is adopted, the light is irradiated to the surface of the photoresist through a mask plate with a specific pattern, and a photoresist pattern corresponding to the pattern on the mask plate is formed after development. In the subsequent process of the integrated circuit, the photoresist pattern is used as a barrier layer to selectively etch the film below the photoresist pattern, so that the pattern on the mask plate can be completely transferred to the film on the substrate. As the line width of the integrated circuit pattern becomes thinner, the imaging resolution of the photoresist is required to be higher, and the imaging resolution of the photoresist is inversely proportional to the wavelength of the exposure light source, and therefore, reducing the wavelength of the exposure light source becomes a main approach for realizing a fine line width pattern.
Double patterning is a technique developed for photolithography in semiconductor manufacturing to enhance feature density. In commonly performed lithography, a photoresist is applied to the surface of a semiconductor wafer, and then a pattern is defined in the photoresist. The pattern in the patterned photoresist is defined in a photolithographic mask. Self-Aligned Double Patterning (SADP) is a semiconductor process designed to reduce the number of photolithography steps required to develop a monolayer. SADP employs the formation of hard mask spacers to create other patterns not formed in the lithography mask. The pattern created by the spacers is etched out and filled in, creating further patterns in the semiconductor substrate without using additional photolithographic masks.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of discrete first mask patterns on the substrate; forming a sacrificial side wall on the side wall of the first mask pattern; forming a second mask pattern on the side wall of the sacrificial side wall; the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern on the same side wall of the first mask pattern form a pattern unit, and the distance between the second mask patterns in adjacent pattern units is integral multiple of the width of the first mask pattern; removing the sacrificial side wall; and etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a plurality of discrete fin parts.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the first mask patterns are separated on the substrate and used for forming fin parts; the sacrificial side wall is positioned on the side wall of the first mask pattern; the second mask pattern is positioned on the side wall of the sacrificial side wall and used for forming a fin part; the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern which are positioned on the same side wall of the first mask pattern form a pattern unit, and the distance between the second mask patterns positioned in adjacent pattern units is integral multiple of the width of the first mask pattern.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, a plurality of discrete first mask patterns are formed on the substrate; forming a sacrificial side wall on the side wall of the first mask pattern; and forming a second mask pattern on the side wall of the sacrificial side wall. The first mask graph and the second mask graph are arranged at intervals through the sacrificial side wall, the etching rate of the sacrificial side wall is usually larger than that of the first mask graph and that of the second mask graph, even in a small-size technical node, the first mask graph and the second mask graph are still less damaged in the process of removing the sacrificial side wall, the fin portion formed by etching the substrate by taking the first mask graph and the second mask graph as masks is still good in appearance quality, and therefore the electrical performance of the semiconductor structure can be optimized. Because the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern on the same side wall of the first mask pattern form a pattern unit, and the distance between the second mask patterns in adjacent pattern units is integral multiple of the width of the first mask pattern; therefore, the substrate is etched by taking the first mask pattern and the second mask pattern as masks, the formed fin parts and the distances among the fin parts are multiples of the widths of the fin parts, and the distances among the subsequently formed fin parts can be adjusted by changing the distances among the corresponding adjacent pattern units on the substrate, so that the design requirements of different semiconductor structures are met, and the performance of the semiconductor structures is further improved.
In an alternative, the second mask pattern in a part of the pattern units includes: a device second mask pattern for forming a Fin portion, and a dummy second mask pattern corresponding to a Fin cut (Fin cut) position; after forming a second mask pattern, before removing the sacrificial side wall, forming a first shielding layer exposing the pseudo second mask pattern, and taking the first shielding layer as a mask to ensure that a structure covered by the first shielding layer is not easy to dope in the process of carrying out ion doping on the pseudo second mask pattern; and the etching selection ratio of the pseudo second mask graph after being doped by ions to the second mask graph of the device is increased, so that other structures in the graph unit are not easily damaged in the process of removing the pseudo second mask graph after being doped by ions, and the electrical performance of the semiconductor structure is favorably improved.
In an alternative, the first mask pattern includes: a first device mask pattern used for forming the fin part and a pseudo first mask pattern corresponding to the fin cutting position; after forming the second mask pattern, before removing the sacrificial side wall, forming a second shielding layer exposing the pseudo first mask pattern; therefore, the second shielding layer is used as a mask, the structure covered by the second shielding layer is not easily damaged in the process of removing the pseudo first mask pattern, and the electrical property of the semiconductor structure is favorably improved.
Drawings
Fig. 1 to 7 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 8 to 18 are schematic structural views corresponding to respective steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention;
fig. 19 to 21 are schematic structural views corresponding to respective steps in a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;
FIG. 22 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;
FIG. 23 is a schematic structural diagram of a semiconductor structure in accordance with yet another embodiment of the present invention;
FIG. 24 is a schematic structural diagram of a semiconductor structure according to yet another embodiment of the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
As shown in fig. 1, a plurality of discrete core layers 2 are formed on a substrate 1, and a first pattern material layer (not shown) is conformally covered on the core layers 2 and the substrate 1 with the core layers 2 exposed; and removing the first pattern material layer on the core layer 2 and the substrate 1 to form a first pattern layer 3 on the side wall of the core layer 2.
As shown in fig. 2, the core layer 2 is removed in preparation for the subsequent formation of a second pattern layer on the sidewalls of the first pattern layer 3.
As shown in fig. 3, conformally covering the first pattern layer 3 and the substrate 1 with the exposed first pattern layer 3 with a second pattern material layer (not shown); and removing the second pattern material layer on the first pattern layer 3 and the substrate 1 to form a second pattern layer 4 on the side wall of the first pattern layer 3.
As shown in fig. 4, the first pattern layer 3 is removed to prepare for the subsequent formation of a third pattern layer on the sidewall of the second pattern layer 4.
As shown in fig. 5, conformally covering the second pattern layer 4 and the substrate 1 with the second pattern layer 4 exposed with a third pattern material layer (not shown); and removing the third pattern material layer on the second pattern layer 4 and the substrate 1 to form a third pattern layer 5 positioned on the side wall of the second pattern layer 4, wherein the third pattern layer 5 comprises a pseudo third pattern layer 7 and a device third pattern layer 6.
As shown in fig. 6, the second graphics layer 4 is removed.
As shown in fig. 7, the dummy third graphics layer 7 in the third graphics layer 5 is removed.
With the continuous improvement of the integration level of the integrated circuit, the line width and the pitch of the patterns in the integrated circuit are smaller and smaller, because the resolving capability of the current lithography machine is insufficient, when the pseudo third pattern layer 7 is removed, the device third pattern layer 6 adjacent to the pseudo third pattern layer 7 is easily damaged (as shown in a and B in the figure), and after the substrate 1 is etched by the damaged device third pattern 6, the formed fin part has structural defects, so that the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, in the embodiment of the invention, a plurality of discrete first mask patterns are formed on the substrate; forming a sacrificial side wall on the side wall of the first mask pattern; and forming a second mask pattern on the side wall of the sacrificial side wall. The first mask graph and the second mask graph are arranged at intervals through the sacrificial side wall, the etching rate of the sacrificial side wall is generally larger than that of the first mask graph and that of the second mask graph, the first mask graph and the second mask graph are less damaged in the process of removing the sacrificial side wall, even in a technical node with a small size, the appearance quality of a fin portion formed by etching the substrate by taking the first mask graph and the second mask graph as masks is still good, and therefore the electrical performance of the semiconductor structure can be optimized. The widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal; the first mask patterns, the sacrificial side walls and the second mask patterns on the same side walls of the first mask patterns form pattern units, and the space between the second mask patterns in adjacent pattern units is an integral multiple of the width of the first mask patterns; therefore, the substrate is etched by taking the first mask pattern and the second mask pattern as masks, the formed fin parts and the distances among the fin parts are all multiples of the width of the fin parts, and the distances among the subsequently formed fin parts can be adjusted by changing the distances among the corresponding adjacent pattern units on the substrate, so that the design requirements of different semiconductor structures are met, and the performance of the semiconductor structures is further improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 8 to 18 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.
Referring to fig. 8, a substrate 100 is provided. The substrate 100 is used to provide a process platform for subsequent fin formation.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
The step of providing the substrate 100 further comprises forming an etch-resistant layer 101 on the substrate 100. The anti-etching layer 101 protects the substrate 100 from etching in the subsequent process of forming the first mask pattern and the second mask pattern on the substrate 100.
In this embodiment, the material of the anti-etching layer 101 is silicon nitride. In other embodiments, the material of the etch-resistant layer may also be one or more of silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Referring to fig. 9 to 11, a plurality of discrete first mask patterns 102 (shown in fig. 11) are formed on the substrate 100. The first mask pattern 102 provides for the subsequent formation of a second mask pattern.
The step of forming a plurality of discrete first mask patterns 102 on the substrate 100 includes: forming a core material layer 103, a core mask material layer (not shown) on the core material layer 103, and a photoresist layer 104 on the core mask material layer on the substrate 100; etching the core mask material layer by using the photoresist layer 104 as a mask to form a first core mask layer 105 (as shown in fig. 9); etching a part of the sidewall of the first core mask layer 105 to form a second core mask layer 106 (as shown in fig. 10); and etching the core material layer 103 by using the second core mask layer 106 as a mask to form a first mask pattern 102.
The material of the first mask pattern 102 includes one or more of titanium nitride, silicon nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound. In this embodiment, the material of the first mask pattern 102 is silicon nitride.
In this embodiment, the distance between adjacent first mask patterns 102 is the width of five first mask patterns 102. In other embodiments, the pitch of the first mask patterns 102 may also be an integer multiple greater than five.
In this embodiment, the width of the first mask pattern 102 is 7nm to 8 nm. Accordingly, the minimum pitch (pitch) D of adjacent first mask patterns 102 is 42 nm to 48 nm.
It should be noted that, in the present embodiment, as shown in fig. 11, the first mask pattern 102 includes a device first mask pattern 1022 for forming a fin portion, and a dummy first mask pattern 1021 corresponding to a fin cut (fin cut) position.
With continued reference to fig. 9 and 10, a wet etching process is used to etch a portion of the sidewalls of the first core mask layer 105 to form a second core mask layer 106.
And removing part of the side wall of the first core mask layer 105 by etching, so that the width of the second core mask layer 106 is smaller than that of the first core mask layer 105, and the second core mask layer 106 is used for subsequently etching the core material layer 103 to form the first core mask layer 105.
In the conventional photolithography process, due to the limitation of photolithography capability, the first core mask layer 105 with a wider width is formed first, the difficulty of the formation process is low, and then the second core mask layer 106 with a narrower width is easily formed by removing part of the sidewall of the first core mask layer 105 by etching.
Specifically, the first core mask layer 105 is made of silicon nitride, and correspondingly, the etching solution is a phosphoric acid solution.
Referring to fig. 12, sacrificial spacers 107 are formed on sidewalls of the first mask patterns 102. And forming a second mask pattern on the side wall of the sacrificial side wall 107, wherein the sacrificial side wall 107 is used for defining a distance between the second mask pattern and the first mask pattern 102.
The step of forming the sacrificial sidewall spacers 107 includes: forming a sacrificial side wall material layer (not shown in the figure) on the sacrificial side wall 107 and the substrate 100 exposed by the sacrificial side wall 107, removing the sacrificial side wall material layer on the first mask pattern 102 and the substrate 100, and forming the sacrificial side wall 107 on the side wall of the first mask pattern 102.
In this embodiment, the sacrificial spacer 107 is made of amorphous carbon, amorphous germanium, or amorphous silicon.
In this embodiment, the width of the sacrificial sidewall 107 is 7nm to 8 nm.
In this embodiment, the sacrificial material Layer is formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. The chemical vapor deposition and the atomic layer deposition have good conformal covering capability, and the formed sacrificial side wall material layer has good thickness uniformity.
Referring to fig. 13, a second mask pattern 108 is formed on the sidewalls of the sacrificial spacers 107; the widths of the first mask pattern 102, the sacrificial side wall 107 and the second mask pattern 108 are equal, the first mask pattern 102, the sacrificial side wall 107 on the same side wall of the first mask pattern 102 and the second mask pattern 108 form a pattern unit, and the distance between the second mask patterns 108 in adjacent pattern units is an integral multiple of the width of the first mask pattern 102.
The first mask pattern 102 and the second mask pattern 108 provide for subsequent fin formation.
In the embodiment of the invention, a plurality of discrete first mask patterns 102 are formed on the substrate; forming a sacrificial side wall 107 on the side wall of the first mask pattern 102; a second mask pattern 108 is formed on the sidewalls of the sacrificial spacers 107. The first mask pattern 102 and the second mask pattern 108 are spaced by the sacrificial side wall 107, and generally, the etched rate of the sacrificial side wall 107 is greater than the etched rate of the first mask pattern 102 and the second mask pattern 108, so that even in a small-sized technology node, in the subsequent process of removing the sacrificial side wall 107, the first mask pattern 102 and the second mask pattern 108 are still less damaged, the fin feature quality formed by etching the substrate by using the first mask pattern 102 and the second mask pattern 108 as masks is still good, and further, the electrical performance of the semiconductor structure can be optimized. Because the widths of the first mask pattern 102, the sacrificial sidewall 107 and the second mask pattern 108 are equal, the first mask pattern 102, the sacrificial sidewall 107 on the sidewall of the same first mask pattern 102 and the second mask pattern 108 form a pattern unit, and the distance between the second mask patterns 108 in adjacent pattern units is an integral multiple of the width of the first mask pattern 102; therefore, the substrate 100 is subsequently etched by using the first mask pattern 102 and the second mask pattern 108 as masks, the formed distances between adjacent fins are all multiples of the width of the fins, and the distances between the subsequently formed fins can be adjusted by changing the distances between corresponding adjacent pattern units on the substrate 100, so that the design requirements of different semiconductor structures are met, and the performance of the semiconductor structures is further improved.
In this embodiment, the distance d between the second mask patterns 108 in adjacent pattern units is the width of one first mask pattern 102, that is, the distance between the adjacent pattern units is the width of one first mask pattern 102. In other embodiments, the pitch of the second mask patterns 108 in adjacent pattern units may also be a multiple of more than one width of the first mask pattern 102.
In this embodiment, the step of forming the second mask pattern 108 includes: forming a second mask pattern material layer (not shown in the figure) on the first mask pattern 102 and the sacrificial side wall 107 and on the substrate 100 exposed by the first mask pattern 102 and the sacrificial side wall 107, removing the second mask pattern material layer on the first mask pattern 102, the sacrificial side wall 107 and the substrate 100, and forming a second mask pattern 108 on the side wall of the sacrificial side wall 107.
The material of the second mask pattern 108 includes one or more of silicon, titanium nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound, and the material of the second mask pattern 108 is different from the material of the first mask pattern 102. In this embodiment, the material of the second mask pattern 108 is silicon.
It should be noted that the etched rate of the first mask pattern 102 is greater than the etched rate of the second mask pattern 108, so as to prepare for removing the first mask pattern 102 by a subsequent wet process.
In this embodiment, the second mask pattern material layer is formed by a chemical vapor deposition process or an atomic layer deposition process. The chemical vapor deposition and the atomic layer deposition have good conformal covering capability, and the formed second mask material layer has good thickness uniformity.
In this embodiment, the width of the second mask pattern 108 is 7nm to 8 nm.
In this embodiment, the second mask pattern 108 in a part of the pattern units includes: a device second mask pattern 1082 for forming a fin portion, and a dummy second mask pattern 1081 corresponding to a fin-cut position.
The subsequent steps further include etching the dummy second mask pattern 1081 to avoid fin formation at that location.
Therefore, referring to fig. 14, after forming the second mask pattern 108 and before removing the sacrificial sidewall spacers 107, the method further includes: forming a first shielding layer 109 exposing the dummy second mask pattern 1081; performing ion doping on the pseudo second mask pattern 1081 by using the first shielding layer 109 as a mask, and increasing the etching selection ratio of the pseudo second mask pattern 1081 to the device second mask pattern 1082 after doping; the ion-doped dummy second mask patterns 1081 are removed.
In the process of ion doping the dummy second mask pattern 1081 by using the first shielding layer 109 as a mask, the first mask pattern 102 and the device second mask pattern 1082 covered by the first shielding layer 109 are not easily doped; in the process of removing the ion-doped pseudo second mask pattern 1081, the structure covered by the shielding layer 109 is not easily damaged, which is beneficial to improving the electrical performance of the semiconductor structure.
After the dummy second mask pattern 1081 is ion-doped, the etched rate of the dummy second mask pattern 1081 is greater than the etched rate of the device second mask pattern 1082, such that the dummy second mask pattern 1081 is more easily removed than before doping.
In this embodiment, the step of forming the first shielding layer 109 includes: forming a shielding material layer (not shown) covering the graphic units and a photoresist layer on the shielding material layer; and etching the shielding material layer by taking the photoresist layer as a mask to form a first shielding layer 109.
It should be noted that, in this embodiment, since the etched rate of the dummy second mask pattern 1081 is greater than the etched rate of the device second mask pattern 1082, damage to the device second mask pattern 1082 is less in the process of removing the dummy second mask pattern 1081, for this reason, the first shielding layer 109 not only exposes the dummy second mask pattern 1081, but also exposes the device second mask pattern 1082, which is close to the dummy second mask pattern 1081, in the adjacent pattern unit, so as to increase a process window for forming the first shielding layer 109 and reduce the process difficulty for forming the first shielding layer 109. In other embodiments, the first blocking layer may expose only the dummy second mask pattern.
In this embodiment, the first shielding layer 109 is made of an organic material, and is easy to remove and not easy to have residue in a subsequent process. Specifically, the first blocking layer 109 is made of a bottom anti-reflective coating (BARC) material. In other embodiments, the material of the first shielding layer may also be an ODL (organic dielectric layer) material, a photoresist, a DARC (dielectric anti-reflective coating) material, a DUO (Deep UV Light Absorbing Oxide) material, or an APF (Advanced Patterning Film) material.
In this embodiment, ions are doped in the dummy second mask pattern 1081 by ion implantation. The etch rate of the dummy second mask pattern 1081 after doping ions is greater than the etch rate of the device second mask pattern 1082.
Specifically, the doping ions are germanium ions. In this embodiment, the material of the dummy second mask pattern 1081 is silicon, after germanium ions are implanted correspondingly, the material of the dummy second mask pattern 1081 is silicon germanium, and the material of the device second mask pattern 1082 is silicon, so that the etching selectivity of silicon germanium and silicon is relatively high, and therefore, when the dummy second mask pattern 1081 is removed, the etching rate of the dummy second mask pattern 1081 is greater than that of the device second mask pattern 1082. In other embodiments, the doping ions may also be oxygen ions, the material of the dummy second mask pattern is silicon, and after the oxygen ions are implanted correspondingly, the material of the dummy second mask pattern 1081 is changed into silicon oxide, so that when the dummy second mask pattern is removed, the etching rate of the dummy second mask pattern is greater than the etching rate of the device second mask pattern 1082.
It should be noted that the dosage of the dopant ion implantation should not be too large or too small. If the dosage of the doped ions is too large, too much process time is spent, and the production efficiency is not high; if the implantation dose of the doped ions is too small, the etching selection ratio of the pseudo second mask pattern 1081 of the doped ions to the device second mask pattern 1082 is not favorable to increase, and the pseudo second mask pattern 1081 is not favorable to be removed subsequently. In this embodiment, the implant dose is 1.0E14 atoms per square centimeter to 5.0E15 atoms per square centimeter.
It should be noted that the implantation energy of the dopant ions should not be too large or too small. If the implantation energy of the doped ions is too large, the doped ions easily penetrate through the dummy second mask pattern 1081 and enter the sacrificial side wall 107, which is not favorable for increasing the etching selectivity ratio between the dummy second mask pattern 1081 and the device second mask pattern 1082, is not favorable for removing the dummy second mask pattern 1081 by subsequent etching, and the doped ions also enter the substrate 100 to cause pollution; if the implantation energy of the doped ions is too small, the doped ions are likely to stay on the surface of the dummy second mask pattern 1081, which is not favorable for increasing the etching selectivity of the whole dummy second mask pattern 1081 and the device second mask pattern 1082, and is not favorable for removing the dummy second mask pattern 1081 subsequently. In this embodiment, the implantation energy is 1Kev to 10 Kev.
It should be noted that the included angle between the ion implantation direction and the normal line of the surface of the substrate 100 should not be too large or too small. If the included angle between the ion implantation direction and the normal line is too large, ions are not easy to be implanted into the bottom of the pseudo second mask pattern 1081, and the implanted ions are easy to enter the sacrificial side wall 107 and the first mask pattern 102, which is not beneficial to removing the pseudo second mask pattern 1081 by subsequent etching; if the included angle between the ion implantation direction and the normal line of the substrate 100 is too small, the implanted ions are easily concentrated at the top of the pseudo second mask pattern 1081 and in the sacrificial sidewall 107, and the implanted ions at the bottom of the pseudo second mask pattern 1081 are too few to facilitate the removal of the pseudo second mask pattern 1081 by subsequent etching. In this embodiment, the angle between the ion implantation direction and the normal of the surface of the substrate 100 is 10 to 40 degrees.
In this embodiment, after the ion doping, the dummy second mask pattern 1081 is removed by a wet etching process. Specifically, the material of the pseudo second mask pattern 1081 after being doped with ions is silicon, and correspondingly, the etching solution adopted by the wet etching process is a tetramethylammonium hydroxide solution. In other embodiments, the material of the dummy second mask pattern is silicon, the dopant ions are oxygen ions, and correspondingly, the etching solution used in the wet etching process is a hydrofluoric acid solution.
It should be noted that, in this embodiment, the dummy second mask pattern 1081 corresponds to a fin-cut region, and the dummy second mask pattern 1081 is located on the right side of the partial graphic unit. In other embodiments, the dummy second mask pattern may also be located on the left side of the partial graphic unit, and the corresponding method for removing the dummy second mask pattern has the same steps and is not described again.
Referring to fig. 15, the method of forming the semiconductor structure further includes: after removing the dummy second mask pattern 1081, the first blocking layer 109 is removed. The first blocking layer 109 is removed in preparation for the subsequent formation of a second blocking layer exposing the dummy first mask pattern 1021.
In this embodiment, the first blocking layer 109 is made of a BARC material, and the first blocking layer 109 is removed by ashing. In other embodiments, the first blocking layer may be removed by a dry etching process.
Referring to fig. 16, the method for forming the semiconductor structure includes: after the second mask pattern 108 is formed, before the sacrificial sidewall 107 is removed, a second shielding layer 110 exposing the pseudo first mask pattern 1021 (as shown in fig. 15) is formed; the second blocking layer 110 is used as a mask to remove the dummy first mask pattern 1021.
With the second blocking layer 110 as a mask, the device first mask pattern 1022 and the second mask pattern 108 covered by the second blocking layer 110 are not easily damaged in the process of removing the pseudo first mask pattern 1021, which is beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, the step of forming the second shielding layer 110 includes: forming a shielding material layer (not shown) covering the graphic units and a photoresist layer on the shielding material layer; and etching the shielding material layer by using the photoresist layer as a mask to form a second shielding layer 110.
It should be noted that, in this embodiment, since the etched rate of the first mask pattern 102 is greater than the etched rate of the second mask pattern 108, that is, the etched rate of the dummy first mask pattern 1021 is greater than the etched rate of the second mask pattern 108, the second shielding layer 110 not only exposes the dummy first mask pattern 1021, but also exposes the device second mask pattern 108 and the sacrificial sidewall 107 in the pattern unit where the dummy first mask pattern 1021 is located, so as to increase the process window for forming the second shielding layer 110, and is still applicable to the process of smaller process node. In other embodiments, the first blocking layer may expose only the dummy first mask pattern.
In this embodiment, the dummy first mask pattern 1021 is removed by a wet etching process.
Specifically, in this embodiment, the material of the dummy first mask pattern 1021 is silicon nitride, and correspondingly, the etching solution adopted in the wet etching process is a phosphoric acid solution.
It should be noted that, after the dummy first mask pattern 1021 is removed, the second blocking layer 110 is removed (as shown in fig. 16).
In this embodiment, ashing is used to remove the second mask layer 110. In other embodiments, the second shielding layer may be removed by a dry etching process.
Referring to fig. 17, the sacrificial side walls 107 are removed (as shown in fig. 16). And removing the sacrificial side walls 107 to prepare for etching the substrate 100 by taking the first device mask pattern 1021 and the second device mask pattern 1082 as masks to form a fin portion.
In this embodiment, the sacrificial spacer 107 is removed by a wet etching process, and the etched rate of the sacrificial spacer 107 is greater than the etched rates of the first mask pattern 102 and the second mask pattern 108. In other embodiments, the sacrificial spacer may be removed by a dry etching process.
Specifically, in this embodiment, a tetramethyl ammonium hydroxide solution is used to remove the sacrificial sidewall 107.
Referring to fig. 18, the substrate 100 is etched using the first mask pattern 102 and the second mask pattern 108 as masks (as shown in fig. 17), so as to form a plurality of discrete fins 111.
In this embodiment, in the process of forming the fin portion 111, the first mask pattern 102 is a device first mask pattern 1022, and the second mask pattern 108 is a device second mask pattern 1082.
In this embodiment, the substrate 100 is etched by a dry etching process to form a plurality of discrete fin portions 111. In other embodiments, the substrate may be etched by a process combining a dry process and a wet process to form a plurality of discrete fin portions.
It should be noted that, in this embodiment, the dummy second mask pattern 1081 is removed first (as shown in fig. 14), and then the dummy first mask pattern 1021 is removed (as shown in fig. 14). In other embodiments, the dummy first mask pattern 1021 may be removed first, and then the dummy second mask pattern 1081 may be removed.
Fig. 19 to 21 are schematic structural diagrams corresponding to respective steps in a second embodiment of a method for forming a semiconductor structure according to the present invention.
The same points of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that: and forming the first mask pattern.
Referring to fig. 19, a core layer 202 is formed on a substrate 200. The substrate 200 is used to provide a process platform for subsequent fin formation.
The step of providing the substrate 200 further comprises forming an etch-resistant layer 201 on the substrate 200.
For the specific description of the substrate 200 and the anti-etching layer 201, reference may be made to the corresponding description in the first embodiment, and details are not repeated here.
Referring to fig. 20, a first mask pattern 203 is formed on sidewalls of the core layer 202. The first mask pattern 203 provides for the subsequent formation of a second mask pattern.
The step of forming the first mask pattern 203 includes: conformally covering the first mask pattern material layer on the core layer 202 and the substrate 200 exposed by the core layer 202; the core layer 202 and the first mask pattern material layer on the substrate 200 are removed, and a first mask pattern 203 is formed on sidewalls of the core layer 202.
The material of the first mask pattern 203 includes one or more of titanium nitride, silicon nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound. In this embodiment, the material of the first mask pattern 203 is silicon nitride.
In this embodiment, the minimum pitch (pitch) D between adjacent first mask patterns 203 is 42 nm to 48 nm.
In this embodiment, the distance between adjacent first mask patterns 203 is the width of five first mask patterns 203. In other embodiments, the pitch of the first mask patterns 203 may also be an integer multiple greater than five.
Accordingly, in this embodiment, the width of the first mask pattern 203 is 7nm to 8 nm.
Referring to fig. 21, after the first mask pattern 203 is formed, the core layer 202 is removed (as shown in fig. 20).
In this embodiment, the forming method and corresponding effect of the first mask pattern 203 and the subsequent second mask pattern are the same as those of the first embodiment, and are not repeated in this embodiment.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. With continued reference to fig. 13, a schematic diagram of a first embodiment of the semiconductor structure of the present invention is shown.
As shown in fig. 13, the semiconductor structure includes: a substrate 100; a plurality of first mask patterns 102, which are separated from the substrate 100, wherein the first mask patterns 102 are used for forming fin portions; sacrificial side walls 107 located on the side walls of the first mask patterns 102; a second mask pattern 108 located on a sidewall of the sacrificial sidewall 107, wherein the second mask pattern 108 is used for forming a fin portion; the widths of the first mask pattern 102, the sacrificial side wall 107 and the second mask pattern 108 are equal, the first mask pattern 102, the sacrificial side wall 107 on the same side wall of the first mask pattern 102 and the second mask pattern 108 form a pattern unit, and the distance d between the second mask patterns 108 in adjacent pattern units is an integral multiple of the width of the first mask pattern 102.
In the embodiment of the invention, a plurality of discrete first mask patterns 102 are formed on the substrate; forming a sacrificial side wall 107 on the side wall of the first mask pattern 102; a second mask pattern 108 is formed on the sidewalls of the sacrificial spacers 107. The first mask pattern 102 and the second mask pattern 108 are spaced by the sacrificial side wall 107, and generally, the etched rate of the sacrificial side wall 107 is greater than the etched rate of the first mask pattern 102 and the second mask pattern 108, so that even in a small-sized technology node, the first mask pattern 102 and the second mask pattern 108 are still less damaged in the subsequent process of removing the sacrificial side wall 107, the fin feature quality formed by etching the substrate by using the first mask pattern 102 and the second mask pattern 108 as masks is still better, and further, the electrical performance of the semiconductor structure can be optimized.
Because the widths of the first mask pattern 102, the sacrificial sidewall 107 and the second mask pattern 108 are equal, the first mask pattern 102, the sacrificial sidewall 107 on the sidewall of the same first mask pattern 102 and the second mask pattern 108 form a pattern unit, and the distance d between the second mask patterns 108 in adjacent pattern units is an integral multiple of the width of the first mask pattern 102; therefore, the substrate 100 is subsequently etched by using the first mask pattern 102 and the second mask pattern 108 as masks, the formed distances between adjacent fins are all multiples of the width of the fins, and the distances between the subsequently formed fins can be adjusted by changing the distances between corresponding adjacent pattern units on the substrate 100, so that the design requirements of different semiconductor structures are met, and the performance of the semiconductor structures is further improved.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the semiconductor structure further includes: an etch-resistant layer 101, the etch-resistant layer 101 being located on the substrate 100. Accordingly, the first mask patterns 102, the sacrificial side walls 107, and the second mask patterns 108 are located on the etch-resistant layer 101.
In this embodiment, the material of the anti-etching layer 101 is silicon nitride. In other embodiments, the material of the etch-resistant layer may also be one or more of silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The material of the first mask pattern 102 includes one or more of titanium nitride, silicon nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound. In this embodiment, the material of the first mask pattern 102 is silicon nitride.
In this embodiment, the width of the first mask pattern 102 is 7nm to 8 nm.
In this embodiment, the distance between adjacent first mask patterns 102 is the width of five first mask patterns 102. In other embodiments, the pitch of the first mask patterns 102 may also be an integer multiple greater than five.
Accordingly, the minimum distance D between adjacent first mask patterns 102 is 42 nm to 48 nm.
The sacrificial sidewall 107 is used to ensure a distance between the second mask pattern 108 and the first mask pattern 102.
In this embodiment, the sacrificial spacer 107 is made of amorphous carbon, amorphous germanium, or amorphous silicon.
In this embodiment, the width of the sacrificial sidewall 107 is 7nm to 8 nm.
In this embodiment, the etched rate of the first mask pattern 102 is greater than the etched rate of the second mask pattern 108.
The material of the second mask pattern 108 includes one or more of silicon, titanium nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound, or nickel silicon compound, and the material of the second mask pattern 108 is different from the material of the first mask pattern 102. In this embodiment, the material of the second mask pattern 108 is silicon.
In this embodiment, the width of the second mask pattern 108 is 7nm to 8 nm.
Referring to fig. 22, a schematic diagram of a second embodiment of the semiconductor structure of the present invention is shown. The same parts of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that:
the second mask pattern 308 in the semiconductor structure includes: a device second mask pattern 3082 for forming a fin portion, and a dummy second mask pattern 3081 corresponding to the fin-cut position; and doping ions, which are positioned in the pseudo second mask pattern 3081, for increasing the etching selection ratio of the pseudo second mask pattern 3081 to the device second mask pattern 3082 after doping.
The etching rate of the pseudo second mask pattern 3081 containing the doped ions is greater than the etching selection of the device second mask pattern 3082, the device second mask pattern 3082 is not easily damaged in the subsequent process of removing the pseudo second mask pattern 3081 doped with the doped ions, and a fin portion formed by etching the substrate 300 by taking the device second mask pattern 3082 as a mask has better appearance quality, which is beneficial to improving the electrical performance of a semiconductor structure.
In this embodiment, the dopant ions are germanium ions. In other embodiments, the dopant ions may also be oxygen ions.
For a description of a specific structure and advantages of the semiconductor in this embodiment, reference may be made to the description of the first embodiment, which is not repeated herein.
Referring to fig. 23, a schematic diagram of a third embodiment of the semiconductor structure of the present invention is shown. The same parts of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that:
the semiconductor structure further includes a first dummy graphic unit 410 including: the sacrificial spacer 407 and the second mask pattern 408 are oppositely disposed, and are located on the sidewall of the sacrificial spacer 407; the opposite sacrificial side walls 407 and the substrate 400 enclose an opening 409, the position of the opening 409 corresponds to the position of the fin cut, and the width of the opening 409 is equal to the width of the first mask pattern 402.
In the semiconductor structure, the sacrificial side wall 407 and the substrate 400 enclose an opening 409, and in the subsequent process of etching the substrate 400 with the second mask pattern 408, the sacrificial side wall 407 and the substrate 400 below the opening 409 are etched, so that a fin portion is formed at a position corresponding to the second mask pattern 408, and the first dummy pattern unit 410 provides for forming various fin portion pitches on the substrate 400, which is beneficial to improving the electrical performance of the semiconductor structure.
For a description of a specific structure and advantages of the semiconductor in this embodiment, reference may be made to the description of the first embodiment, which is not repeated herein.
Referring to fig. 24, a schematic diagram of a fourth embodiment of the semiconductor structure of the present invention is shown. The same points of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that:
the semiconductor structure further includes a second dummy graphic unit 510 including: the first mask pattern 502, the sacrificial side wall 507 located on the side wall of the first mask pattern 502, and the second mask pattern 508 located on any side of the sacrificial side wall 507 far away from the first mask pattern 502; the other side where the second mask pattern 508 is not formed corresponds to the fin cut position.
In this semiconductor structure, the second mask pattern 508 is formed only on one side of the second dummy pattern unit 510, the substrate 500 is etched to form a fin portion in a region corresponding to the second dummy pattern unit 510 on the substrate 500, and the first mask pattern 502 and the substrate 500 under the second mask pattern 508 are etched; the sacrificial spacers 507 in the second dummy pattern unit 510 and the substrate 500 between the first mask pattern 502 and the second mask pattern 508 in the adjacent pattern unit are etched. The second dummy pattern unit 510 provides for the subsequent formation of various fin pitches on the substrate 500, which is beneficial for improving the electrical performance of the semiconductor structure.
It should be noted that, in this embodiment, the second mask pattern 508 is formed on the sacrificial sidewall 507 on the left side in the second dummy pattern unit 510. In other embodiments, the second mask pattern 508 may also be formed on the sacrificial sidewall 507 on the right side in the second dummy pattern unit 510.
For a description of a specific structure and advantages of the semiconductor in this embodiment, reference may be made to the description of the first embodiment, which is not repeated herein.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of discrete first mask patterns on the substrate;
forming a sacrificial side wall on the side wall of the first mask pattern;
forming a second mask pattern on the side wall of the sacrificial side wall; the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern on the same side wall of the first mask pattern form a pattern unit, and the distance between the second mask patterns in adjacent pattern units is integral multiple of the width of the first mask pattern;
removing the sacrificial side wall;
and etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a plurality of discrete fin parts.
2. The method for forming a semiconductor structure according to claim 1, wherein the second mask patterns in the partial pattern units include a device second mask pattern for forming a fin portion, and a dummy second mask pattern corresponding to a fin-cut position; the first mask pattern comprises a device first mask pattern used for forming a fin part and a pseudo first mask pattern corresponding to a fin cutting position;
the forming method of the semiconductor structure comprises the following steps: removing the pseudo first mask pattern and then removing the pseudo second mask pattern;
alternatively, the first and second electrodes may be,
the forming method of the semiconductor structure comprises the following steps: and removing the pseudo second mask pattern, and then removing the pseudo first mask pattern.
3. The method of forming a semiconductor structure of claim 1, wherein the second mask pattern in a portion of the pattern unit comprises: a device second mask pattern used for forming the fin part and a pseudo second mask pattern corresponding to the fin cutting position;
the forming method of the semiconductor structure comprises the following steps: after the second mask graph is formed, before the sacrifice side wall is removed, a first shielding layer exposing the pseudo second mask graph is formed;
taking the first shielding layer as a mask, carrying out ion doping on the pseudo second mask graph, and increasing the etching selection ratio of the pseudo second mask graph after doping to the second mask graph of the device;
and removing the ion-doped pseudo second mask pattern.
4. The method of forming a semiconductor structure of claim 1, wherein the first mask pattern comprises: a first device mask pattern used for forming the fin part and a pseudo first mask pattern corresponding to the fin cutting position;
the forming method of the semiconductor structure comprises the following steps: after the second mask pattern is formed, before the sacrificial side wall is removed, a second shielding layer exposing the pseudo first mask pattern is formed;
and removing the pseudo first mask pattern by taking the second shielding layer as a mask.
5. The method of claim 3, wherein the dummy second mask pattern is doped with ions by ion implantation.
6. The method of claim 3, wherein the dopant ions are germanium ions or oxygen ions.
7. The method of claim 3, 5 or 6, wherein the process parameters of the ion doping comprise: the implant dose is 1.0E14 atoms per square centimeter to 5.0E15 atoms per square centimeter; the implantation energy is 1Kev to 10 Kev; the ion implantation direction is at an angle of 10 to 40 degrees to the normal of the substrate surface.
8. The method of forming a semiconductor structure of claim 3, wherein the dummy second mask pattern is removed using a wet etching process.
9. The method of claim 8, wherein the wet etching process uses an etching solution that is a tetramethylammonium hydroxide solution or a hydrofluoric acid solution.
10. The method of forming a semiconductor structure of claim 4, wherein the dummy first mask pattern is removed using a wet etch process.
11. The method of forming a semiconductor structure of claim 10, wherein the wet etching process uses a phosphoric acid solution as an etching solution.
12. The method of claim 1, wherein a pitch between adjacent first mask patterns is a width of five first mask patterns.
13. The method of forming a semiconductor structure of claim 1, wherein forming a plurality of discrete first mask patterns on the substrate comprises:
forming a core material layer covering the substrate, a core mask material layer positioned on the core material layer and a photoresist layer positioned on the core mask material layer;
etching the core mask material layer by taking the photoresist layer as a mask to form a first core mask layer;
etching part of the side wall of the first core mask layer to form a second core mask layer;
etching the core material layer by taking the second core mask layer as a mask to form a first mask pattern;
alternatively, the first and second electrodes may be,
the step of forming a plurality of discrete first mask patterns on the substrate comprises:
forming a core layer on the substrate;
forming a first mask pattern on a sidewall of the core layer;
the method for forming the semiconductor structure further comprises the following steps: after the first mask pattern is formed, the core layer is removed.
14. A semiconductor structure, comprising:
a substrate;
the first mask patterns are separated on the substrate and used for forming fin parts;
the sacrificial side wall is positioned on the side wall of the first mask pattern;
the second mask pattern is positioned on the side wall of the sacrificial side wall and used for forming a fin part; the widths of the first mask pattern, the sacrificial side wall and the second mask pattern are equal, the first mask pattern, the sacrificial side wall and the second mask pattern which are positioned on the same side wall of the first mask pattern form a pattern unit, and the distance between the second mask patterns positioned in adjacent pattern units is integral multiple of the width of the first mask pattern.
15. The semiconductor structure of claim 14, wherein the second mask pattern comprises: a device second mask pattern used for forming the fin part and a pseudo second mask pattern corresponding to the fin cutting position;
and the doping ions are positioned in the pseudo second mask graph and used for increasing the etching selection ratio of the pseudo second mask graph and the device second mask graph after doping.
16. The semiconductor structure of claim 14, further comprising a first dummy graphics unit, the first dummy graphics unit comprising: the sacrificial side wall and the second mask pattern are arranged oppositely, and the second mask pattern is positioned on the side wall of the sacrificial side wall; the opposite sacrificial side walls and the substrate enclose an opening, the position of the opening corresponds to the position of fin cutting, and the width of the opening is equal to that of the first mask pattern.
17. The semiconductor structure of claim 14, further comprising a second dummy graphics unit, the second dummy graphics unit comprising: the first mask pattern, the sacrificial side wall positioned on the side wall of the first mask pattern, and the second mask pattern positioned on any side of the sacrificial side wall far away from the first mask pattern; and the position of the other side without the second mask pattern corresponds to the fin cutting position.
18. The semiconductor structure of claim 14, wherein the sacrificial spacer is made of amorphous carbon, amorphous germanium or amorphous silicon.
19. The semiconductor structure of claim 14, wherein a minimum pitch adjacent to the first mask pattern is 42 nm to 48 nm.
20. The semiconductor structure of claim 14, wherein the first mask pattern and the second mask pattern are of different materials; the material of the first mask pattern comprises silicon, titanium nitride, silicon carbide, silicon oxynitride, a titanium silicon compound, a cobalt silicon compound or a nickel silicon compound;
the material of the second mask pattern comprises silicon, titanium nitride, silicon carbide, silicon oxynitride, titanium silicon compound, cobalt silicon compound or nickel silicon compound.
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| US20160093502A1 (en) * | 2014-09-29 | 2016-03-31 | International Business Machines Corporation | Fin cut for tight fin pitch by two different sit hard mask materials on fin |
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| US20180047575A1 (en) * | 2016-08-09 | 2018-02-15 | International Business Machines Corporation | Self-aligned single dummy fin cut with tight pitch |
| US9911619B1 (en) * | 2016-10-12 | 2018-03-06 | Globalfoundries Inc. | Fin cut with alternating two color fin hardmask |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022205698A1 (en) * | 2021-03-30 | 2022-10-06 | 长鑫存储技术有限公司 | Mask pattern and preparation method therefor, and semiconductor structure and preparation method therefor |
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