CN113327850A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113327850A CN113327850A CN202010129524.6A CN202010129524A CN113327850A CN 113327850 A CN113327850 A CN 113327850A CN 202010129524 A CN202010129524 A CN 202010129524A CN 113327850 A CN113327850 A CN 113327850A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a base, wherein the base comprises a substrate and an alloy mask material layer positioned on the substrate; forming a pattern definition layer on the alloy mask material layer; forming an opening in the pattern definition layer, wherein the alloy mask material layer is exposed from the opening; forming an alloy layer in the opening; removing the pattern definition layer after the alloy layer is formed; etching the alloy mask material layer by taking the alloy layer as a mask to form an alloy mask layer; and etching the substrate by taking the alloy layer and the alloy mask layer as masks, and forming a plurality of spaced grooves and substrate spacers positioned between the grooves in the substrate. The alloy layer and the alloy mask layer are made of alloy materials, and in the process of etching to form the groove, the generated polymer impurities are all polymer impurities with metal ions, and the polymer impurities with the metal ions cause more consistent obstruction in the etching process, so that the appearance of the groove is uniform and better, and the improvement of the electrical property of the semiconductor structure is facilitated.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the continuous improvement of the integration level of the integrated circuit, the integrated circuit is rapidly developed to the submicron and deep submicron directions, the line width of the pattern of the integrated circuit is thinner and thinner, and the higher requirement is provided for the semiconductor process. Therefore, it is an urgent subject to study how to realize fine line width patterns to meet new requirements of semiconductor processes.
Photolithography (Lithograph) is a key process technology for implementing integrated circuit patterns. In the photolithography technique, a photosensitive material (photoresist) is coated on a thin film of a substrate, light of a wavelength band corresponding to the photosensitive characteristic of the photoresist is adopted, the light is irradiated to the surface of the photoresist through a mask plate with a specific pattern, and a photoresist pattern corresponding to the pattern on the mask plate is formed after development. In the subsequent process of the integrated circuit, the photoresist pattern is used as a barrier layer to selectively etch the film below the photoresist pattern, so that the pattern on the mask plate can be completely transferred to the film on the substrate. As the line width of the integrated circuit pattern becomes thinner, the imaging resolution of the photoresist is required to be higher, and the imaging resolution of the photoresist is inversely proportional to the wavelength of the exposure light source, and therefore, reducing the wavelength of the exposure light source becomes a main approach for realizing a fine line width pattern.
Currently, with the development of integrated circuits, the lithography technology has undergone the development processes of G-line lithography (436nm), I-line lithography (365nm), KrF deep ultraviolet lithography (248nm), ArF deep ultraviolet lithography (193nm), and the like. The kind of the exposure light source includes near Ultraviolet light (nurv), medium Ultraviolet light (MUV), deep Ultraviolet light (DUV), Extreme Ultraviolet light (EUV), and the like.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and an alloy mask material layer positioned on the substrate; forming a pattern definition layer on the alloy mask material layer; forming an opening or a plurality of discrete openings in the pattern definition layer, the opening exposing the alloy mask material layer; forming an alloy layer in the opening; after the alloy layer is formed, removing the pattern definition layer; etching the alloy mask material layer by taking the alloy layer as a mask to form an alloy mask layer; and etching the substrate by taking the alloy layer and the alloy mask layer as masks, and forming a plurality of spaced grooves and substrate isolating layers positioned between the grooves in the substrate.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: providing a base, wherein the base comprises a substrate and an alloy mask material layer positioned on the substrate; a pattern definition layer on the alloy mask material layer, the pattern definition layer having one or more openings therein exposing the alloy mask material layer; an alloy layer located in the opening.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the alloy layer is used as a mask to etch the alloy mask material layer to form an alloy mask layer, the alloy layer and the alloy mask layer are used as masks to etch the substrate, and a plurality of separated grooves are formed in the substrate. In the embodiment of the invention, the alloy layer and the alloy mask layer are made of alloy materials, and the generated polymer impurities are polymer impurities with metal ions in the process of etching to form the groove, and the polymer impurities with the metal ions cause more consistent obstruction in the etching process, so that the appearance of the groove is uniform and better, correspondingly, the quality of a metal connecting line formed in the groove subsequently is better, and the electrical property of the semiconductor structure is favorably improved.
Drawings
Fig. 1 to 9 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 10 to 21 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 9, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, the semiconductor structure includes: the mask comprises a substrate 1, a substrate mask material layer 2 located on the substrate 1, and a pattern definition layer 3 located on the substrate mask material layer 2.
Referring to fig. 1 to 5 in combination, a plurality of doped layers 9 are sequentially formed in the pattern defining layer 3 through a plurality of doping film forming steps, including: forming a first mask layer 7 on the pattern definition layer 3; forming an opening 8 exposing the pattern definition layer 3 in the first mask layer 7; doping ions in the pattern definition layer 3 exposed from the opening 8 to form a doping layer 9; after the doping layer 9 is formed, removing the first mask layer 7; the etch resistance of the doped layer 9 is greater than the etch resistance of the pattern defining layer 3.
The first mask layer 7 includes: an organic material layer 4, an anti-reflective coating 5 on the organic material layer 4, and a first photoresist layer 6 on the anti-reflective coating 5.
Referring to fig. 6, after forming a plurality of the doped layers 9, the pattern defining layer 3 is removed.
Referring to fig. 7, fig. 7 is an isometric view based on fig. 6, after removing the pattern definition layer 3, forming a second mask layer 11, wherein the second mask layer 11 is provided with a groove 12.
Referring to fig. 8, the substrate mask material layer 2 is etched using the second mask layer 11 as a mask to form a substrate mask layer 10.
After the substrate mask layer 10 is formed, the second mask layer 11 is removed.
Referring to fig. 9, after removing the second mask layer 11, etching the substrate 1 by using the doping layer 9 and the substrate mask layer 10 as masks, and forming a trench 13 in the substrate 1.
The doping layer 9 is usually made of silicon doped with boron ions, the substrate mask layer 10 is usually made of an alloy material such as titanium nitride, and correspondingly, in the process of forming the trench 13, polymer impurities generated by etching the doping layer 9 are free of metal ions, polymer impurities generated by etching the substrate mask layer 10 are free of metal ions, the polymer impurities with the metal ions and the polymer impurities without the metal ions are randomly and unevenly distributed on the surface of the substrate 1, so that the obstruction caused in the etching process is inconsistent, the uniformity of the appearance of the trench 13 is poor, and correspondingly, the quality of metal connecting lines subsequently formed in the trench 13 is poor, and the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and an alloy mask material layer positioned on the substrate; forming a pattern definition layer on the alloy mask material layer; forming an opening or a plurality of discrete openings in the pattern definition layer, the opening exposing the alloy mask material layer; forming an alloy layer in the opening; after the alloy layer is formed, removing the pattern definition layer; etching the alloy mask material layer by taking the alloy layer as a mask to form an alloy mask layer; and etching the substrate by taking the alloy layer and the alloy mask layer as masks, and forming a plurality of spaced grooves and substrate isolating layers positioned between the grooves in the substrate.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the alloy layer is used as a mask to etch the alloy mask material layer to form an alloy mask layer, the alloy layer and the alloy mask layer are used as masks to etch the substrate, and a plurality of separated grooves are formed in the substrate. In the embodiment of the invention, the alloy layer and the alloy mask layer are made of alloy materials, and the generated polymer impurities are polymer impurities with metal ions in the process of etching to form the groove, and the polymer impurities with the metal ions cause more consistent obstruction in the etching process, so that the appearance of the groove is uniform and better, correspondingly, the quality of a metal connecting line formed in the groove subsequently is better, and the electrical property of the semiconductor structure is favorably improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 10 to 21 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 10, a base is provided, the base comprising a substrate 100 and a layer 101 of alloy masking material on the substrate 100.
In this embodiment, the material of the substrate 100 includes a dielectric layer. An alloy layer is formed on the substrate 100, and the dielectric layer is etched using the alloy layer as a mask to form a trench in the dielectric layer.
The dielectric layer is made of a low-k dielectric material, so that parasitic capacitance between metal connecting lines formed subsequently can be reduced, and the RC delay of the rear section can be reduced.
Specifically, the material of the dielectric layer comprises SiCOH.
It should be noted that the substrate 100 further includes a transistor, the transistor is usually formed at the bottom of the dielectric layer, the transistor includes a gate structure, and source and drain doped regions located at two sides of the gate structure, and a contact hole plug (not shown in the figure) contacting the source and drain doped regions is further formed in the substrate.
The alloy mask material layer 101 is used to prepare for subsequent etching of the dielectric layer. The etching resistance of the alloy mask material layer 101 is high, and in the subsequent etching process of the dielectric layer, the materials of the dielectric layer and the alloy mask material layer 101 have a high etching selection ratio.
In this embodiment, the material of the alloy mask material layer 101 includes TiN and TiO2、HfN、ZrO2And Al2O3One or more of (a).
With continued reference to fig. 10, a pattern definition layer 102 is formed on the alloy mask material layer 101.
The pattern definition layer 102 is used to provide a process platform for the subsequent formation of an alloy layer.
In this embodiment, the pattern definition layer 102 is made of amorphous silicon. In other embodiments, the material of the pattern definition layer may also be silicon oxide. Amorphous silicon is a commonly used material in the process, has a simple forming process, and is beneficial to reducing the process cost of the semiconductor structure.
It should be noted that the pattern definition layer 102 is not too thick or too thin. If the pattern definition layer 102 is too thick, the aspect ratio of the opening formed in the pattern definition layer 102 is too large, and a void (void) is liable to exist in the alloy layer formed in the opening by the selective deposition process, resulting in poor formation quality of the alloy layer; if the pattern definition layer 102 is too thin, the depth of the opening formed in the pattern definition layer 102 is too small, the depth of the opening may limit the formation height of the alloy layer, and the alloy layer may not well function as a mask in the subsequent process of forming the alloy mask layer by etching the alloy mask material layer 101 with the alloy layer as a mask. In this embodiment, in the step of providing the pattern definition layer 102, the thickness of the pattern definition layer 102 is 30 nm to 50 nm.
Referring to fig. 11-16, an opening or a plurality of discrete openings 104 (shown in fig. 16) are formed in the pattern definition layer 102, and the openings 104 expose the alloy mask material layer 101.
The opening 104 provides space for the subsequent formation of an alloy layer.
In this embodiment, taking the formation of a plurality of openings 104 in the pattern definition layer 102 as an example, the step of forming the openings 104 in the pattern definition layer 102 to expose the alloy mask material layer 101 includes:
as shown in fig. 11 to 15, a plurality of discrete doping layers 105 (as shown in fig. 15) are sequentially formed in the pattern defining layer 102 through a plurality of doping film forming steps, and the etching resistance of the doping layers 105 is lower than that of the pattern defining layer 102.
The etching resistance of the doped layer 105 is less than that of the pattern definition layer 102, and the pattern definition layer 102 is less damaged in the subsequent step of removing the doped layer 105.
Specifically, the doping film forming step includes:
as shown in fig. 11, a mask layer 103 is formed on the pattern definition layer 102.
In this embodiment, the mask layer 103 includes an organic material layer 1031, an anti-reflective coating 1032 on the organic material layer 1031, and a photoresist layer 1033 on the anti-reflective coating 1032.
In this embodiment, the organic material layer 1031 includes an ODL (organic dielectric layer) material, a DUO (Deep UV Light Absorbing Oxide) material, or a soc (spin on carbon) material.
In the present embodiment, the material of the anti-reflective coating 1032 includes a BARC (bottom-antireflective coating) material or a Si-ARC (Silicon-anti-reflective coating) material.
As shown in fig. 12, a groove 106 exposing the pattern definition layer 102 is formed in the mask layer 103.
The recess 106 defines a region to be doped in the pattern-defining layer 102.
The step of forming the recess 106 includes: exposing the photoresist layer 1033 to form a photoresist groove (not shown) in the photoresist layer 1033; after the photoresist groove is formed, the anti-reflection coating 1032 and the organic material layer 1031 exposed out of the photoresist groove are etched by adopting a dry etching process to form the groove 106.
In this embodiment, the dry etching process has anisotropic etching characteristics and a better etching profile, and can transfer the photoresist groove pattern in the photoresist layer 1033 to the anti-reflective coating 1032 and the organic material layer 1031.
It should be noted that in the present embodiment, the photoresist layer 1033, the anti-reflective coating 1032 and the organic material layer 1031 are consumed in the step of forming the recess 106, and the photoresist layer 1033 is completely etched and removed when the recess 106 is formed. In other embodiments, the photoresist layer may not be completely consumed when forming the recess.
As shown in fig. 13, ions are doped into the pattern defining layer 102 exposed by the groove 106 to form a doped layer 105.
Doping ions into the pattern definition layer 102 exposed by the groove 106, so that the material of the ion-doped pattern definition layer 102 is modified, the etching resistance degree of the doping layer 105 is lower than that of the pattern definition layer 102, the etching resistance degree of the doping layer 105 is lower than that of the alloy mask material layer 101, and in the subsequent process of removing the doping layer 105, the damage of the pattern definition layer 102 and the alloy mask material layer 101 is small.
In this embodiment, ions are doped into the pattern defining layer 102 exposed by the groove 106 by ion implantation to form a doped layer 105. The ion implantation has the characteristics of simple operation, low process cost and the like.
Specifically, in the step of doping ions in the pattern definition layer exposed by the groove, the doped ions include phosphorus ions.
The process parameters of ion implantation include: the dose of the doped ion implantation is 1.0E19 atoms per square centimeter to 1.0E21 atoms per square centimeter; the implantation energy of the doped ions is 1Kev to 20Kev, and the included angle between the implantation angle of the doped ions and the normal line of the surface of the substrate 100 is less than 10 degrees.
It should be noted that the dosage of the dopant ion implantation should not be too large or too small. The extending direction perpendicular to the groove 106 is taken as a transverse direction, if the implantation dose of the dopant ions is too large, too much process time is spent, the forming efficiency of the doping layer 105 is low, and if the implantation dose of the dopant ions is too large, the dopant ions can laterally diffuse into the pattern defining layer 102 under the groove 106 where the organic material layer 1031 is not exposed, in the subsequent process of removing the doping layer 105, the transverse dimension of the formed opening is larger than the transverse dimension of the pre-designed opening, and further, the transverse dimension of the alloy layer formed in the opening in the subsequent process is too large, so that the transverse dimension of the trench formed by etching the substrate 100 is too small by taking the alloy layer as a mask, the process requirement is not met, and the electrical performance of the semiconductor structure is not optimized. If the implantation dose of the doped ions is too small, the etching selectivity of the formed doped layer 105 and the pattern definition layer 102 is relatively small, and in the subsequent process of removing the doped layer 105, the lateral dimension of the formed opening is smaller than the lateral dimension of the pre-designed opening, so that the lateral dimension of the alloy layer formed in the opening in the subsequent process is too small, the lateral dimension of the trench formed by etching the substrate 100 is too small according to the alloy layer as a mask, the process requirement is not met, and the electrical performance of the semiconductor structure is not optimized. In this embodiment, the dopant ion implantation dose is 1.0E19 atoms per square centimeter to 1.0E21 atoms per square centimeter.
It should be noted that the implantation energy of the dopant ions should not be too large or too small. If the implantation energy of the doped ions is too large, the doped ions easily penetrate through the pattern definition layer 102 and enter the alloy mask material layer 101, the alloy mask material layer 101 is easily damaged in the process of removing the doped layer 105 through etching and forming an opening, an alloy layer is formed in the opening subsequently, the alloy layer is etched to form the alloy mask material layer 101 to form an alloy mask layer, the height of a mask formed by the alloy layer and the alloy mask layer is small, the formation of a groove with a specified depth is not facilitated, and the electrical performance of a semiconductor structure is poor; if the implantation energy of the doped ions is too small, the doped ions are likely to stay on the surface of the pattern definition layer 102, so that the etching selectivity of the doped layer 105 and the pattern definition layer 102 is relatively small, and in the process of removing the doped layer 105 by etching, the lateral dimension of the formed opening is smaller than that of the pre-designed opening, so that the lateral dimension of the alloy layer formed in the opening subsequently is too small, and the lateral dimension of the trench formed by etching the substrate 100 is too small according to the alloy layer as a mask, thereby not meeting the process requirements and being not beneficial to optimizing the electrical performance of the semiconductor structure. In this embodiment, the implantation energy is 1Kev to 20 Kev.
The included angle between the implantation direction of the doped ions and the normal line of the surface of the substrate 100 is not too large. If the included angle is too large, in the process of ion implantation of the pattern definition layer 102 exposed by the groove 106, due to a shadow effect, doped ions are easily implanted into the organic material layer 1031 and the anti-reflection coating 1032, in the subsequent process of removing the doped layer 105, etching selection of the doped layer 105 and the pattern definition layer 102 is relatively small, in the subsequent process of removing the doped layer 105, the lateral dimension of a formed opening is smaller than the lateral dimension of a pre-designed opening, and further, the lateral dimension of an alloy layer subsequently formed in the opening is too small, so that the lateral dimension of a trench subsequently formed by etching the substrate 100 is too small by taking the alloy layer as a mask, which does not meet process requirements, and results in poor electrical performance of a semiconductor structure. In this embodiment, the included angle between the ion implantation direction and the normal line of the surface of the substrate 100 is less than 10 degrees.
As shown in fig. 14, after the doping layer 105 is formed, the mask layer 103 is removed.
In this embodiment, a plurality of openings need to be formed in the pattern definition layer 102, so that the mask layer 103 is removed to prepare for the next doping film forming step.
After the doping layer 105 is formed, the material of the mask layer 103 includes an organic material layer 1031 and an anti-reflective coating 1032 on the organic material layer 1031.
In this embodiment, the mask layer 103 is removed by an ashing process.
As shown in fig. 15, after a plurality of doping film formation steps, a plurality of discrete doping layers 105 are formed in the pattern defining layer 102.
In a subsequent process, the doped layer 105 is removed, and a plurality of discrete openings are formed in the pattern definition layer 102.
As shown in fig. 16, the doping layer 105 is removed, and a plurality of openings 104 exposing the alloy mask material layer 101 are formed in the pattern definition layer 102.
The opening 104 provides a process space for the subsequent formation of an alloy layer.
In this embodiment, the doped layer 105 is removed by an isotropic dry etching process. The isotropic dry etching process has the characteristics of high etching efficiency, simplicity in operation and the like, and the top of the alloy mask material layer 101 is not easily damaged. The material of the doped layer 105 comprises amorphous silicon doped with phosphorus, and the corresponding etching gas comprises hydrogen fluoride gas. In other embodiments, the doped layer may be removed by an anisotropic dry etching process.
In another embodiment, the step of forming an opening in the pattern definition layer to expose the alloy mask material layer includes: forming a mask layer on the pattern definition layer, wherein the mask layer is provided with a plurality of grooves exposing the pattern definition layer; doping ions in the pattern defining layer exposed out of the groove by taking the mask layer as a mask to form a plurality of doping layers, wherein the etching resistance of the doping layers is smaller than that of the pattern defining layer; and removing the doping layer, and forming a plurality of openings exposing the alloy mask material layer in the pattern definition layer.
Referring to fig. 17, an alloy layer 107 is formed in the opening 104.
And etching the alloy mask material layer 101 by using the alloy layer 107 as a mask to form an alloy mask layer, etching the substrate 100 by using the alloy layer 107 and the alloy mask layer as masks, and forming a plurality of separated grooves in the substrate 100. In the embodiment of the present invention, the alloy layer 107 and the alloy mask layer are made of alloy materials, and during the process of forming the trench by etching, the generated polymer impurities are all polymer impurities with metal ions, and the polymer impurities with metal ions cause more consistent obstacles during the etching process, so that the trench has better morphology uniformity, and accordingly, the quality of a metal connection line formed in the trench subsequently is better, which is beneficial to improving the electrical performance of the semiconductor structure.
It should be noted that, in the step of etching the alloy mask material layer 101 by using the alloy layer 107 as a mask, the etching selection ratio between the alloy mask material layer 101 and the alloy layer 107 is not too small. If the etching selection ratio is too small, the alloy layer 107 is easily consumed too early in the process of etching the alloy mask material layer 101 by using the alloy layer 107 as a mask, so that the alloy layer 107 cannot well function as a mask, and accordingly, the formation quality of a groove in the dielectric layer is poor. In this embodiment, in the step of etching the alloy mask material layer 101 by using the alloy layer 107 as a mask, an etching selectivity ratio of the alloy mask material layer 101 to the alloy layer 107 is greater than 3.
In this embodiment, the material of the alloy layer includes TiN and TiO2、HfN、ZrO2And Al2O3One or more of (a).
In this embodiment, in the step of forming the alloy layer 107 in the opening 104, the top surface of the alloy layer 107 is lower than the top surface of the pattern definition layer 102.
The top surface of the alloy layer 107 is lower than the top surface of the pattern definition layer 102, so that the alloy layer 107 is not easy to shield the pattern definition layer 102 in the subsequent step of removing the pattern definition layer 102, so that the pattern definition layer 102 is not easy to have residue.
It should be noted that the alloy layer 107 is not too tall or too short. If the alloy layer 107 is too high, the alloy mask material layer 101 is etched by using the alloy layer 107 as a mask, and after an alloy mask layer is formed, the height of the alloy layer 107 is still too high, which makes it easy to take too much processing time to remove the alloy layer 107. If the alloy layer 107 is too short, the alloy layer 107 is not likely to well perform the function of etching a mask in the subsequent process of etching the alloy mask material layer 101 by using the alloy layer 107 as a mask to form an alloy mask layer. In this embodiment, in the step of forming the alloy layer 107 in the opening 104, the thickness of the alloy layer 107 is one third to two thirds of the depth of the opening 104. Specifically, the height of the alloy layer 107 is 10 nm to 30 nm.
In this embodiment, a selective Deposition process (selective Deposition) is used to form an alloy layer 107 on the alloy mask material layer 101 exposed by the opening 104. The alloy layer 107 and the alloy mask material layer 101 are in direct contact.
The step of the selective deposition process comprises: forming a hydroxyl group (not shown) on the pattern definition layer 102; after the hydroxyl group is formed, treating the hydroxyl group by using gas containing a hydrophobic functional group; after the hydroxyl group is treated with a gas containing a hydrophobic functional group, an alloy layer 107 is selectively formed on the alloy mask material layer 101 exposed from the opening.
On top of the pattern-defining layer 102, the forming step of forming the hydroxyl group includes: the top of the pattern-defining layer 102 is reacted with water to form the hydroxyl group.
In this embodiment, the material of the pattern definition layer 102 includes amorphous silicon. In the process of reacting amorphous silicon with water to form silicon oxide, the silicon oxide may be provided with hydroxyl groups.
The method for forming the semiconductor structure further includes: a pattern mask (not shown) is formed in the opening 104 below the top of the pattern-defining layer 102 before the top of the pattern-defining layer 102 is reacted with water.
The pattern shielding layer makes it difficult for water to contact the side walls and the bottom surface of the opening, so that water is difficult to react with the side walls and the bottom surface of the opening, and hydroxyl groups are not easily formed on the side walls and the bottom surface of the opening, so that the hydroxyl groups are formed only on the top of the pattern defining layer 102.
Accordingly, in the step of forming the hydroxyl group by reacting the top of the pattern-defining layer 102 with water, the pattern-defining layer 102 higher than the pattern-blocking layer is reacted with water to form the hydroxyl group.
The pattern blocking layer is made of an organic material, and after a hydroxyl group is formed on the top of the pattern defining layer 102, the damage to the pattern defining layer 102 and the alloy mask material layer 101 is small in the process of removing the pattern blocking layer.
During the treatment of the hydroxyl groups with the gas containing hydrophobic functional groups, the process gas containing hydrophobic functional groups is brought into contact with the hydroxyl groups on top of the pattern-defining layer 102.
A process gas containing a hydrophobic functional group is brought into contact with the hydroxyl group on top of the pattern-defining layer 102, and the hydrophobic functional group replaces the hydroxyl group in the pattern-defining layer 102, so that the top of the pattern-defining layer 102 is modified so that the top of the pattern-defining layer 102 does not contain an adsorption site of a precursor of an alloy layer, and thus, in the subsequent step of forming an alloy layer on the alloy mask material layer exposed by the opening, the precursor of the alloy layer is not formed on top of the pattern-defining layer 102.
In this embodiment, the process gas containing hydrophobic functional groups includes a silicon-containing gas.
Specifically, the silicon-containing gas comprises one or more of alkyl silane, alkoxy silane, alkyl siloxane, alkoxy siloxane, alkyl alkoxy siloxane, aryl silane, acyl silane, aryl siloxane, acyl siloxane and silazane.
The step of selectively forming an alloy layer 107 on the alloy mask material layer 101 exposed by the opening 104 includes: a precursor of an alloy layer is selectively formed on the alloy mask material layer 101 exposed by the opening 104, and the precursor of the alloy layer is subjected to a redox reaction to form the alloy layer 107.
It should be noted that, during the process of selectively forming the precursor of the alloy layer on the alloy mask material layer 101 exposed by the opening 104, the precursor of the alloy layer is deposited indiscriminately in the pattern defining layer 102 and the opening 104 between the pattern defining layer 102, but because the top of the pattern defining layer 102 contains the hydrophobic functional group, the adsorption force between the precursor of the alloy layer and the top of the pattern defining layer 102 is poor, so that the precursor of the alloy layer is finally formed only in the opening 104.
In this embodiment, a Metal Organic Chemical Vapor Deposition (MOCVD) process is used to form a precursor of the alloy layer. The metal organic chemical vapor deposition process is favorable for improving the thickness uniformity of the precursor of the alloy layer, and has good gap filling performance and good step coverage. In other embodiments, an atomic layer deposition process may also be used to form the precursor of the alloy layer.
The precursor of the alloy layer usually contains impurity elements such as C, N, O and S, and the precursor of the alloy layer is subjected to a redox reaction, so that the impurity elements in the precursor layer of the alloy layer can be removed sufficiently easily, and the purity of the alloy layer 107 can be improved.
The method for forming the semiconductor structure further comprises the following steps: after the gas containing the hydrophobic functional group is brought into contact with the hydroxyl group on the top of the pattern-defining layer 102, the pattern-blocking layer is removed.
It should be noted that, in the process of forming the precursor of the alloy layer on the alloy mask material layer 101 exposed by the opening 104 by using the selective deposition process, the flow rate of the reaction gas should not be too large or too small. If the flow rate of the reaction gas is too large, the formation rate of the precursor of the alloy layer is too fast, the precursor of the alloy layer is easily formed on the top surface of the pattern definition layer 102, and after the precursor of the alloy layer is subjected to oxidation-reduction treatment to form an alloy layer 107, the alloy layer 107 on the top surface of the pattern definition layer 102 is easily reduced in the process of removing the pattern definition layer 102, which is not favorable for improving the formation efficiency of the semiconductor structure; and if the flow of the reaction gas is too large, the process controllability and the reaction rate uniformity of the precursor for forming the alloy layer are difficult to control. If the flow rate of the reaction gas is too small, the formation rate of the precursor of the alloy layer is too slow, which is not favorable for increasing the formation rate of the alloy layer 107. In this embodiment, in the step of forming the precursor of the alloy layer by using the selective deposition process, the flow rate of the reaction gas is 10sccm to 1000 sccm.
It should be noted that, during the process of forming the precursor of the alloy layer on the alloy mask material layer 101 exposed by the opening 104 by using the selective deposition process, the chamber pressure should not be too high or too low. If the chamber pressure is too high, the alloy layer 107 is easily formed on the top surface of the pattern definition layer 102, and then the precursor of the alloy layer is subjected to a redox treatment to form the alloy layer 107, and then the alloy layer 107 on the top surface of the pattern definition layer 102 is easily reduced in the process of removing the pattern definition layer 102, which is not favorable for improving the formation efficiency of the semiconductor structure; and if the chamber pressure is too high, the process controllability and the reaction rate uniformity of the precursor for forming the alloy layer are difficult to control. If the chamber pressure is too low, the formation rate of the precursor of the alloy layer is too slow, which is not favorable for improving the formation efficiency of the alloy layer 107. In this embodiment, a selective deposition process is used, and the chamber pressure is 1mTorr to 100mTorr during the formation of the alloy layer 107.
In other embodiments, the step of forming an alloy layer in the opening includes: forming an alloy material layer covering the opening and the pattern definition layer; removing the alloy material layer on the pattern definition layer; and after removing the alloy material layer on the pattern definition layer, etching back a part of the alloy material layer with the thickness in the opening, and taking the rest alloy material layer positioned in the opening as the alloy layer.
Accordingly, the alloy material layer is formed by using an Atomic Layer Deposition (ALD) process. The atomic layer deposition process comprises multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the alloy material layer, and in addition, the atomic layer deposition process has good gap filling performance and step coverage, and gaps (void) are not easy to appear in the alloy material layer. In other embodiments, the alloy material layer may also be formed using a chemical vapor deposition process.
Referring to fig. 18, after the alloy layer 107 is formed, the pattern definition layer 102 is removed.
The pattern definition layer 102 is removed in preparation for subsequent etching of the alloy mask material layer 101 with the alloy layer 107 as a mask.
In this embodiment, the pattern definition layer 102 is removed by a wet etching process. The wet etching process has the advantages of high etching rate, simple operation and low process cost.
In this embodiment, the pattern defining layer 102 is made of amorphous silicon, and the etching solution for removing the amorphous silicon correspondingly includes a tetramethylammonium hydroxide (TMAH) solution.
Referring to fig. 19 and 20, the alloy mask material layer 101 is etched using the alloy layer 107 as a mask to form an alloy mask layer 108.
In the subsequent process, the substrate 100 is etched by using the alloy layer 107 and the alloy mask layer 108 as masks, and a plurality of spaced trenches and substrate spacers located between the trenches are formed in the substrate 100.
In this embodiment, the alloy mask material layer 101 is etched by a dry etching process using the alloy layer 107 as a mask to form an alloy mask layer 108. The dry etching process has anisotropic etching characteristic and better etching profile controllability, and can etch a plurality of films in the same etching equipment by replacing etching gas, thereby simplifying the process steps.
It should be noted that after removing the pattern definition layer 102, before etching the alloy mask material layer 101 by using the alloy layer 107 as a mask, a substrate mask layer 109 is formed on the alloy layer 107 and the alloy mask material layer 101, the substrate mask layer 109 has a mask opening 110, and an extending direction of the mask opening 110 intersects with an extending direction of the alloy layer 107.
The extending direction of the mask opening 110 intersects with the extending direction of the alloy layer 107, and accordingly, in the process of etching the alloy mask material layer 101, the substrate mask layer 109 and the alloy layer 107 jointly serve as a mask for etching the alloy mask material layer 101.
Specifically, the extending direction of the mask opening 110 is perpendicular to the extending direction of the alloy layer 107, and the uniformity of two ends of the extending direction of the trench formed by etching the substrate 100 with the substrate mask layer 109 and the alloy layer 107 as masks is higher, which is beneficial to making the metal connecting lines formed in the trench in the subsequent process not easy to bridge together.
In this embodiment, the material of the substrate mask layer 109 includes an organic material layer 1091, an anti-reflective coating 1092 on the organic material layer 1091, and a photoresist layer 1093 on the anti-reflective coating 1092, and the mask opening 110 is located in the photoresist layer 1093.
With reference to fig. 20, in the step of etching the alloy mask material layer 101 with the alloy layer 107 as a mask to form an alloy mask layer 108, the alloy mask material layer 101 is etched with the substrate mask layer 109 and the alloy layer 107 as masks to form the alloy mask layer 108.
It should be noted that the etching resistance of the substrate mask layer 109 is smaller than the etching resistance of the alloy layer 107, and after the alloy mask material layer 101 is etched to form the alloy mask layer 108, the alloy layer 107 still has a higher thickness, so that the substrate 100 is etched by using the alloy layer 107 and the alloy mask layer 108 as masks, and a trench is formed in the substrate 100.
The method for forming the semiconductor structure further comprises the following steps: after the alloy mask layer 108 is formed, the substrate mask layer 109 is removed.
The substrate mask layer 109 does not contain metal ions, so that the substrate mask layer 109 is removed, and the problem that polymer impurities with metal ions and polymer impurities without metal ions which are formed simultaneously are randomly and unevenly distributed on the surface of the substrate 100 in the process of forming a groove by subsequent etching, so that the appearance uniformity of the subsequently formed groove is poor due to inconsistent obstruction in the process of forming the groove by etching, and correspondingly, the quality of a metal connecting line which is subsequently formed in the groove 13 is poor, so that the electrical performance of a semiconductor structure is poor is avoided.
In this embodiment, the substrate mask layer 109 is removed by an ashing process.
Referring to fig. 21, after the substrate mask layer 109 is removed, the substrate 100 is etched by using the alloy layer 107 and the alloy mask layer 108 as masks, so as to form a plurality of spaced trenches 111 and substrate spacers 112 located between the trenches 111.
In this embodiment, the alloy layer 107 and the alloy mask layer 108 are made of metal ions, and when the substrate 100 is etched by using the alloy layer 107 and the alloy mask layer 108 as masks to form the trench 111, the generated polymer impurities carry the metal ions, and the obstacles caused by the polymer impurities carrying the metal ions during the process of forming the trench 111 by etching are relatively consistent, so that the trench 111 has a relatively good uniform appearance, and accordingly, the quality of the metal connecting line formed in the trench 111 subsequently is relatively good, and the metal connecting lines in the adjacent trenches 111 are not in contact with each other, which is beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, the substrate 100 is etched by using the alloy layer 107 and the alloy mask layer 108 as masks and using a dry etching process to form a plurality of spaced trenches 111 and a substrate spacer 112 located between the trenches 111. The dry etching process has anisotropic etching characteristics and good etching profile controllability, and is beneficial to enabling the appearance of the groove 111 to meet the process requirements, and in addition, the dry etching process is beneficial to accurately controlling the forming depth of the groove 111.
Note that the trench 111 is formed in the dielectric layer.
Correspondingly, the metal connecting line formed subsequently is positioned in the groove 111, and the dielectric layer is made of a low-k dielectric material, so that the parasitic capacitance between the metal connecting lines is favorably reduced, and the RC delay of the rear section is favorably reduced.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 17, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: providing a base, wherein the base comprises a substrate 100 and an alloy mask material layer 101 positioned on the substrate 100; a pattern definition layer 102 disposed on the alloy mask material layer 101, wherein the pattern definition layer 102 has one or more openings 104 therein for exposing the alloy mask material layer 101; an alloy layer 107 located in the opening 104.
And etching the alloy mask material layer 101 by using the alloy layer 107 as a mask to form an alloy mask layer, etching the substrate 100 by using the alloy layer 107 and the alloy mask layer as masks, and forming a plurality of separated grooves in the substrate 100. In the embodiment of the present invention, the alloy layer 107 and the alloy mask layer are made of alloy materials, and during the process of forming the trench by etching, the generated polymer impurities are all polymer impurities with metal ions, and the polymer impurities with metal ions cause more consistent obstacles during the etching process, so that the trench has better morphology uniformity, and accordingly, the quality of a metal connection line formed in the trench subsequently is better, which is beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, the material of the substrate 100 includes a dielectric layer. A trench is subsequently formed in the dielectric layer.
The dielectric layer is made of a low-k dielectric material, so that parasitic capacitance between metal connecting lines formed subsequently can be reduced, and the RC delay of the rear section can be reduced.
Specifically, the material of the dielectric layer comprises SiCOH.
It should be noted that the substrate 100 further includes a transistor, the transistor is usually formed at the bottom of the dielectric layer, the transistor includes a gate structure, and source and drain doped regions located at two sides of the gate structure, and a contact hole plug (not shown in the figure) contacting the source and drain doped regions is further formed in the substrate.
And etching the alloy mask material layer 101 by taking the alloy layer 107 as a mask to form an alloy mask layer. And after forming the alloy mask layer, etching the substrate by taking the alloy mask layer and the alloy layer as masks, and forming a groove in the substrate.
In this embodiment, the material of the alloy mask material layer 101 has a high etching resistance, and in the subsequent etching process of the substrate 100, the materials of the substrate 100 and the alloy mask material layer 101 have a high etching selectivity.
In this embodiment, the material of the alloy mask material layer 101 includes TiN and TiO2、HfN、ZrO2And Al2O3One or more of (a).
In this embodiment, the pattern definition layer 102 is made of amorphous silicon. Amorphous silicon is a commonly used material in the process, has a simple forming process, and is beneficial to reducing the process cost of the semiconductor structure. In other embodiments, the material of the pattern definition layer may also be silicon oxide.
It should be noted that the pattern definition layer 102 is not too thick or too thin. The alloy layer 107 is formed in the opening 104 by a selective deposition process, if the pattern definition layer 102 is too thick, the aspect ratio of the corresponding opening 104 is too large, and a void (void) is liable to exist in the alloy layer 107 formed in the opening 104 by the selective deposition process, resulting in poor formation quality of the alloy layer 107; if the pattern definition layer 102 is too thin, so that the depth of the opening 104 formed in the pattern definition layer 102 is too small, the depth of the opening 104 may limit the formation height of the alloy layer 107, and the alloy layer 107 may not function as a mask in the subsequent process of forming the alloy mask layer by etching the alloy mask material layer 101 with the alloy layer 107 as a mask. In this embodiment, in the step of providing the pattern definition layer 102, the thickness of the pattern definition layer 102 is 30 nm to 50 nm.
The semiconductor structure further includes: a hydrophobic functional group on top of the pattern definition layer 102.
The hydrophobic functional group modifies the top of the pattern-defining layer 102 such that the top of the pattern-defining layer 102 does not contain an adsorption site of a precursor of an alloy layer, so that the alloy layer 107 is not easily formed on the top of the pattern-defining layer 102 during the formation of the alloy layer 107 using a selective deposition process.
In this embodiment, the alloy layer 107 is in direct contact with the alloy mask material layer 101. The surface of the alloy mask material layer 101 does not contain a hydrophobic functional group, and thus, the alloy layer 107 formed by the selective deposition process is in direct contact with the alloy mask material layer 101.
In this embodiment, the material of the alloy layer 107 includes TiN and TiO2、HfN、ZrO2And Al2O3One or more of (a).
It should be noted that the alloy layer 107 is not too tall or too short. If the alloy layer 107 is too high, the alloy mask material layer 101 is etched by using the alloy layer 107 as a mask, and after an alloy mask layer is formed, the height of the alloy layer 107 is still too high, which makes it easy to take too much processing time to remove the alloy layer 107. If the alloy layer 107 is too short, the alloy layer 107 is not likely to well perform the function of etching a mask in the subsequent process of etching the alloy mask material layer 101 by using the alloy layer 107 as a mask to form an alloy mask layer. In this embodiment, in the step of forming the alloy layer 107 in the opening 104, the thickness of the alloy layer is one third to two thirds of the depth of the opening 104. Specifically, the height of the alloy layer 107 is 10 nm to 30 nm.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and an alloy mask material layer positioned on the substrate;
forming a pattern definition layer on the alloy mask material layer;
forming an opening or a plurality of discrete openings in the pattern definition layer, the opening exposing the alloy mask material layer;
forming an alloy layer in the opening;
after the alloy layer is formed, removing the pattern definition layer;
etching the alloy mask material layer by taking the alloy layer as a mask to form an alloy mask layer;
and etching the substrate by taking the alloy layer and the alloy mask layer as masks, and forming a plurality of spaced grooves and substrate isolating layers positioned between the grooves in the substrate.
2. The method of claim 1, wherein an alloy layer is formed on the alloy mask material layer exposed by the opening by a selective deposition process.
3. The method of forming a semiconductor structure of claim 2, wherein the step of selectively depositing comprises: forming a hydroxyl group on top of the pattern definition layer; after the hydroxyl group is formed, treating the hydroxyl group by using gas containing a hydrophobic functional group; and after the hydroxyl is treated by gas containing hydrophobic functional groups, selectively forming an alloy layer on the alloy mask material layer exposed from the opening.
4. The method of forming a semiconductor structure of claim 3, wherein the forming of the hydroxyl group comprises: reacting the top of the pattern-defining layer with water to form the hydroxyl group.
5. The method of forming a semiconductor structure of claim 3, wherein the process gas comprising hydrophobic functional groups comprises a silicon-containing gas;
the silicon-containing gas comprises one or more of an alkylsilane, an alkoxysilane, an alkylalkoxysilane, an alkylsiloxane, an alkoxysiloxane, an alkylalkoxysiloxane, an arylsilane, an acylsilane, an arylsiloxane, an acylsiloxane, and a silazane.
6. The method of forming a semiconductor structure according to claim 1, wherein the step of selectively forming an alloy layer on the alloy mask material layer exposed by the opening comprises: selectively forming a precursor of an alloy layer on the alloy mask material layer exposed from the opening; and carrying out oxidation-reduction reaction on the precursor of the alloy layer to form the alloy layer.
7. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming an alloy mask layer by etching the alloy mask material layer using the alloy layer as a mask, an etching selectivity ratio of the alloy mask material layer to the alloy layer is greater than 3.
8. The method of claim 1 or 7, wherein the alloy layer comprises TiN, TiO, and a material of the alloy layer2、HfN、ZrO2And Al2O3One or more of (a).
9. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming an alloy layer in the opening, the alloy layer has a thickness of one third to two thirds of a depth of the opening.
10. The method of forming a semiconductor structure according to claim 1, wherein the step of forming an alloy layer in the opening comprises: forming an alloy material layer covering the opening and the pattern definition layer;
removing the alloy material layer on the pattern definition layer;
and after removing the alloy material layer on the pattern definition layer, etching back a part of the alloy material layer with the thickness in the opening, and taking the rest alloy material layer positioned in the opening as the alloy layer.
11. The method of claim 10, wherein the alloy material layer is formed using an atomic layer deposition process or a metal organic chemical vapor deposition process.
12. The method of forming a semiconductor structure of claim 1, wherein forming an opening in the pattern definition layer that exposes the layer of alloy masking material comprises: sequentially forming a plurality of discrete doping layers in the pattern defining layer through a plurality of doping film forming steps, wherein the etching resistance of the doping layers is less than that of the pattern defining layer; the doping film forming step comprises: forming a mask layer on the pattern definition layer; forming a groove exposing the pattern definition layer in the mask layer; doping ions in the pattern definition layer exposed out of the groove to form a doping layer; after the doping layer is formed, removing the mask layer;
and removing the doping layer, and forming a plurality of openings exposing the alloy mask material layer in the pattern definition layer.
13. The method of forming a semiconductor structure of claim 12, wherein a material of the pattern definition layer comprises amorphous silicon or silicon oxide.
14. The method of claim 12, wherein in the step of doping ions in the pattern-defining layer exposed by the recess, the doped ions comprise phosphorous ions.
15. The method for forming a semiconductor structure according to claim 1, wherein after removing the pattern definition layer and before etching the alloy mask material layer using the alloy layer as a mask, a substrate mask layer is formed on the alloy layer and the alloy mask material layer, the substrate mask layer having a mask opening, an extending direction of the mask opening intersecting an extending direction of the alloy layer;
etching the alloy mask material layer by taking the alloy layer as a mask to form an alloy mask layer, wherein the alloy mask material layer is etched by taking the substrate mask layer and the alloy layer as masks to form the alloy mask layer;
after the alloy mask layer is formed, removing the substrate mask layer;
and after removing the substrate mask layer, etching the substrate by taking the alloy layer and the alloy mask layer as masks to form a plurality of spaced grooves and a substrate interlayer positioned between the grooves.
16. The method for forming a semiconductor structure according to claim 15, wherein an extending direction of the mask opening is perpendicular to an extending direction of the alloy layer.
17. A semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and an alloy mask material layer positioned on the substrate;
a pattern definition layer on the alloy mask material layer, the pattern definition layer having one or more openings therein exposing the alloy mask material layer;
an alloy layer located in the opening.
18. The semiconductor structure of claim 17, wherein the alloy layer is in direct contact with the alloy mask material layer.
19. The semiconductor structure of claim 17, wherein a material of the alloy layer comprises TiN, TiO2、HfN、ZrO2And Al2O3One or more of (a).
20. The semiconductor structure of claim 17, wherein the semiconductor structure further comprises: a hydrophobic functional group on top of the pattern definition layer.
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