CN111383920A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN111383920A CN111383920A CN201811639998.4A CN201811639998A CN111383920A CN 111383920 A CN111383920 A CN 111383920A CN 201811639998 A CN201811639998 A CN 201811639998A CN 111383920 A CN111383920 A CN 111383920A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a base, wherein the base comprises a substrate and a pattern definition layer positioned on the substrate; doping ions at a plurality of positions of the pattern definition layer simultaneously or doping ions at a plurality of positions of the pattern definition layer in sequence to form a metal blocking layer, wherein the etching difficulty of the metal blocking layer is greater than that of the pattern definition layer; removing the pattern definition layer without doping ions; and etching the substrate by taking the metal blocking layer as a mask, and forming a plurality of substrate grooves and substrate isolating layers positioned among the substrate grooves in the substrate. In the subsequent processing, the substrate grooves are filled with conductive materials, and the substrate interlayer enables the conductive materials in the substrate grooves not to be easily contacted, so that the isolation of devices is realized, and the electrical performance of the semiconductor structure is optimized.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the continuous improvement of the integration level of the integrated circuit, the integrated circuit is rapidly developed to the submicron and deep submicron directions, the line width of the pattern of the integrated circuit is thinner and thinner, and the higher requirement is provided for the semiconductor process. Therefore, it is an urgent subject to study how to realize fine line width patterns to meet new requirements of semiconductor processes.
Photolithography (Lithograph) is a key process technology for implementing integrated circuit patterns. In the photolithography technique, a photosensitive material (photoresist) is coated on a thin film of a substrate, light of a wavelength band corresponding to the photosensitive characteristic of the photoresist is adopted, the light is irradiated to the surface of the photoresist through a mask plate with a specific pattern, and a photoresist pattern corresponding to the pattern on the mask plate is formed after development. In the subsequent process of the integrated circuit, the photoresist pattern is used as a barrier layer to selectively etch the film below the photoresist pattern, so that the pattern on the mask plate can be completely transferred to the film on the substrate. As the line width of the integrated circuit pattern becomes thinner, the imaging resolution of the photoresist is required to be higher, and the imaging resolution of the photoresist is inversely proportional to the wavelength of the exposure light source, and therefore, reducing the wavelength of the exposure light source becomes a main approach for realizing a fine line width pattern.
Currently, with the development of integrated circuits, the lithography technology has undergone the development processes of G-line lithography (436nm), I-line lithography (365nm), KrF deep ultraviolet lithography (248nm), ArF deep ultraviolet lithography (193nm), and the like. The kind of the exposure light source includes near Ultraviolet light (nurv), medium Ultraviolet light (MUV), deep Ultraviolet light (DUV), Extreme Ultraviolet light (EUV), and the like.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a pattern definition layer positioned on the substrate; doping ions at a plurality of positions of the pattern definition layer simultaneously or doping ions at a plurality of positions of the pattern definition layer in sequence to form a metal blocking layer, wherein the etching difficulty of the metal blocking layer is greater than that of the pattern definition layer; removing the pattern definition layer without doping ions; and etching the substrate by taking the metal blocking layer as a mask, and forming a plurality of substrate grooves and substrate isolating layers positioned among the substrate grooves in the substrate.
Optionally, ions are doped in the pattern definition layer by means of ion implantation.
Optionally, the material of the pattern definition layer is silicon oxide; the step of doping ions in the pattern definition layer includes: and doping silicon ions in the pattern definition layer to form a metal blocking layer made of silicon-rich silicon oxide.
Optionally, the material of the pattern definition layer is amorphous silicon; the step of doping ions in the pattern definition layer includes: and doping boron ions in the pattern definition layer to form a metal blocking layer.
Optionally, the process parameters of the ion implantation include: the implantation dosage is 1.0E19 atoms per square centimeter to 1.0E21 atoms per square centimeter, the implantation energy is 1Kev to 20Kev, and the included angle between the ion implantation angle and the normal line of the substrate surface is 0 to 10 degrees.
Optionally, the step of sequentially doping ions into a plurality of positions of the pattern definition layer to form the metal blocking layer includes performing a film formation substep on each of the plurality of positions, the film formation substep including: forming the first bottom anti-reflection layer on the pattern definition layer, etching the first bottom anti-reflection layer, and forming a residual first bottom anti-reflection layer and a through hole in the residual first bottom anti-reflection layer; doping ions to the pattern definition layer exposed from the through hole; and after ion doping, removing the residual first bottom anti-reflection layer.
Optionally, the step of doping ions at a plurality of positions of the pattern definition layer simultaneously includes: after the pattern definition layer is formed, before ions are doped at a plurality of positions of the pattern definition layer at the same time, a mask pattern layer with a plurality of openings is formed; and doping ions into the pattern definition layer by taking the mask pattern layer as a mask to form a metal blocking layer.
Optionally, the step of forming a mask pattern layer having a plurality of openings includes: forming a mask material layer on the pattern definition layer; performing a plurality of pattern transfer steps on the mask material layer, and forming a mask pattern layer with a plurality of openings in the mask material layer; the pattern transferring step includes: forming a first bottom anti-reflection layer on the mask material layer; etching the first bottom anti-reflection layer to form a residual first bottom anti-reflection layer and a through hole in the residual first bottom anti-reflection layer; etching the mask material layer by taking the residual first bottom anti-reflection layer as a mask to form a mask pattern layer; removing the residual first bottom anti-reflection layer; the method for forming the semiconductor structure further comprises the following steps: and after the metal blocking layer is formed, removing the mask pattern layer.
Optionally, the mask pattern layer is made of silicon nitride or silicon oxynitride.
Optionally, the material of the pattern definition layer is silicon oxide, silicon oxynitride or silicon nitride.
Optionally, the thickness of the pattern definition layer is 30 nm to 50 nm.
Optionally, the step of providing a substrate further comprises: forming a substrate mask material layer between the substrate and the pattern definition layer; the method for forming the semiconductor structure further comprises the following steps: after removing the pattern definition layer and before etching the substrate to form a substrate groove, patterning the substrate mask material layer to form a substrate mask layer; the step of forming a plurality of substrate recesses in the substrate comprises: and etching the substrate by taking the substrate mask layer and the metal blocking layer as masks, and forming a plurality of substrate grooves and substrate interlayers positioned between the substrate grooves in the substrate.
Optionally, the substrate mask layer is made of silicon nitride or titanium nitride.
Optionally, the top surface of the substrate spacer is flush with the bottom surface of the substrate mask layer.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a pattern definition layer on the substrate; the metal blocking layers are formed in the pattern definition layer, ions are doped in the metal blocking layers, and the etching difficulty of the metal blocking layers is greater than that of the pattern definition layer.
Optionally, the material of the pattern definition layer is silicon oxide or amorphous silicon.
Optionally, the thickness of the pattern definition layer is 30 nm to 50 nm.
Optionally, the metal blocking layer is made of silicon-rich silicon oxide or boron-rich amorphous silicon.
Optionally, a substrate masking material layer is located between the substrate and the pattern definition layer.
Optionally, the substrate mask layer is made of silicon nitride or titanium nitride.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, ions are doped at a plurality of positions of the pattern definition layer simultaneously or are doped at a plurality of positions of the pattern definition layer in sequence to form the metal blocking layer, the etching difficulty of the metal blocking layer is more than that of the pattern definition layer, therefore, when the substrate is etched by taking the metal blocking layer as a mask, the metal blocking layer is not easy to be etched, thereby playing a good mask role, when a plurality of substrate grooves and substrate interlayers positioned between the substrate grooves are formed in the substrate, the substrate interlayers positioned below the original metal blocking layer are not easy to be thinned, furthermore, when the substrate grooves are filled with conductive materials in subsequent processes, the conductive materials in the substrate grooves are not easy to contact with each other through the substrate interlayer, so that the isolation of devices is realized, and the electrical performance of the semiconductor structure is optimized.
In an alternative scheme, the forming method of the semiconductor structure further comprises the step of forming a mask pattern layer with a plurality of openings after the step of forming the pattern definition layer and before the step of simultaneously doping ions to a plurality of positions of the pattern definition layer. The mask pattern layer is formed by performing multiple pattern transfer steps on the mask material layer, and ions are doped in the pattern definition layer exposed out of the mask pattern layer at the same time to form a metal blocking layer. In the embodiment of the invention, a plurality of metal blocking layers can be formed by carrying out pattern transfer for a plurality of times and only carrying out doping once, so that the process steps are simplified and the working efficiency is improved on the basis of optimizing the electrical performance of the semiconductor structure.
Drawings
Fig. 1 to 10 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 11 to 20 are schematic structural views corresponding to respective steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention;
fig. 21 to 24 are schematic structural views corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 10, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, the semiconductor structure includes: the mask comprises a substrate 1, a substrate mask material layer 2 located on the substrate 1, and a pattern definition layer 3 located on the substrate mask material layer 2.
Referring to fig. 2, a first bottom anti-reflective coating 4 and a first photoresist layer 5 on the first bottom anti-reflective coating 4 are formed on the pattern defining layer 3.
Referring to fig. 3, the pattern on the first photoresist layer 5 is transferred onto the pattern defining layer 3, and a via hole 6 is formed in the pattern defining layer 3.
Referring to fig. 4, a first bottom anti-reflective coating layer and a first photoresist layer are sequentially formed on the pattern defining layer 3 where the via hole 6 is formed; the pattern in the first photoresist layer is transferred into the pattern definition layer 3, forming two vias 6 in the pattern definition layer 3.
After the two via holes 6 are formed, the remaining first bottom anti-reflection coating and the remaining first photoresist layer are removed.
Referring to fig. 5, the via hole 6 in the pattern definition layer 3 is filled with a barrier material to form the metal blocking layer 7.
Referring to fig. 6 and 7, fig. 6 is an isometric view, and fig. 7 is a view in the direction C of fig. 6, which is parallel to the extending direction of the metal blocking layer 7. The pattern definition layer 3 is removed (as shown in fig. 5), and the metal blocking layer 7 is separately located on the substrate mask material layer 2.
Referring to fig. 8 to 10, fig. 8 is a schematic axial view, and fig. 9 is a schematic cross-sectional view at the metal blocking layer 7, perpendicular to the extending direction of the metal blocking layer 7. Forming a second bottom anti-reflective coating 9 covering the metal blocking layer 7 and the substrate masking material layer 2 (as shown in fig. 6) and a second photoresist layer (not shown) on the second bottom anti-reflective coating 9, and transferring the pattern of the second photoresist layer onto the substrate masking material layer 2 to form a substrate masking layer 10. And etching the substrate 1 by taking the substrate mask layer 10 and the metal blocking layer 7 as masks, and forming substrate grooves 11 and substrate isolation layers 8 positioned between the substrate grooves 11 in the substrate 1.
Transferring the pattern of the second photoresist layer to the substrate mask material layer 2, wherein when the substrate mask layer 10 is formed, a part of the metal blocking layer 7 is easily etched; when the substrate mask layer 10 and the metal blocking layer 7 are used as masks to etch the substrate 1 to form the substrate grooves 11, the metal blocking layer 7 is removed too early, so that the top surface of the substrate isolation layer 8 is lower than the top surface of the substrate 1, and conductive materials in the substrate grooves 11 cannot be isolated by the substrate isolation layer 8 in the later period when the substrate grooves 11 are filled with the conductive materials, so that the electrical property of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a pattern definition layer positioned on the substrate; doping ions at a plurality of positions of the pattern definition layer simultaneously or doping ions at a plurality of positions of the pattern definition layer in sequence to form a metal blocking layer, wherein the etching difficulty of the metal blocking layer is greater than that of the pattern definition layer; removing the pattern definition layer without doping ions; and etching the substrate by taking the metal blocking layer as a mask, and forming a plurality of substrate grooves and substrate isolating layers positioned among the substrate grooves in the substrate.
In the embodiment of the invention, ions are doped at a plurality of positions of the pattern definition layer simultaneously or are doped at a plurality of positions of the pattern definition layer in sequence to form the metal blocking layer, the etching difficulty of the metal blocking layer is more than that of the pattern definition layer, therefore, when the substrate is etched by taking the metal blocking layer as a mask, the metal blocking layer is not easy to be etched, thereby playing a good mask role, when a plurality of substrate grooves and substrate interlayers positioned between the substrate grooves are formed in the substrate, the substrate interlayers positioned below the original metal blocking layer are not easy to be thinned, furthermore, when the substrate grooves are filled with conductive materials in subsequent processes, the conductive materials in the substrate grooves are not easy to contact with each other through the substrate interlayer, so that the isolation of devices is realized, and the electrical performance of the semiconductor structure is optimized.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 11 to fig. 20 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 11, a base is provided, the base including a substrate 100 and a pattern definition layer 101 on the substrate 100.
In this embodiment, the material of the substrate 100 includes a silicon nitride layer and a silicon oxide layer on the silicon nitride layer. The silicon nitride layer is used as an etching stop layer when the substrate 100 is etched to form a substrate groove by taking the metal blocking layer as a mask.
In other embodiments, the material of the substrate may also include silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Components, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, inductors, or the like, can also be formed within the substrate 100. The surface of the substrate 100 may also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
The pattern definition layer 101 is used to transfer a pattern in a subsequently formed photoresist layer.
In this embodiment, the material of the pattern definition layer 101 is silicon oxide. In other embodiments, the material of the pattern definition layer may also be amorphous silicon.
The step of providing a substrate further comprises: a layer of substrate masking material 108 is formed between the substrate 100 and the pattern definition layer 101.
The substrate masking material layer 108 is used to prepare the substrate 100 for subsequent etching.
In this embodiment, the substrate mask material layer 108 is made of titanium silicon. In other embodiments, the material of the substrate mask material layer may also be silicon nitride.
It should be noted that after the substrate mask material layer 108 is formed, the hard mask material layer 103 is formed on the substrate mask material layer 108 before the pattern definition layer 101 is formed. The layer of hard mask material 103 provides for the subsequent formation of a hard mask layer.
It should be noted that the pattern definition layer 101 is not too thick or too thin. If the pattern definition layer 101 is too thick, the implanted ions cannot reach the bottom of the pattern definition layer 101 when the metal blocking layer is formed by ion implantation on the pattern definition layer 101 in the following step, so that the etching resistance of the bottom of the formed metal blocking layer is poor; if the pattern definition layer 101 is too thin, ions may penetrate through the pattern definition layer 101 into the substrate mask material layer 108 when the pattern definition layer 101 is subsequently ion implanted, thereby affecting the properties of the substrate mask material layer 108. In this embodiment, the thickness of the pattern definition layer 101 is 30 nm to 50 nm.
Referring to fig. 12 to 15, doping ions are sequentially performed on a plurality of positions of the pattern definition layer 101 to form a metal blocking layer 102 (as shown in fig. 15), where the etching difficulty of the metal blocking layer 102 is greater than that of the pattern definition layer 101.
In this embodiment, the step of forming the metal barrier layer 102 includes performing film formation steps for a plurality of positions, respectively. The film forming steps comprise: forming the first bottom anti-reflection layer 104 on the pattern definition layer 101, etching the first bottom anti-reflection layer 104, and forming a residual first bottom anti-reflection layer 107 and a through hole 106 in the residual first bottom anti-reflection layer 107; doping ions to the pattern definition layer 101 exposed from the through hole 106; after ion doping, the remaining first bottom anti-reflection layer 107 is removed.
Specifically, as shown in fig. 12, the film forming substeps comprise: the first bottom anti-reflection layer 104 is formed on the pattern definition layer 101.
The first bottom anti-reflective layer 104 can improve critical dimension uniformity in a photolithography process.
In this embodiment, the first bottom anti-reflection layer 104 is formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process.
In this embodiment, the first bottom anti-reflection layer 104 includes: an amorphous carbon layer 1041 and a silicon-containing bottom antireflective layer 1042 on the amorphous carbon layer 1041.
The method for forming the semiconductor structure further includes: a photoresist layer 105 is formed on the first bottom anti-reflective layer 104.
The step of forming the photoresist layer 105 includes: a photoresist material layer is formed on the first bottom anti-reflection layer 104, and the photoresist material layer is exposed to form a photoresist layer 105.
As shown in FIG. 13, the first bottom anti-reflective layer 104 is etched (as shown in FIG. 12) to form a remaining first bottom anti-reflective layer 107 and vias 106 in the remaining first bottom anti-reflective layer 107.
The step of forming the via hole 106 includes: and etching the first bottom anti-reflection layer 104 by taking the photoresist layer 105 as a mask to form a through hole 106.
It should be noted that in the step of forming the through hole 106, the first bottom anti-reflection layer 104 is consumed continuously when the first bottom anti-reflection layer 104 is etched. In this embodiment, the first bottom anti-reflection layer 104 is etched by a dry etching process, and a through hole 106 is formed in the remaining first bottom anti-reflection layer 107.
In this embodiment, the first bottom anti-reflection layer 104 is etched by a dry etching process, in the process of forming the through hole 106, both the photoresist layer 105 and the first bottom anti-reflection layer 104 are continuously consumed, and when the through hole 106 is formed in the remaining first bottom anti-reflection layer 107, the photoresist layer 105 is completely etched and removed. In other embodiments, the photoresist layer may not be removed when the via hole is formed in the remaining first bottom anti-reflection layer.
As shown in fig. 14, ions are doped into the pattern definition layer 101 exposed by the through hole 106, and a metal blocking layer 102 is formed in the pattern definition layer 101, where the etching difficulty of the metal blocking layer 102 is greater than that of the pattern definition layer 101.
The etching difficulty of the metal blocking layer 102 is also greater than that of the substrate 100, the substrate 100 is etched by taking the metal blocking layer 102 as a mask, and when a substrate groove is formed in the substrate 100, the metal blocking layer 102 is not easily damaged.
The etching difficulty of the metal blocking layer 102 is greater than that of the pattern defining layer 101, and when the pattern defining layer 101 without doped ions is subsequently removed, the probability of damage to the metal blocking layer 102 is greatly reduced.
In this embodiment, the etching difficulty of the metal blocking layer 102 is also greater than the etching difficulty of the substrate mask material layer 108. When the substrate mask material layer 108 is etched by using the metal blocking layer 102 as a mask, the probability that the metal blocking layer 102 is damaged is smaller than the probability that the substrate mask material layer 108 is damaged.
In this embodiment, the metal blocking layer 102 is formed by doping ions into the pattern defining layer 101 by ion implantation. In other embodiments, a metal blocking layer may also be formed in the pattern definition layer by diffusion doping.
The process parameters of ion implantation include: the implant dose is 1.0E19 atoms per square centimeter to 1.0E21 atoms per square centimeter; the implantation energy is 1Kev to 20Kev, and the included angle between the ion implantation angle and the normal line of the surface of the substrate 100 is 0 to 10 degrees.
It should be noted that the dosage of the dopant ion implantation should not be too large or too small. If the dosage of the doped ions is too large, too much process time is spent, and the production efficiency is not high; if the implantation dosage of the doped ions is too small, the etching difficulty of the formed metal blocking layer 102 is not obviously improved compared with that of the pattern definition layer 101, and when the substrate 100 is etched by taking the metal blocking layer 102 as a mask, the metal blocking layer 102 is easily etched, so that the formed substrate interlayer positioned below the original metal blocking layer 102 is easily thinned, and further when conductive materials are filled in substrate grooves between the substrate interlayers subsequently, the conductive materials in the substrate grooves are easily contacted, the isolation of devices is not easily realized, and the electrical performance of a semiconductor structure is not favorably optimized. In this embodiment, the dopant ion implantation dose is 1.0E19 atoms per square centimeter to 1.0E21 atoms per square centimeter.
It should be noted that the implantation energy of the dopant ions should not be too large or too small. If the implantation energy of the doped ions is too large, the doped ions easily penetrate through the pattern definition layer 101 to enter the substrate mask material layer 108, which is not beneficial to increasing the etching selection ratio of the metal blocking layer 102 and the pattern definition layer 101, the metal blocking layer 102 is easily etched, so that a substrate interlayer formed below the original metal blocking layer 102 subsequently is easily thinned, and further, when conductive materials are filled in substrate grooves between the substrate interlayers subsequently, the conductive materials in the substrate grooves are easily contacted, so that the isolation of devices is not easy to realize, and the electrical performance of a semiconductor structure is not beneficial to being optimized; if the implantation energy of the doped ions is too small, the doped ions are likely to stay on the surface of the pattern definition layer 101, which is not beneficial to increasing the etching selectivity of the metal blocking layer 102 and the pattern definition layer 101. In this embodiment, the implantation energy is 1Kev to 20 Kev.
The angle between the ion implantation direction and the normal of the surface of the substrate 100 should not be too large. And subsequently, the metal blocking layer 102 is used as a mask to etch the substrate isolation layers formed on the substrate 100 and the substrate grooves between the substrate isolation layers. If the included angle between the ion implantation direction and the surface of the substrate 100 is too large, the size of the substrate groove is smaller than the design value in the extending direction of the substrate groove, and then the substrate interlayer is filled with a conductive material, so that the conductive material is easy to break down the substrate interlayer, the isolation of devices is not easy to realize, and the electrical performance of the semiconductor structure is not favorable to be optimized. In this embodiment, the included angle between the ion implantation direction and the normal line of the surface of the substrate 100 is 0 to 10 degrees.
In this embodiment, the material of the pattern definition layer 101 is silicon oxide; the step of doping ions in the pattern definition layer 101 includes: the pattern defining layer 101 is doped with silicon ions to form a metal blocking layer 102 made of silicon-rich silicon oxide.
In other embodiments, the material of the pattern definition layer is amorphous silicon; the step of doping ions in the pattern definition layer includes: and doping boron ions in the pattern definition layer to form a metal blocking layer.
With continued reference to FIG. 14, after ion doping, the remaining first bottom anti-reflective layer 107 is removed. The remaining first bottom anti-reflection layer 107 is removed in preparation for subsequent film formation sub-steps or for removal of the pattern defining layer 101 not doped with ions.
In this embodiment, an ashing process is used to remove the remaining first bottom anti-reflective layer 107.
Referring to fig. 15, in the present embodiment, two film formation steps are taken as an example. Accordingly, two metal blocking layers 102 are formed in fig. 15.
Referring to fig. 16-17, wherein fig. 16 is an axial side view and fig. 17 is a view from direction a of fig. 16, the view from direction a being parallel to the extending direction of the metal blocking layer 102. The pattern defining layer 101, which is not doped with ions, is removed. And removing the pattern definition layer 101 without doped ions to expose the metal blocking layer 102, so as to prepare for etching the substrate 100 by taking the metal blocking layer 102 as a mask to form a substrate groove.
In this embodiment, the pattern defining layer 101 not doped with ions is removed by a wet etching process.
Referring to fig. 18-20, fig. 18 is an isometric view, and fig. 19 is a cross-sectional view of fig. 18 taken parallel to the B-direction view, which is perpendicular to the direction of extension of the metallic blocking layer 102. The substrate 100 is etched by using the metal blocking layer 102 as a mask, and a plurality of substrate grooves 109 (shown in fig. 20) and substrate spacers 110 (shown in fig. 20) located between the substrate grooves 109 are formed in the substrate 100.
The metal blocking layer 102 is used as a mask to etch substrate grooves 109 formed in the substrate 100 and substrate spacers 110 located between the substrate grooves 109, the substrate grooves 109 are isolated from each other through the substrate spacers 110, and in the subsequent process, when conductive materials are filled in the substrate grooves 109, the conductive materials in the substrate grooves are not easily contacted through the substrate spacers, so that the isolation of devices is realized, and the electrical performance of a semiconductor structure is optimized.
As shown in fig. 18 and 19, the method for forming the semiconductor structure further includes: after removing the pattern definition layer 101, before etching the substrate 100 to form a substrate groove 109, patterning the substrate mask material layer 108 to form a substrate mask layer 111.
In this embodiment, the step of patterning the substrate mask material layer 108 to form the substrate mask layer 111 includes: forming a second bottom anti-reflection layer 112 covering the metal blocking layer 102 and the substrate masking material layer 108 and a substrate photoresist material layer (not shown) on the second bottom anti-reflection layer 112, and performing an exposure process on the substrate photoresist material layer to form a substrate photoresist layer (not shown); the pattern of the substrate photoresist layer is transferred into the substrate masking material layer 108 to form a substrate masking layer 111.
It should be noted that, in the step of positioning the metal blocking layer 102 in the second bottom anti-reflection layer 112, patterning the substrate masking material layer 108, and forming the substrate masking layer 111, the metal blocking layer 102 also serves as a mask.
It should be further noted that, before the substrate mask material layer 108 is patterned to form the substrate mask layer 111, the hard mask material layer 103 is patterned to form the hard mask layer 115. The hard mask layer 115 enables the sidewalls of the formed substrate mask layer 111 to have better verticality with the substrate 100.
As shown in fig. 20, the etching of the substrate 100 with the metal blocking layer 102 as a mask means that the substrate 100 is etched with the metal blocking layer 102 and the substrate mask layer 111 as masks.
The step of forming a plurality of substrate recesses 109 in the substrate 100 comprises: and etching the substrate 100 by taking the substrate mask layer 111 and the metal blocking layer 102 as masks, and forming a plurality of substrate grooves 109 and substrate isolation layers 110 positioned between the substrate grooves 109 in the substrate 100.
In this embodiment, the etching difficulty of the metal blocking layer 102 formed by doping ions is also greater than the etching difficulty of the substrate mask material layer 108. Taking the substrate mask layer 111 and the metal blocking layer 102 as masks, and removing the metal blocking layer 102 in the process of forming the substrate groove 109; after the metal blocking layer 102 is etched and removed, continuing to etch the substrate mask layer 111 to form a substrate mask layer groove 113; the substrate mask layer 111 originally exposed from the metal blocking layer 102 is removed by a certain thickness in the process of etching the substrate 100 and forming the substrate recess 109, so as to form a residual substrate mask layer 114. In other embodiments, the etching difficulty of the metal blocking layer may be much greater than that of the substrate mask material layer, and the metal blocking layer is not completely etched and removed after the process of forming the substrate groove.
It should be noted that the bottom surface of the substrate mask layer 111 and the bottom surface of the residual substrate mask layer 114 are at the same position. In this embodiment, the top surface of the substrate isolation layer 110 is flush with the bottom surface of the substrate mask layer 111, which means that the top surface of the substrate isolation layer 110 is flush with the bottom surface of the remaining substrate mask layer 114.
The substrate mask layer 111 and the metal blocking layer 102 are used as masks, the substrate 100 is etched, after a plurality of substrate grooves 109 and substrate isolation layers 110 located between the substrate grooves 109 are formed in the substrate 100, conductive materials are filled in the substrate grooves 109, and the conductive materials in the substrate grooves 109 are not easy to contact with each other through the substrate isolation layers 110, so that isolation of devices is achieved, and electrical properties of a semiconductor structure are optimized.
Fig. 21 to 24 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
The same parts of this embodiment as those of the previous embodiment will not be described herein again. The present embodiment is different from the previous embodiment in that ions are doped simultaneously at a plurality of positions of the pattern definition layer 201. The step of simultaneously doping the plurality of positions of the pattern definition layer 201 with ions includes: after the pattern definition layer 201 is formed, before ions are doped to a plurality of positions of the pattern definition layer 201 at the same time, a mask pattern layer 203 with a plurality of openings is formed; and doping ions into the pattern definition layer 201 by taking the mask pattern layer 203 as a mask to form a metal blocking layer 202. The etching difficulty of the metal blocking layer 202 is greater than that of the pattern definition layer 201.
Referring to fig. 21 and 22, after forming the pattern definition layer 201, before simultaneously doping ions to a plurality of positions of the pattern definition layer 201, the step of forming a mask pattern layer 203 having a plurality of openings 204 includes: forming a mask material layer 206 on the pattern definition layer 201; a plurality of pattern transfer steps are performed on the masking material layer 206 to form a masking pattern layer 203 having a plurality of openings 204 in the masking material layer 206.
As shown in fig. 21, the pattern transferring step includes: a first bottom anti-reflective layer 207 is formed on the masking material layer 206.
In this embodiment, the first bottom anti-reflection layer 207 includes: an amorphous carbon layer 2071 and a silicon-containing bottom anti-reflective layer 2072 on the amorphous carbon layer 2071.
The method for forming the semiconductor structure further includes: before forming the first bottom anti-reflection layer 207 on the mask material layer 206, a base is provided, which includes the substrate 200, the substrate mask material layer 208 on the substrate 200, the pattern definition layer 201 on the substrate mask material layer 208, and the mask material layer 206 on the pattern definition layer 201.
It should be noted that the substrate further includes: a hard mask material layer 209 located between the substrate mask material layer 208 and the pattern definition layer 201. The hard mask material layer 209 enables the sidewalls of the substrate mask layer formed by subsequent patterning to be more perpendicular to the substrate 100.
As shown in fig. 22, the pattern transferring step further includes: etching the first bottom anti-reflection layer 207 to form a remaining first bottom anti-reflection layer (not shown) and a via hole (not shown) in the remaining first bottom anti-reflection layer; etching the mask material layer 206 by using the remaining first bottom anti-reflection layer as a mask to form a mask pattern layer 203; and removing the residual first bottom anti-reflection layer.
The step of forming a remaining first bottom anti-reflection layer and a via hole in the remaining first bottom anti-reflection layer includes: after the first bottom anti-reflection layer 207 is formed, forming a photoresist material layer covering the first bottom anti-reflection layer 207, and performing exposure treatment on the photoresist material layer to form a photoresist layer 205; the first bottom anti-reflection layer 207 is etched using the photoresist layer 205 as a mask to form a remaining first bottom anti-reflection layer (not shown) and a via hole in the remaining first bottom anti-reflection layer.
It should be noted that in this embodiment, in the process of forming the through hole by using the dry etching process, both the photoresist layer 205 and the first bottom anti-reflection layer 207 are continuously consumed, and when the through hole is formed in the remaining first bottom anti-reflection layer, the photoresist layer 205 is completely etched and removed. In other embodiments, the photoresist layer may not be completely removed when the via is formed in the remaining first bottom anti-reflection layer.
Referring to fig. 23, the step of doping ions into the pattern definition layer 201 by using the mask pattern layer 203 as a mask to form the metal blocking layer 202 includes: after the multiple pattern transfer steps are completed, doping ions are carried out in the pattern defining layer 201 exposed by the mask pattern layer 203, and a metal blocking layer 202 is formed.
In the embodiment of the invention, the pattern on the photoresist layer 205 is transferred to the mask pattern layer 203 through multiple pattern transfer steps, then ions are doped in the pattern definition layer 201 exposed out of the mask pattern layer 203 to form the metal blocking layer 202, and through multiple pattern transfer, only one doping is performed to form a plurality of metal blocking layers 202, so that the process steps are simplified on the basis of optimizing the electrical performance of the semiconductor structure, and the working efficiency is improved.
The method for forming the semiconductor structure further comprises the following steps: after the metal blocking layer 202 is formed, the mask pattern layer 203 is removed.
In the subsequent steps, the removal of the pattern definition layer 201 without doped ions and the etching of the substrate 200 with the metal blocking layer 202 as a mask are the same as in the previous embodiment, and are not repeated herein.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 15, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a pattern definition layer 101 on the substrate 100; the metal blocking layers 102 are located in the pattern definition layer 101, ions are doped in the metal blocking layers 102, and the etching difficulty of the metal blocking layers 102 is greater than that of the pattern definition layer 101.
In this embodiment, the material of the substrate 100 includes a silicon nitride layer and a silicon oxide layer on the silicon nitride layer.
In other embodiments, the material of the substrate may also include silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Components, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, inductors, or the like, can also be formed within the substrate 100. The surface of the substrate 100 may also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the material of the pattern definition layer 101 is silicon oxide. In other embodiments, the material of the pattern definition layer may also be silicon oxynitride or silicon nitride.
It should be noted that the pattern definition layer 101 is not too thick or too thin. The metal blocking layer 102 is formed by performing ion implantation on a part of the pattern defining layer 101, if the pattern defining layer 101 is too thick, the bottom of the metal blocking layer 102 formed by performing ion implantation on the pattern defining layer 101 is provided with the pattern defining layer 101 with a part of thickness, so that the height of the formed metal blocking layer 102 is lower than a design value; if the pattern definition layer 101 is too thin, the implanted ions will penetrate through the pattern definition layer 101 into the substrate mask material layer 108, so that the formed metal blocking layer 102 has poor etching resistance. In this embodiment, the thickness of the pattern definition layer 101 is 30 nm to 50 nm.
In addition, the semiconductor structure further includes: a hard mask material layer 103 located between the substrate mask material layer 108 and the pattern definition layer 101. The layer 209 of hard mask material provides for the subsequent formation of a hard mask layer.
In this embodiment, a substrate mask material layer 108 is located between the substrate 100 and the pattern definition layer 101. The layer of substrate masking material 108 provides for the formation of a substrate masking layer 111 (shown in fig. 19) in a subsequent process.
In this embodiment, the substrate mask material layer 108 is made of titanium nitride. In other embodiments, the material of the substrate mask material layer may also be silicon nitride.
In this embodiment, the etching difficulty of the metal blocking layer 102 formed by doping ions is greater than the etching difficulty of the substrate mask material layer 108.
In this embodiment, the material of the metal blocking layer 102 is silicon-rich silicon oxide. In other embodiments, the material of the metal blocking layer may also be boron-rich amorphous silicon.
In the subsequent process, the substrate 200 is etched by using the metal blocking layer 102 and the substrate mask layer 111 as masks, and a plurality of substrate grooves 109 (as shown in fig. 20) and substrate spacers 110 (as shown in fig. 20) located between the substrate grooves are formed in the substrate 200. After the substrate groove 109 is formed, the substrate groove 109 is filled with a conductive material, and the filling materials between the substrate interlayers 110 are not in contact, so that the isolation of a device is realized, and the electrical performance of a semiconductor structure is optimized.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a pattern definition layer positioned on the substrate;
doping ions at a plurality of positions of the pattern definition layer simultaneously or doping ions at a plurality of positions of the pattern definition layer in sequence to form a metal blocking layer, wherein the etching difficulty of the metal blocking layer is greater than that of the pattern definition layer;
removing the pattern definition layer without doping ions;
and etching the substrate by taking the metal blocking layer as a mask, and forming a plurality of substrate grooves and substrate isolating layers positioned among the substrate grooves in the substrate.
2. The method of claim 1, wherein the pattern definition layer is doped with ions by ion implantation.
3. The method of forming a semiconductor structure according to claim 2, wherein a material of the pattern definition layer is silicon oxide; the step of doping ions in the pattern definition layer includes: and doping silicon ions in the pattern definition layer to form a metal blocking layer made of silicon-rich silicon oxide.
4. The method of forming a semiconductor structure of claim 2, wherein the pattern definition layer is formed of amorphous silicon; the step of doping ions in the pattern definition layer includes: and doping boron ions in the pattern definition layer to form a metal blocking layer.
5. The method of claim 2, 3 or 4, wherein the ion implantation process parameters comprise: the implantation dosage is 1.0E19 atoms per square centimeter to 1.0E21 atoms per square centimeter, the implantation energy is 1Kev to 20Kev, and the included angle between the ion implantation angle and the normal line of the substrate surface is 0 to 10 degrees.
6. The method of forming a semiconductor structure according to claim 1, wherein the step of sequentially doping a plurality of sites of the pattern defining layer with ions to form the metal blocking layer comprises performing film formation substeps for each of the plurality of sites, the film formation substeps comprising:
forming the first bottom anti-reflection layer on the pattern definition layer, etching the first bottom anti-reflection layer, and forming a residual first bottom anti-reflection layer and a through hole in the residual first bottom anti-reflection layer; doping ions to the pattern definition layer exposed from the through hole; and after ion doping, removing the residual first bottom anti-reflection layer.
7. The method of claim 1, wherein the step of simultaneously doping the plurality of sites of the pattern definition layer with ions comprises: after the pattern definition layer is formed, before ions are doped at a plurality of positions of the pattern definition layer at the same time, a mask pattern layer with a plurality of openings is formed; and doping ions into the pattern definition layer by taking the mask pattern layer as a mask to form a metal blocking layer.
8. The method of forming a semiconductor structure of claim 7, wherein the step of forming a mask pattern layer having a plurality of openings comprises:
forming a mask material layer on the pattern definition layer; performing a plurality of pattern transfer steps on the mask material layer, and forming a mask pattern layer with a plurality of openings in the mask material layer;
the pattern transferring step includes: forming a first bottom anti-reflection layer on the mask material layer; etching the first bottom anti-reflection layer to form a residual first bottom anti-reflection layer and a through hole in the residual first bottom anti-reflection layer; etching the mask material layer by taking the residual first bottom anti-reflection layer as a mask to form a mask pattern layer; removing the residual first bottom anti-reflection layer;
the method for forming the semiconductor structure further comprises the following steps: and after the metal blocking layer is formed, removing the mask pattern layer.
9. The method for forming a semiconductor structure according to claim 8, wherein a material of the mask pattern layer is silicon nitride or silicon oxynitride.
10. The method of claim 1, wherein the pattern definition layer is made of silicon oxide, silicon oxynitride, or silicon nitride.
11. The method of claim 1, wherein the pattern definition layer has a thickness of 30 nm to 50 nm.
12. The method of forming a semiconductor structure of claim 1, wherein the step of providing a substrate further comprises: forming a substrate mask material layer between the substrate and the pattern definition layer;
the method for forming the semiconductor structure further comprises the following steps: after removing the pattern definition layer and before etching the substrate to form a substrate groove, patterning the substrate mask material layer to form a substrate mask layer;
the step of forming a plurality of substrate recesses in the substrate comprises: and etching the substrate by taking the substrate mask layer and the metal blocking layer as masks, and forming a plurality of substrate grooves and substrate interlayers positioned between the substrate grooves in the substrate.
13. The method of claim 12, wherein the substrate mask layer is made of silicon nitride or titanium nitride.
14. The method of forming a semiconductor structure of claim 12, wherein a top surface of the substrate spacer layer is flush with a bottom surface of the substrate mask layer.
15. A semiconductor structure, comprising:
a substrate;
a pattern definition layer on the substrate;
the metal blocking layers are doped with ions, and the etching difficulty of the metal blocking layers is greater than that of the pattern definition layers.
16. The semiconductor structure of claim 15, wherein the pattern definition layer is silicon oxide or amorphous silicon.
17. The semiconductor structure of claim 15, wherein the pattern definition layer has a thickness of 30 nm to 50 nm.
18. The semiconductor structure of claim 15, wherein the material of the metal blocking layer is silicon-rich silicon oxide or boron-rich amorphous silicon.
19. The semiconductor structure of claim 15, wherein a layer of substrate masking material is located between the substrate and the pattern definition layer.
20. The semiconductor structure of claim 19, wherein the material of the substrate mask material layer is silicon nitride or titanium nitride.
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