CN111509043B - Mask pattern forming method and fin field effect transistor - Google Patents
Mask pattern forming method and fin field effect transistor Download PDFInfo
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- CN111509043B CN111509043B CN201910091989.4A CN201910091989A CN111509043B CN 111509043 B CN111509043 B CN 111509043B CN 201910091989 A CN201910091989 A CN 201910091989A CN 111509043 B CN111509043 B CN 111509043B
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 230000005669 field effect Effects 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 78
- 239000007943 implant Substances 0.000 claims abstract description 48
- 239000000945 filler Substances 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 19
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 238000005530 etching Methods 0.000 description 13
- 238000002513 implantation Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 239000002210 silicon-based material Substances 0.000 description 7
- 239000011800 void material Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 241001660693 Trapezia Species 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910052800 carbon group element Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/76—Patterning of masks by imaging
Abstract
The invention discloses a method for forming a mask pattern, which comprises the steps of depositing and forming a mask layer; forming a photoresist layer pattern on the mask layer; implanting mask layer gap fillers into the mask layer through the intervals of the photoresist layer patterns; implanting a mask layer implant into the mask layer via the spaces of the photoresist layer pattern; and removing the photoresist layer pattern and the mask layer blocked by the photoresist layer pattern. According to the method for forming the mask pattern, the mask layer gap filler is implanted into the mask layer, so that diffusion and scattering phenomena of the mask layer implant are reduced. Therefore, the mask layer implant can diffuse and scatter according to a preset path, so that the shape of the mask pattern becomes regular, and the quality of the mask pattern is improved. The invention also provides a fin field effect transistor with higher mask quality and better performance.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming a mask pattern and a fin field effect transistor.
Background
In the whole process of semiconductor chip manufacturing, a part of the process is the middle of the layout to wafer manufacturing, namely mask manufacturing. Because this process is a critical part of the overall semiconductor manufacturing process, it is also the most expensive part of the process, and is one of the bottlenecks that limit the nodes of the semiconductor chip manufacturing process. Therefore, mask fabrication plays a very important role in the production process of semiconductor chips.
In addition, in the process of producing semiconductor chips, the patterns of the silicon chips used are all derived from the patterns of the mask, and therefore, the quality of the mask patterns is related to the quality of the whole chip.
With the increasing demands on the performance of semiconductor chips, this means that there is an increasing demand for each process of the semiconductor chips, including the manufacture of masks. Commonly used materials for forming the mask include silicon oxide, silicon nitride, amorphous silicon, and the like. Compared with silicon oxide and silicon nitride, the amorphous silicon material has the advantages of low cost, easy image formation, high selectivity during etching and the like, and is widely applied to three-dimensional field effect transistors, such as fin field effect transistors; in the highly integrated three-dimensional field effect transistor, for example, the fin field effect transistor with the process node smaller than 10nm, the choice of amorphous silicon as the mask material has become the mainstream. But high quality mask patterns are difficult and heavy to form.
The existing method for forming the mask pattern is as follows: and coating a photoresist on the mask, implanting boron ions into the gap of the photoresist once, and then removing the photoresist and the amorphous silicon material. However, since the amorphous silicon material itself has a small density, a chip using the amorphous silicon material has many voids, and the more voids, the more the diffusion and scattering phenomena of boron ions at the time of implantation become apparent. Over time, the surface of the mask may become rough and uneven, thereby affecting the subsequent etching.
In addition, since boron ions are implanted only once, the cross-sectional shape of the formed mask pattern may have a trapezoid shape, an inverted trapezoid shape, or even a shuttle shape. These non-uniform shapes can lead to over-etching or under-etching of the chip during etching.
Disclosure of Invention
The invention aims to solve the problem of low quality of mask pattern formation in the prior art. The invention provides a mask pattern forming method and a fin field effect transistor prepared by the method, which can improve the mask pattern forming quality. Further, the roughness of the mask surface can be reduced.
In order to solve the above technical problems, an embodiment of the present invention discloses a method for forming a mask pattern, including the following steps: depositing to form a mask layer; forming a photoresist layer pattern on the mask layer; implanting mask layer gap fillers into the mask layer through the intervals of the photoresist layer patterns; implanting a mask layer implant into the mask layer via the spaces of the photoresist layer pattern; and removing the photoresist layer pattern and the mask layer blocked by the photoresist layer pattern.
By adopting the technical scheme, the formation quality of the mask pattern can be improved, and the situation of over etching or incomplete etching is avoided.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, wherein a material of the mask layer is amorphous silicon.
By adopting the technical scheme, the cost of the mask is lower, the image is easier to form, and the selectivity is higher during etching.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, wherein the mask layer gap filler is at least one of carbon, germanium, tin, lead, and titanium, and the number of times of implanting the mask layer gap filler is at least one.
By adopting the technical scheme, gaps in the amorphous silicon material can be filled, so that the surface of the mask is smoother and smoother.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, wherein the mask layer implant is at least one of boron, gallium and indium, and the number of times of implantation of the mask layer implant is at least one.
By adopting the technical scheme, the gaps of the amorphous silicon material can be effectively filled, so that the shape of the cross section of the mask pattern is more regular.
According to another embodiment of the present invention, a method for forming a mask pattern according to an embodiment of the present invention is provided, wherein when the number of times of implanting a mask layer implant is two or more, the mask layer implant is sequentially implanted from a side close to the contact between the mask layer and a photoresist layer pattern to a side far from the photoresist layer pattern in the mask layer.
By adopting the technical scheme, the gaps of the amorphous silicon material can be further filled, so that the shape of the cross section of the mask pattern is more regular.
According to another embodiment of the present invention, a method for forming a mask pattern according to an embodiment of the present invention, depositing a mask layer includes: providing a substrate, and sequentially forming a first oxide layer, a titanium nitride layer and a second oxide layer on the substrate, wherein the first oxide layer is close to the substrate, and the second oxide layer is far away from the substrate; and depositing a mask layer on the second oxide layer.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, wherein the first oxide layer and the second oxide layer are plasma enhanced oxide layers.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, and a mask layer is deposited by a plasma enhanced chemical vapor deposition method or a furnace tube deposition method.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, and a process for removing a photoresist layer pattern includes dry etching or wet etching; the mask layer for removing the pattern shielding of the photoresist layer comprises a mask layer for removing the pattern shielding of the photoresist layer through tetramethyl ammonium hydroxide or ammonia water.
The embodiment of the invention also discloses a fin field effect transistor, and the mask pattern of the fin field effect transistor is prepared by the method.
The fin field effect transistor with the mask pattern formed by the method has the advantages that the mask pattern of the fin field effect transistor is more regular and the performance is better.
Drawings
FIG. 1 is a flowchart of a method for forming a mask pattern according to an embodiment of the present invention;
fig. 2 to fig. 7 are schematic process flow diagrams for forming a mask pattern according to an embodiment of the invention.
Reference numerals:
1. a mask layer; 11. mask layer gap filler; 12. a mask pattern; 2. a photoresist layer pattern; 3. a first oxide layer; 4. a titanium nitride layer; 5. a second oxide layer; 6. a substrate.
Detailed Description
Further advantages and effects of the present invention will become apparent to those skilled in the art from the disclosure of the present specification, by describing the embodiments of the present invention with specific examples. While the description of the invention will be described in connection with the preferred embodiments, it is not intended to limit the inventive features to the implementation. Rather, the purpose of the invention described in connection with the embodiments is to cover other alternatives or modifications, which may be extended by the claims based on the invention. The following description contains many specific details for the purpose of providing a thorough understanding of the present invention. The invention may be practiced without these specific details. Furthermore, some specific details are omitted from the description in order to avoid obscuring the invention. It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
It should be noted that in this specification, like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present embodiment, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", "inner", "bottom", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship in which the inventive product is conventionally put in use, are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present invention.
The terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In the description of the present embodiment, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present embodiment can be understood in a specific case by those of ordinary skill in the art.
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
In order to solve the problem of low quality of mask pattern formation in the prior art. The invention provides a mask pattern forming method. Specifically, referring to fig. 1, the method for forming a mask pattern provided in this embodiment includes:
step S1: and depositing to form a mask layer. Specifically, the mask layer 1 is deposited at a position where the mask pattern 12 is required to be formed, and the mask pattern 12 is formed on the mask layer 1. Further, the deposition forming mask layer 1 may be specifically formed on an oxide layer or a substrate.
Further, referring to fig. 2 to 6, in the technical solution provided in the present invention, depositing to form the mask layer 1 includes: providing a substrate 6, and sequentially forming a first oxide layer 3, a titanium nitride layer 4 and a second oxide layer 5 on the substrate 6, wherein the first oxide layer 3 is close to the substrate 6, and the second oxide layer 5 is far away from the substrate 6; a mask layer 1 is deposited on the second oxide layer 5. It is to be understood that, in order to protect the titanium nitride layer 4, a dielectric layer may also be formed on the titanium nitride layer 4. Specifically, the dielectric layer may be silicon nitride, silicon oxide, or other dielectric materials. Namely, a second oxide layer 5, a dielectric layer, a titanium nitride layer 4 and a first oxide layer 3 are sequentially deposited below the mask layer 1, the first oxide layer 3 is close to the substrate 6, and the second oxide layer 5 is close to the mask layer 1. Further, the dielectric layer is deposited by an atomic layer deposition process or a plasma enhanced chemical vapor deposition method.
It should be noted that, referring to fig. 2 to fig. 6, in the technical solution provided by the present invention, the material of the mask layer 1 is amorphous silicon. Amorphous silicon has the characteristic of active chemical property, so that the amorphous silicon is used as the material of the mask layer 1, and the pattern is easier to form; furthermore, because of the specificity of the amorphous silicon structure, the amorphous silicon can be made thin and the manufacturing cost is low. However, since amorphous silicon has a low density, there are many voids.
Step S2: a photoresist layer pattern 2 is formed on the mask layer 1. In particular, see fig. 3. The formation of the photoresist layer pattern 2 on the mask layer 1 may be specifically divided into the following steps: the first step, coating a photoresist, namely coating a photoresist layer (not shown in the figure) with uniform thickness on the mask layer 1; step two, a photomask is arranged and exposure is carried out on the photoresist, namely the photoresist to be etched is exposed through the photomask; third, the photoresist is etched, and the exposed photoresist is etched immediately to form a photoresist layer pattern 2.
Step S3: and implanting mask layer gap filler into the mask layer through the interval of the photoresist layer pattern. In particular, see fig. 4. After the etching of the photoresist layer in step S2, a portion of the photoresist layer is etched and a portion of the photoresist layer is not etched. The non-etched portion forms a photoresist pattern 2, and the mask layer 1 at the interval of the photoresist pattern 2 is not covered by the photoresist, i.e. the portion is etched. Thus, the mask layer gap filler 11 directly enters the mask layer 1 through the space between the photoresist layer patterns 2.
More specifically, the mask layer gap filler 11 is used to fill the gap of the mask layer 1 when the density of the material of the mask layer 1 is low, so as to prevent the occurrence of the phenomenon of roughness of the surface of the mask layer 1 and the phenomenon of irregular shape of the formed mask pattern 12.
Further, in the technical solution provided in the present invention, referring to fig. 4, the mask layer gap filler 11 is at least one of carbon, germanium, tin, lead, and aluminum. The scheme adopts carbon implantation. Specifically, the mask layer gap filler 11 selects a carbon group element other than silicon in order to prevent the other elements from reacting with silicon.
Further, the mask layer void filler 11 is implanted at least once, i.e., the mask layer void filler 11 may be implanted once, twice, or even more. The specific number of implants may be selected by those skilled in the art according to the actual situation, as long as the mask layer void filler 11 is implanted to reduce the diffusion and scattering phenomena during implantation of the mask layer implant. Specifically, the method of implanting the mask layer void filler 11 includes, but is not limited to, diffusion and ion implantation, which is not specifically limited in this embodiment.
In the mask layer 1 with smaller density, such as amorphous silicon, the mask layer gap filler 11 is implanted, so that the gap of amorphous silicon can be filled by using the mask layer gap filler 11, then the implanted atoms cannot be seriously diffused or scattered, the mask layer 1 can be implanted according to a preset implantation path, the shape of the mask pattern is more regular, and the quality of the mask pattern is further improved.
Further, the method of implanting the mask layer void filler 11 is less costly and more convenient to operate than other methods of adding a thin film layer or adding a mask pattern to achieve reduced scattering and diffusion of the mask layer implant. Meanwhile, no waste is generated, and the method is more environment-friendly.
Step S4: a mask layer implant is implanted into the mask layer through the spaces of the photoresist layer pattern. In particular, see fig. 5. There are spaces between the photoresist layer patterns 2, and the mask layer implant is continued to be implanted through the spaces between the photoresist layer patterns 2. This process may also be referred to as mask layer implant doping.
Further, in the technical scheme provided by the invention, referring to fig. 5, the mask layer implant is at least one of boron, gallium and indium, and the embodiment selects the boron implant. The number of times of implanting the mask layer implant is more than one. In particular, the mask layer implant may be implanted one, two, or even three or more times. The mask layer implant is implanted for a plurality of times, so that the shape of the mask pattern 12 can be adjusted, and trapezia, inverted trapezia and shuttles of the shape of the mask pattern 12 are avoided, thereby preventing over etching or incomplete etching in the subsequent etching process. In particular, the method of implanting the mask layer implant includes, but is not limited to, ion implantation and doping, which is not particularly limited in this embodiment.
Further, in the technical solution provided in the present invention, refer to fig. 5. When the number of times of implantation of the mask layer implant is two or more, the mask layer implant is implanted in the mask layer 1 from the side closer to the side where the mask layer 1 contacts the photoresist layer pattern 2 to the side farther from the photoresist layer pattern 2. That is, the mask layer implant is only present within the mask layer 1 after implantation. In addition, since the mask layer 1 has a certain thickness, the mask layer implant should be implanted close to the side where the mask layer 1 contacts the photoresist layer pattern 2 during implantation, and then the mask layer implant should be sequentially implanted away from the photoresist layer pattern 2. When the mask layer implant is implanted only once, the mask layer implant is directly implanted near the side of the mask layer 1 contacting the photoresist layer pattern 2, and the mask layer implant can continuously fill the gap of the side of the mask layer 1 far from the photoresist layer pattern 2 due to the scattering and diffusion effects. When the mask layer implant implantation is performed for a plurality of times, the mask layer implant is implanted near the side where the mask layer 1 contacts the photoresist layer pattern 2 for the first time, and the mask layer implant implantation after the second time can be sequentially implanted toward the side where the mask layer 1 is far away from the photoresist layer pattern 2, so as to fill the gap of the side where the mask layer 1 is far away from the photoresist layer pattern 2. This process can be understood as the filling of the mask layer implant first of all of the non-smooth portions close to the side of the mask layer 1 in contact with the photoresist layer pattern 2 and then of the side remote from the photoresist layer pattern 2.
Step S5: and removing the photoresist layer pattern and the mask layer blocked by the photoresist layer pattern. Specifically, referring to fig. 6, the photoresist layer pattern 2 is removed, and referring to fig. 7, the mask layer 1 blocked by the photoresist layer pattern 2 is removed. The amorphous silicon portion doped with the mask layer void filler 11 and the mask layer implant left after the removal is the mask pattern 12.
It should be noted that, in the technical solution provided by the present invention, referring to fig. 6 to fig. 7, the process adopted for removing the photoresist layer pattern 2 includes dry etching or wet etching; the removal of the mask layer 1 blocked by the photoresist layer pattern 2 includes removing the mask layer 1 blocked by the photoresist layer pattern 2 by tetramethylammonium hydroxide or ammonia water. Namely, the photoresist layer pattern 2 is removed mainly by adopting a photoetching process, and in the photoetching process, when the photoresist layer pattern 2 is removed by developing and etching, the selected solution is tetramethyl ammonium hydroxide or ammonia water.
Further, in the technical solution provided in the present invention, referring to fig. 2 to 7, the first oxide layer 3 and the second oxide layer 5 are plasma enhanced oxide layers. The plasma enhanced oxide layer has good impurity masking effect and protective isolation effect due to the specific conductivity and instability.
Further, in the technical scheme provided by the invention, referring to fig. 2 to 6, the mask layer 1 is deposited by adopting a plasma enhanced chemical vapor deposition method or a furnace tube deposition method.
The technical scheme of the invention also discloses a fin field effect transistor, and the fin field effect transistor prepared by the mask pattern forming method has better performance because the mask pattern is more regular in shape and higher in quality.
Further, in this embodiment, the process node of the finfet is less than 16nm. Specifically, the process node of the FinFET can be various sizes of 16nm, 14nm, 10nm or 7nm and below 7 nm. The method for forming the mask pattern provided by the embodiment can be also suitable for fin field effect transistors with the thickness of more than 16nm.
In the method for forming the mask pattern, the mask layer gap filler, such as carbon, is implanted before the mask layer implant is implanted. Carbon fills the gaps of the mask layer with smaller density, so that the mask layer implant is implanted into the mask layer according to a preset implantation path without serious diffusion and scattering phenomena. So that the surface of the mask layer becomes smoother and flatter. And, the carbon implantation does not affect the mask characteristics.
Compared with other methods for adding a film layer or adding a mask pattern to reduce scattering and diffusion of a mask layer implant, the method for implanting the mask layer gap filler has lower cost and is more convenient to operate. Meanwhile, no waste is generated, and the method is more environment-friendly.
Further, the original implant implanted into the mask layer is changed into implant implanted more than once, so that the concentration of carbon in each part of the mask layer can be effectively balanced, the shape of the mask pattern can be adjusted, and the occurrence of trapezia, inverted trapezia and other shapes can be avoided. Thereby improving the quality of the mask pattern.
The embodiment of the invention discloses a method for forming a mask pattern, which comprises the following steps: depositing to form a mask layer; forming a photoresist layer pattern on the mask layer; implanting mask layer gap fillers into the mask layer through the intervals of the photoresist layer patterns; implanting a mask layer implant into the mask layer via the spaces of the photoresist layer pattern; and removing the photoresist layer pattern and the mask layer blocked by the photoresist layer pattern.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, wherein a material of the mask layer is amorphous silicon.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, wherein the mask layer gap filler is at least one of carbon, germanium, tin, lead, and titanium, and the number of times of implanting the mask layer gap filler is at least one.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, wherein the mask layer implant is at least one of boron, gallium and indium, and the number of times of implantation of the mask layer implant is at least one.
According to another embodiment of the present invention, a method for forming a mask pattern according to an embodiment of the present invention is provided, wherein when the number of times of implanting a mask layer implant is two or more, the mask layer implant is sequentially implanted from a side close to the contact between the mask layer and a photoresist layer pattern to a side far from the photoresist layer pattern in the mask layer.
According to another embodiment of the present invention, a method for forming a mask pattern according to an embodiment of the present invention, depositing a mask layer includes: providing a substrate, and sequentially forming a first oxide layer, a titanium nitride layer and a second oxide layer on the substrate, wherein the first oxide layer is close to the substrate, and the second oxide layer is far away from the substrate; and depositing a mask layer on the second oxide layer.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, wherein the first oxide layer and the second oxide layer are plasma enhanced oxide layers.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, and a mask layer is deposited by a plasma enhanced chemical vapor deposition method or a furnace tube deposition method.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed in the embodiment of the present invention, and a process for removing a photoresist layer pattern includes dry etching or wet etching; the mask layer for removing the pattern shielding of the photoresist layer comprises a mask layer for removing the pattern shielding of the photoresist layer through tetramethyl ammonium hydroxide or ammonia water.
The embodiment of the invention also discloses a fin field effect transistor, and the mask pattern of the fin field effect transistor is prepared by the method.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing is a further detailed description of the invention with reference to specific embodiments, and it is not intended to limit the practice of the invention to those descriptions. Various changes in form and detail may be made therein by those skilled in the art, including a few simple inferences or alternatives, without departing from the spirit and scope of the present invention.
Claims (7)
1. A method for forming a mask pattern, comprising the steps of:
depositing to form a mask layer;
forming a photoresist layer pattern on the mask layer;
implanting mask layer gap fillers into the mask layer through the intervals of the photoresist layer patterns, wherein the mask layer gap fillers are at least one of carbon, germanium, tin, lead and titanium, and the times of implanting the mask layer gap fillers are at least one time;
implanting mask layer implants into the mask layer through the intervals of the photoresist layer patterns, wherein the mask layer implants are at least one of boron, gallium and indium, and the times of implanting the mask layer implants are at least one time;
removing the photoresist layer pattern and the mask layer blocked by the photoresist layer pattern;
the process for removing the photoresist layer pattern comprises dry etching or wet etching;
and removing the mask layer blocked by the photoresist layer pattern by using tetramethyl ammonium hydroxide or ammonia water.
2. The method of claim 1, wherein the mask layer is amorphous silicon.
3. The method of forming a mask pattern according to claim 1, wherein when the number of times of implanting the mask layer implant is two or more, the mask layer implant is implanted in the mask layer from a side closer to the mask layer contacting the photoresist layer pattern to a side farther from the photoresist layer pattern.
4. The method of claim 1, wherein depositing a mask layer comprises:
providing a substrate, and sequentially forming a first oxide layer, a titanium nitride layer and a second oxide layer on the substrate, wherein the first oxide layer is close to the substrate, and the second oxide layer is far away from the substrate;
and depositing and forming the mask layer on the second oxide layer.
5. The method of claim 4, wherein the first oxide layer and the second oxide layer are plasma enhanced oxide layers.
6. The method of forming a mask pattern as claimed in claim 4, wherein,
the mask layer is deposited by adopting a plasma enhanced chemical vapor deposition method or a furnace tube deposition method.
7. A fin field effect transistor, wherein a mask pattern of the fin field effect transistor is prepared based on the method for forming a mask pattern according to any one of claims 1 to 6.
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| CN101308768A (en) * | 2007-05-14 | 2008-11-19 | 海力士半导体有限公司 | Method of forming pattern of semiconductor device |
| TW200926260A (en) * | 2007-12-07 | 2009-06-16 | Nanya Technology Corp | Patterning method |
| CN102347217A (en) * | 2010-07-27 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for making fine pattern on semiconductor device |
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| US20150270144A1 (en) * | 2014-03-20 | 2015-09-24 | Inotera Memories, Inc. | Patterned structure of semiconductor device and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308768A (en) * | 2007-05-14 | 2008-11-19 | 海力士半导体有限公司 | Method of forming pattern of semiconductor device |
| TW200926260A (en) * | 2007-12-07 | 2009-06-16 | Nanya Technology Corp | Patterning method |
| CN102347217A (en) * | 2010-07-27 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for making fine pattern on semiconductor device |
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