KR20130008730A - Method for forming sti trench of semiconductor device - Google Patents

Method for forming sti trench of semiconductor device Download PDF

Info

Publication number
KR20130008730A
KR20130008730A KR1020110069247A KR20110069247A KR20130008730A KR 20130008730 A KR20130008730 A KR 20130008730A KR 1020110069247 A KR1020110069247 A KR 1020110069247A KR 20110069247 A KR20110069247 A KR 20110069247A KR 20130008730 A KR20130008730 A KR 20130008730A
Authority
KR
South Korea
Prior art keywords
region
trench
depth
ferry
mask
Prior art date
Application number
KR1020110069247A
Other languages
Korean (ko)
Inventor
김명옥
김희정
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110069247A priority Critical patent/KR20130008730A/en
Publication of KR20130008730A publication Critical patent/KR20130008730A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method for forming a shallow trench isolation(STI) trench of a semiconductor device is provided to form a third trench having a third depth and to prevent an active slip phenomenon. CONSTITUTION: A pad oxide film(200) and a hard mask(300) are deposited on a semiconductor substrate(100). A first area is firstly etched to form a first trench having a first depth. A first and a second region are etched to form a second trench having a second depth. The first and the second region are etched at the same time to form a third trench having a third depth. [Reference numerals] (AA) Cell area; (BB) Ferry area

Description

Method for forming STI trench of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming an STI trench of a semiconductor device, and more particularly, to controlling a loading effect phenomenon between a cell region trench and a ferry region trench formed when the STI trench is formed in a semiconductor device. The present invention relates to a STI trench formation method of a semiconductor device capable of preventing a change.

Recently, due to the development of semiconductor process technology and the development of semiconductor design rules, the size of semiconductor devices is gradually decreasing, and effective methods for electrically insulated between fine semiconductor devices have been studied. .

In order to insulate the semiconductor devices, an isolation layer forming method for forming a shallow trench isolation (STI) trench in a semiconductor substrate between the semiconductor devices to electrically separate the devices is used.

1A to 1C are diagrams illustrating a general STI trench formation method. 1A to 1C, in the general STI trench forming method, after the pad oxide layer 20 and the hard masks 31 to 33 are deposited on the semiconductor substrate 10, the pad oxide layer 20 is etched away. The hard masks 31 to 33 are selectively etched to form cell region patterns and ferry region patterns.

The cell trench 40 and the ferrite trench may be sequentially etched by sequentially etching the pad oxide layer 20 and the semiconductor substrate 10 of the cell region and the ferry region exposed using the hard masks 31 to 33 as etch barriers. 50) (FIG. 1B, 1C).

Subsequently, an insulating film is embedded in the cell trench 40 and the ferrite trench 50 to form an isolation layer for separating the semiconductor devices.

However, in general, in the etching process for forming the STI trench, a difference occurs in the etching amount of the ferry region having a relatively less dense pattern than the cell region in which the pattern is densely formed.

This phenomenon is called a loading effect phenomenon, and is a phenomenon caused by poor etching due to insufficiency of the reaction product as compared to the wide pattern during the etching process for the fine pattern.

That is, in the general STI trench forming method, as shown in the photograph shown in FIG. 1C, a difference in depth between the cell trench 40 and the ferry trench 50 occurs due to the occurrence of a loading effect phenomenon.

As a result, the difference in depth between the cell trench 40 and the ferrite trench 50 increases the stress level of the semiconductor device during the subsequent process. Increasing the stress level causes a phenomenon such as active slip, crack, or dislocation to cause a semiconductor device to malfunction.

In order to solve the loading effect problem, a method of separating the trench between the cell region and the ferry region into a separate process is used, but the implementation of the process is complicated and the number of processes increases by several steps.

Accordingly, an object of the present invention is to provide a STI trench formation method capable of preventing a defect in a semiconductor device by controlling a loading effect phenomenon occurring when the STI trench is formed in the semiconductor device.

An STI trench forming method of a semiconductor device according to an embodiment of the present invention may include forming a hard mask on the semiconductor substrate to form trenches of a first region and a second region; First etching the semiconductor substrate of the first region to form a first trench having a first depth; And simultaneously etching the semiconductor substrates of the first region and the second region to form a second trench having a second depth and a third trench having a third depth.

The method of forming a shallow trench isolation (STI) trench of a semiconductor device according to an embodiment of the present invention has an effect of controlling a loading effect between a cell region and a ferri region.

In addition, the method for forming an STI trench of a semiconductor device according to an embodiment of the present invention may include active slip, crack, and dislocation due to an increase in a stress level that may occur during a subsequent process. There is an effect that can prevent such a phenomenon.

In addition, according to the embodiment of the present invention, the STI trench forming method of the semiconductor device may have an effect of preventing a defect such as a leakage fail of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.
1A to 1C are diagrams illustrating a conventional STI trench formation method.
2A to 2F are diagrams illustrating a STI trench formation method according to the present invention.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the embodiments of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

2A to 2F are diagrams illustrating a STI trench formation method according to the present invention. Referring to FIG. 2A, the STI trench formation method according to the present invention first deposits the pad oxide layer 200 and the hard mask 300 on the semiconductor substrate 100.

The semiconductor substrate 100 includes a first region and a second region. The first region is a cell region in which cells of a semiconductor device are to be formed, and the second region is a ferry region in which peripheral circuits are to be formed.

The pad oxide layer 200 functions as an etch stopper for the hard mask 300 during an etching process for patterning the hard mask 300.

When the deposition of the hard mask 300 is completed, a photosensitive film (not shown) is coated on the hard mask 300, and then an exposure using a device isolation exposure mask and a developing process are sequentially performed to form a photosensitive film (not shown). Pattern.

Thereafter, the hard mask 300 is sequentially etched using the patterned photoresist (not shown) as an etch mask to form a cell region pattern and a ferry region pattern on the semiconductor substrate. In this case, the hard mask 300 is etched using the pad oxide film 200 as an etch stop layer so that the pad oxide film 200 is completely exposed until the pad oxide film 200 is completely exposed.

The hard mask 300 may be implemented using a polysilicon based material having a high etching selectivity relative to an oxide based material.

In the embodiment of the present invention, the hard mask 300 is shown as an example formed of a first hard mask 310, a second hard mask 320, and a third hard mask 300, the hard mask 300 The number of films to be deposited and the type of materials may vary depending on the type of semiconductor device to be manufactured and design rules.

The STI trench forming method of the semiconductor device of the present invention may further include a pretreatment process step of oxidizing the exposed surface on the semiconductor substrate 100 when the selective etching of the hard mask 300 is completed.

The pretreatment process is a step for preventing the occurrence of scum when forming a cell pattern to be formed later. The pretreatment process uses a method of oxidizing the surface by using an O 2 plasma (Plasma).

Referring to FIG. 2B, when the formation of the hard mask 300 is completed, the photosensitive film 400 is coated on the entire surface of the semiconductor substrate 100. The photoresist layer 400 may fill all of the etched regions of the hard mask 300 formed through the steps described with reference to FIG. 2A, and deposit a predetermined height or more above the hard mask 300.

The photosensitive film 400 is preferably formed in a thickness of 500 ~ 1000 두께 or more on the top of the hard mask (300).

Referring to FIG. 2C, when the photoresist layer 400 is formed on the entire surface of the semiconductor substrate 100, an exposure mask for exposing only the photoresist layer 410 formed on the entire surface of the cell region pattern on the semiconductor substrate 100 may be used. It exposes and develops and patterns.

Thereafter, the exposed photoresist layer 410 of the cell region pattern is removed to form a Peri Close Mask 420 that opens the cell region pattern on the semiconductor substrate 100 and closes only the ferry region. The ferry closed mask 420 is a mask for preventing etching of the ferry region when the trench of the cell region is formed.

As the photoresist material for forming the ferry close mask 420, the same material as that used in the semiconductor process may be used.

Referring to FIG. 2D, when the formation of the ferry close mask 420 is completed, the pad oxide layer 200 and the semiconductor substrate 100 of the open cell region pattern are sequentially first-etched to sequentially set a first depth ( A first cell trench 500 having D1) is formed.

In this case, the etching depth D1 of the first cell trench 500 may be changed according to a design and a process environment.

Referring to FIG. 2E, when the first trench etching is completed, the ferry close mask 420 formed on the entire surface of the ferry region pattern is removed to open the ferry region pattern.

The ferry method of removing a closed mask 420 in-situ (in-situ) method as O 2, or removed by a plasma treatment, exo-situ (ex-situ) O 2 plasma treatment using the method in the photoresist stripper (stripper) The removal method can be used.

Referring to FIG. 2F, when the removal of the ferry close mask 420 is completed, the pad oxide layer 200 exposed on the ferry region pattern is removed.

The second cell trench 500 ′ and the third depth D3 having the second depth D1 + D2 are simultaneously etched by simultaneously etching the semiconductor substrate 100 of the exposed cell region pattern and the ferry region pattern. The formation of the trench trench 600 having the STI trenches for the semiconductor substrate is completed.

That is, the first trench is etched by a predetermined depth D1 for the cell trench having a relatively slower etching speed than the ferry region, and then the etching is performed simultaneously with the ferry trench 600 during the second trench etch. By further etching (D2), the cell trench depth D1 + D2 to be finally obtained can be obtained.

In this case, etching of the semiconductor substrate 100 may be performed until the second cell trench 500 ′ is set to a predetermined depth D1 + D2. Even if the depth of the second cell trench 500 'is etched by the set depth D1 + D2, the ferrite trench 600 may be more deeply etched. On the contrary, even if the etching process proceeds until the ferry trench 600 reaches the set depth D3, the depth of the second cell trench 500 ′ finally formed may be sufficiently secured.

The final depth D1 + D2 of the cell trench 500 may be about 2500 to 3000 ~, but may vary according to process conditions and design conditions.

In addition, in the embodiment of the present invention, the depth D1 + D2 of the second formed cell trench 500 'is preferably formed deeper than the depth D3 of the perimeter trench 600.

In summary, by adjusting the etching depth D1 of the first cell trench 500 through the first trench etching step illustrated in FIG. 2D, the second cell trench 500 due to the loading effect generated when the STI trench is formed. ') And the difference between the etching depth of the trench trench 600 may be controlled. As a result, failure of the semiconductor device due to the loading effect occurring when the STI trench is formed in the semiconductor device can be prevented.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

100: semiconductor substrate
200: pad oxide film
300: hard mask
420: Perry Close Mask
500: first cell trench
500 ': second cell trench
600: Perry Trench

Claims (12)

Forming a hard mask on the semiconductor substrate to form trenches of the first region and the second region;
First etching the first region of the semiconductor substrate to form a first trench having a first depth; And
Simultaneously etching the first region and the second region of the semiconductor substrate to form a second trench having a second depth and a third trench having a third depth. The method of claim 1,
Forming the first trench,
Forming a peri close mask to open the first region and close only the second region before the first etching; And
And removing the ferry closed mask to open a second region after the first etching is completed. The method of claim 2,
STI trench formation method of the semiconductor device,
And a pretreatment step for oxidizing the exposed surface on the semiconductor substrate prior to forming the ferry close mask. The method of claim 3,
The pretreatment step, STI trench formation method of a semiconductor device using O 2 plasma. The method of claim 2,
Forming the ferry close mask,
Applying a photoresist film to both the first region and the second region on the semiconductor substrate; And
And removing only the photoresist portion applied to the second region and removing the photoresist portion applied to the first region. The method of claim 2,
The ferry close mask is formed on the hard mask to the thickness of 500 ~ 1000 Å thickness STI trench formation method of a semiconductor device. The method of claim 2,
Removing the ferry close mask,
A method of forming an STI trench in a semiconductor device, which step is performed using either an in-situ or an ex-situ method. The method of claim 1,
Forming the hard mask,
Sequentially depositing a pad oxide film and a hard mask on the semiconductor substrate; And
And selectively etching the hard mask by using the pad oxide layer as an etch stop layer. 9. The method of claim 8,
The hard mask may be formed of a material having a larger etching selectivity than that of the pad oxide layer. 10. The method of claim 9,
The hard mask is STI trench formation method of a semiconductor device which is a material containing polysilicon. The method of claim 1,
The second trench depth formed in the first region is formed deeper than the third trench depth formed in the second region. The method of claim 1,
And the first region is a cell region and the second region is a ferry region.
KR1020110069247A 2011-07-13 2011-07-13 Method for forming sti trench of semiconductor device KR20130008730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110069247A KR20130008730A (en) 2011-07-13 2011-07-13 Method for forming sti trench of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110069247A KR20130008730A (en) 2011-07-13 2011-07-13 Method for forming sti trench of semiconductor device

Publications (1)

Publication Number Publication Date
KR20130008730A true KR20130008730A (en) 2013-01-23

Family

ID=47838635

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110069247A KR20130008730A (en) 2011-07-13 2011-07-13 Method for forming sti trench of semiconductor device

Country Status (1)

Country Link
KR (1) KR20130008730A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336849A (en) * 2014-06-12 2016-02-17 中芯国际集成电路制造(上海)有限公司 Formation method of MRAM device
CN106298629A (en) * 2015-05-29 2017-01-04 旺宏电子股份有限公司 Semiconductor element and manufacture method thereof
CN107994027A (en) * 2017-11-21 2018-05-04 长江存储科技有限责任公司 A kind of mitigation method that load effect influences in SONO etchings
CN109110726A (en) * 2018-07-03 2019-01-01 北京大学 A method of improving high-aspect-ratio tungsten alloy etching homogeneity

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336849A (en) * 2014-06-12 2016-02-17 中芯国际集成电路制造(上海)有限公司 Formation method of MRAM device
CN106298629A (en) * 2015-05-29 2017-01-04 旺宏电子股份有限公司 Semiconductor element and manufacture method thereof
CN107994027A (en) * 2017-11-21 2018-05-04 长江存储科技有限责任公司 A kind of mitigation method that load effect influences in SONO etchings
CN109110726A (en) * 2018-07-03 2019-01-01 北京大学 A method of improving high-aspect-ratio tungsten alloy etching homogeneity
CN109110726B (en) * 2018-07-03 2021-06-29 北京大学 Method for improving etching uniformity of high-depth-to-width-ratio tungsten alloy

Similar Documents

Publication Publication Date Title
US9159579B2 (en) Lithography using multilayer spacer for reduced spacer footing
KR100822581B1 (en) Method of manufacturing a flash memory device
KR20130008730A (en) Method for forming sti trench of semiconductor device
CN103390551B (en) The manufacture method of semiconductor device pattern structure
KR100811265B1 (en) Method of fabricating the landing plug contact in semicondutor device
KR101344019B1 (en) Method of implatating ions
KR100525925B1 (en) Method for forming a trench in semiconductor device
KR100807074B1 (en) Method for fabrication a semiconductor device
KR20060136174A (en) Method for manufacturing fine pattern
JP2007180475A (en) Method of manufacturing semiconductor device utilizing amorphous carbon
US7645679B2 (en) Method for forming isolation layer in semiconductor devices
KR20070000204A (en) Method for manufacturing fine pattern
KR20130022950A (en) Semiconductor device and method for manufacturing the same
KR100751687B1 (en) Method for fabricating flash memory device
KR20120003715A (en) Method for manufacturing semiconductor device with buried gate
KR100232198B1 (en) Method of forming an element isolation region in a semiconductor device
KR20090026683A (en) Method for forming pattern of semiconductor device
KR20080002529A (en) Method for manufacturing semiconductor device
KR0161727B1 (en) Element isolation method of semiconductor device
KR101095066B1 (en) Method for manufacturing semiconductor device
KR20100074630A (en) Method for forming patterns of a semiconductor device
KR20110109751A (en) Method for fabricating semiconductor device
KR100568424B1 (en) Method for forming silicide of semiconductor device
CN116895600A (en) Semiconductor device and manufacturing method thereof
KR20080000894A (en) Method for fabricating semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination